Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66686758	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32412818

1

T1

137534

T2

2886

T3

122145

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14994720	1			T1	53985		T2	1711		T3	47688
values[0x0]	40942232	1			T1	191125		T2	3656		T3	168237
values[0x1]	43162624	1			T1	191303		T2	3536		T3	167963

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56852382	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

42247194

1

T1

174293

T2

3644

T3

153790

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	687657	1			T1	1642		T2	43		T3	1491
valid_sources[0x01]	318106	1			T1	1656		T2	34		T3	1467
valid_sources[0x02]	320040	1			T1	1736		T2	40		T3	1511
valid_sources[0x03]	331037	1			T1	1700		T2	32		T3	1499
valid_sources[0x04]	323745	1			T1	1745		T2	22		T3	1553
valid_sources[0x05]	322577	1			T1	1668		T2	28		T3	1484
valid_sources[0x06]	330889	1			T1	1684		T2	30		T3	1496
valid_sources[0x07]	604069	1			T1	1776		T2	45		T3	1514
valid_sources[0x08]	317820	1			T1	1694		T2	49		T3	1498
valid_sources[0x09]	784937	1			T1	1668		T2	36		T3	1548
valid_sources[0x0a]	354482	1			T1	1729		T2	34		T3	1453
valid_sources[0x0b]	333630	1			T1	1677		T2	27		T3	1489
valid_sources[0x0c]	318050	1			T1	1694		T2	34		T3	1537
valid_sources[0x0d]	317881	1			T1	1724		T2	21		T3	1429
valid_sources[0x0e]	1284600	1			T1	1687		T2	39		T3	1491
valid_sources[0x0f]	311856	1			T1	1715		T2	30		T3	1496
valid_sources[0x10]	317480	1			T1	1670		T2	40		T3	1522
valid_sources[0x11]	330257	1			T1	1763		T2	55		T3	1491
valid_sources[0x12]	318403	1			T1	1652		T2	37		T3	1436
valid_sources[0x13]	323002	1			T1	1653		T2	28		T3	1434
valid_sources[0x14]	321528	1			T1	1703		T2	34		T3	1447
valid_sources[0x15]	312575	1			T1	1786		T2	43		T3	1497
valid_sources[0x16]	333650	1			T1	1680		T2	40		T3	1459
valid_sources[0x17]	317797	1			T1	1717		T2	20		T3	1527
valid_sources[0x18]	320109	1			T1	1749		T2	29		T3	1470
valid_sources[0x19]	313980	1			T1	1756		T2	37		T3	1490
valid_sources[0x1a]	316715	1			T1	1779		T2	40		T3	1459
valid_sources[0x1b]	320534	1			T1	1602		T2	44		T3	1458
valid_sources[0x1c]	314901	1			T1	1695		T2	47		T3	1541
valid_sources[0x1d]	323429	1			T1	1676		T2	39		T3	1507
valid_sources[0x1e]	586476	1			T1	1758		T2	31		T3	1532
valid_sources[0x1f]	325331	1			T1	1689		T2	35		T3	1470
valid_sources[0x20]	315457	1			T1	1740		T2	27		T3	1471
valid_sources[0x21]	320253	1			T1	1730		T2	33		T3	1554
valid_sources[0x22]	755755	1			T1	1749		T2	46		T3	1436
valid_sources[0x23]	323765	1			T1	1736		T2	25		T3	1483
valid_sources[0x24]	312912	1			T1	1673		T2	24		T3	1510
valid_sources[0x25]	316273	1			T1	1772		T2	52		T3	1528
valid_sources[0x26]	318821	1			T1	1648		T2	23		T3	1490
valid_sources[0x27]	318772	1			T1	1695		T2	41		T3	1503
valid_sources[0x28]	805199	1			T1	1677		T2	29		T3	1542
valid_sources[0x29]	312926	1			T1	1650		T2	41		T3	1500
valid_sources[0x2a]	312514	1			T1	1806		T2	39		T3	1490
valid_sources[0x2b]	323359	1			T1	1690		T2	41		T3	1533
valid_sources[0x2c]	322975	1			T1	1775		T2	29		T3	1532
valid_sources[0x2d]	316267	1			T1	1637		T2	22		T3	1502
valid_sources[0x2e]	318178	1			T1	1748		T2	39		T3	1500
valid_sources[0x2f]	634978	1			T1	1646		T2	29		T3	1440
valid_sources[0x30]	321882	1			T1	1633		T2	30		T3	1540
valid_sources[0x31]	346926	1			T1	1653		T2	52		T3	1487
valid_sources[0x32]	312054	1			T1	1664		T2	39		T3	1467
valid_sources[0x33]	320337	1			T1	1713		T2	43		T3	1496
valid_sources[0x34]	322317	1			T1	1688		T2	49		T3	1469
valid_sources[0x35]	313769	1			T1	1715		T2	50		T3	1550
valid_sources[0x36]	327189	1			T1	1678		T2	29		T3	1506
valid_sources[0x37]	321629	1			T1	1764		T2	35		T3	1464
valid_sources[0x38]	323482	1			T1	1709		T2	35		T3	1503
valid_sources[0x39]	310437	1			T1	1633		T2	29		T3	1486
valid_sources[0x3a]	321772	1			T1	1744		T2	27		T3	1480
valid_sources[0x3b]	674832	1			T1	1667		T2	34		T3	1536
valid_sources[0x3c]	316990	1			T1	1632		T2	51		T3	1476
valid_sources[0x3d]	325597	1			T1	1795		T2	40		T3	1476
valid_sources[0x3e]	322188	1			T1	1713		T2	53		T3	1503
valid_sources[0x3f]	324456	1			T1	1704		T2	11		T3	1440
valid_sources[0x40]	316330	1			T1	1755		T2	39		T3	1482
valid_sources[0x41]	318112	1			T1	1712		T2	44		T3	1498
valid_sources[0x42]	323748	1			T1	1541		T2	42		T3	1473
valid_sources[0x43]	592081	1			T1	1689		T2	29		T3	1485
valid_sources[0x44]	316965	1			T1	1660		T2	23		T3	1450
valid_sources[0x45]	344403	1			T1	1748		T2	49		T3	1504
valid_sources[0x46]	314554	1			T1	1687		T2	37		T3	1515
valid_sources[0x47]	310253	1			T1	1605		T2	30		T3	1376
valid_sources[0x48]	333117	1			T1	1657		T2	31		T3	1503
valid_sources[0x49]	320792	1			T1	1667		T2	50		T3	1510
valid_sources[0x4a]	357181	1			T1	1691		T2	39		T3	1549
valid_sources[0x4b]	312490	1			T1	1628		T2	42		T3	1494
valid_sources[0x4c]	329207	1			T1	1731		T2	48		T3	1521
valid_sources[0x4d]	322366	1			T1	1830		T2	43		T3	1493
valid_sources[0x4e]	323573	1			T1	1627		T2	37		T3	1549
valid_sources[0x4f]	335832	1			T1	1723		T2	41		T3	1643
valid_sources[0x50]	315563	1			T1	1779		T2	33		T3	1531
valid_sources[0x51]	331337	1			T1	1739		T2	27		T3	1471
valid_sources[0x52]	328914	1			T1	1717		T2	24		T3	1487
valid_sources[0x53]	333561	1			T1	1697		T2	30		T3	1510
valid_sources[0x54]	334280	1			T1	1695		T2	37		T3	1516
valid_sources[0x55]	318212	1			T1	1673		T2	50		T3	1503
valid_sources[0x56]	317578	1			T1	1693		T2	33		T3	1475
valid_sources[0x57]	686861	1			T1	1622		T2	19		T3	1496
valid_sources[0x58]	338184	1			T1	1692		T2	40		T3	1450
valid_sources[0x59]	313734	1			T1	1614		T2	40		T3	1516
valid_sources[0x5a]	718886	1			T1	1780		T2	38		T3	1561
valid_sources[0x5b]	316194	1			T1	1754		T2	37		T3	1609
valid_sources[0x5c]	321312	1			T1	1648		T2	31		T3	1418
valid_sources[0x5d]	334055	1			T1	1659		T2	25		T3	1409
valid_sources[0x5e]	321720	1			T1	1631		T2	40		T3	1525
valid_sources[0x5f]	321548	1			T1	1751		T2	26		T3	1527
valid_sources[0x60]	318945	1			T1	1681		T2	36		T3	1388
valid_sources[0x61]	634112	1			T1	1701		T2	29		T3	1393
valid_sources[0x62]	315123	1			T1	1669		T2	33		T3	1522
valid_sources[0x63]	321472	1			T1	1731		T2	42		T3	1508
valid_sources[0x64]	322094	1			T1	1627		T2	36		T3	1456
valid_sources[0x65]	780257	1			T1	1696		T2	43		T3	1449
valid_sources[0x66]	526303	1			T1	1676		T2	38		T3	1481
valid_sources[0x67]	316565	1			T1	1674		T2	33		T3	1485
valid_sources[0x68]	317806	1			T1	1690		T2	41		T3	1518
valid_sources[0x69]	318271	1			T1	1730		T2	35		T3	1585
valid_sources[0x6a]	327705	1			T1	1758		T2	32		T3	1505
valid_sources[0x6b]	330607	1			T1	1684		T2	24		T3	1432
valid_sources[0x6c]	784835	1			T1	1657		T2	32		T3	1523
valid_sources[0x6d]	329919	1			T1	1563		T2	46		T3	1479
valid_sources[0x6e]	319892	1			T1	1754		T2	38		T3	1451
valid_sources[0x6f]	799906	1			T1	1760		T2	33		T3	1482
valid_sources[0x70]	320712	1			T1	1741		T2	35		T3	1477
valid_sources[0x71]	313011	1			T1	1744		T2	40		T3	1475
valid_sources[0x72]	315084	1			T1	1691		T2	29		T3	1518
valid_sources[0x73]	322121	1			T1	1582		T2	33		T3	1537
valid_sources[0x74]	314625	1			T1	1689		T2	41		T3	1493
valid_sources[0x75]	783837	1			T1	1618		T2	24		T3	1516
valid_sources[0x76]	541259	1			T1	1638		T2	41		T3	1474
valid_sources[0x77]	317229	1			T1	1680		T2	52		T3	1468
valid_sources[0x78]	325044	1			T1	1785		T2	32		T3	1545
valid_sources[0x79]	333066	1			T1	1732		T2	45		T3	1556
valid_sources[0x7a]	591431	1			T1	1708		T2	30		T3	1464
valid_sources[0x7b]	317139	1			T1	1609		T2	22		T3	1506
valid_sources[0x7c]	336776	1			T1	1715		T2	46		T3	1452
valid_sources[0x7d]	321271	1			T1	1589		T2	37		T3	1520
valid_sources[0x7e]	314554	1			T1	1808		T2	25		T3	1513
valid_sources[0x7f]	326210	1			T1	1691		T2	44		T3	1569
valid_sources[0x80]	322705	1			T1	1764		T2	46		T3	1526

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7474766

1

T1

26868

T2

860

T3

24148

values[0x0]

all_enables

biggest_size

15722031

1

T1

70924

T2

1297

T3

62387

values[0x1]

all_enables

biggest_size

9216021

1

T1

39742

T2

729

T3

35610