Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T10,T58
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	12706	0	0
DisabledNoTrigBkwd_A	2147483647	820968	0	0
DisabledNoTrigFwd_A	2147483647	1652560585	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12706	0	0
T5	2689	468	0	0
T6	389510	0	0	0
T7	17483	0	0	0
T8	39969	0	0	0
T9	16802	0	0	0
T10	7294	1332	0	0
T14	292046	0	0	0
T15	86217	0	0	0
T35	416300	0	0	0
T36	262402	0	0	0
T37	762492	0	0	0
T38	59655	0	0	0
T39	80954	0	0	0
T40	191424	0	0	0
T48	184251	0	0	0
T58	1047	272	0	0
T81	183436	0	0	0
T112	40742	0	0	0
T193	0	558	0	0
T194	3100	681	0	0
T195	0	439	0	0
T196	0	186	0	0
T197	0	532	0	0
T198	0	869	0	0
T199	0	494	0	0
T200	0	296	0	0
T201	0	714	0	0
T202	0	745	0	0
T203	0	298	0	0
T204	0	226	0	0
T205	0	639	0	0
T206	0	393	0	0
T207	0	1203	0	0
T208	0	1110	0	0
T209	0	1251	0	0
T210	532670	0	0	0
T211	416731	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	820968	0	0
T1	1469116	1099	0	0
T2	449100	103	0	0
T3	1405776	4686	0	0
T4	237532	44	0	0
T5	10756	9	0	0
T6	1558040	4768	0	0
T7	69932	26	0	0
T8	159876	0	0	0
T9	67208	6	0	0
T10	14588	36	0	0
T14	0	3587	0	0
T16	0	4209	0	0
T35	0	1205	0	0
T36	0	1080	0	0
T37	0	11295	0	0
T38	0	83	0	0
T39	0	62	0	0
T40	0	1	0	0
T41	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1652560585	0	0
T1	1469116	1112497	0	0
T2	449100	210067	0	0
T3	1405776	706386	0	0
T4	237532	139163	0	0
T5	10756	8182	0	0
T6	1558040	791074	0	0
T7	69932	29630	0	0
T8	159876	58695	0	0
T9	67208	47233	0	0
T10	14588	8282	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T196,T200
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	709951444	4982	0	0
DisabledNoTrigBkwd_A	709951444	264214	0	0
DisabledNoTrigFwd_A	709951444	346347984	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	4982	0	0
T10	3647	1332	0	0
T14	146023	0	0	0
T15	86217	0	0	0
T35	208150	0	0	0
T36	131201	0	0	0
T37	381246	0	0	0
T38	59655	0	0	0
T39	80954	0	0	0
T40	191424	0	0	0
T58	1047	0	0	0
T196	0	186	0	0
T200	0	296	0	0
T201	0	714	0	0
T207	0	1203	0	0
T209	0	1251	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	264214	0	0
T1	367279	992	0	0
T2	112275	10	0	0
T3	351444	0	0	0
T4	59383	44	0	0
T5	2689	0	0	0
T6	389510	2933	0	0
T7	17483	13	0	0
T8	39969	0	0	0
T9	16802	6	0	0
T10	3647	36	0	0
T14	0	173	0	0
T35	0	27	0	0
T36	0	670	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	346347984	0	0
T1	367279	17601	0	0
T2	112275	86411	0	0
T3	351444	351438	0	0
T4	59383	8203	0	0
T5	2689	2030	0	0
T6	389510	6776	0	0
T7	17483	4559	0	0
T8	39969	5814	0	0
T9	16802	15345	0	0
T10	3647	2050	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T197,T203
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	709951444	2801	0	0
DisabledNoTrigBkwd_A	709951444	191767	0	0
DisabledNoTrigFwd_A	709951444	421168866	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	2801	0	0
T5	2689	468	0	0
T6	389510	0	0	0
T7	17483	0	0	0
T8	39969	0	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	146023	0	0	0
T35	208150	0	0	0
T36	131201	0	0	0
T37	381246	0	0	0
T197	0	532	0	0
T203	0	298	0	0
T206	0	393	0	0
T208	0	1110	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	191767	0	0
T1	367279	2	0	0
T2	112275	35	0	0
T3	351444	2279	0	0
T4	59383	0	0	0
T5	2689	9	0	0
T6	389510	1826	0	0
T7	17483	12	0	0
T8	39969	0	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	0	167	0	0
T35	0	2	0	0
T36	0	410	0	0
T37	0	2605	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	421168866	0	0
T1	367279	366002	0	0
T2	112275	8201	0	0
T3	351444	2007	0	0
T4	59383	12318	0	0
T5	2689	2036	0	0
T6	389510	7262	0	0
T7	17483	7018	0	0
T8	39969	10859	0	0
T9	16802	16726	0	0
T10	3647	2063	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T194,T198,T204
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	709951444	2415	0	0
DisabledNoTrigBkwd_A	709951444	187311	0	0
DisabledNoTrigFwd_A	709951444	447899869	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	2415	0	0
T48	184251	0	0	0
T81	183436	0	0	0
T112	40742	0	0	0
T194	3100	681	0	0
T195	1221	0	0	0
T198	0	869	0	0
T204	0	226	0	0
T205	0	639	0	0
T210	532670	0	0	0
T211	416731	0	0	0
T212	138662	0	0	0
T213	185754	0	0	0
T214	13187	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	187311	0	0
T1	367279	2	0	0
T2	112275	55	0	0
T3	351444	3	0	0
T4	59383	0	0	0
T5	2689	0	0	0
T6	389510	3	0	0
T7	17483	0	0	0
T8	39969	0	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	0	1301	0	0
T16	0	4209	0	0
T37	0	6039	0	0
T38	0	83	0	0
T39	0	8	0	0
T41	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	447899869	0	0
T1	367279	365434	0	0
T2	112275	8465	0	0
T3	351444	350897	0	0
T4	59383	59321	0	0
T5	2689	2050	0	0
T6	389510	388518	0	0
T7	17483	17431	0	0
T8	39969	39881	0	0
T9	16802	14336	0	0
T10	3647	2077	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T58,T193,T195
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	709951444	2508	0	0
DisabledNoTrigBkwd_A	709951444	177676	0	0
DisabledNoTrigFwd_A	709951444	437143866	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	2508	0	0
T16	352686	0	0	0
T21	16230	0	0	0
T41	187016	0	0	0
T58	1047	272	0	0
T62	32134	0	0	0
T63	153799	0	0	0
T96	289330	0	0	0
T97	29998	0	0	0
T98	153817	0	0	0
T99	122857	0	0	0
T193	0	558	0	0
T195	0	439	0	0
T199	0	494	0	0
T202	0	745	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	177676	0	0
T1	367279	103	0	0
T2	112275	3	0	0
T3	351444	2404	0	0
T4	59383	0	0	0
T5	2689	0	0	0
T6	389510	6	0	0
T7	17483	1	0	0
T8	39969	0	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	0	1946	0	0
T35	0	1176	0	0
T37	0	2651	0	0
T39	0	54	0	0
T40	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	437143866	0	0
T1	367279	363460	0	0
T2	112275	106990	0	0
T3	351444	2044	0	0
T4	59383	59321	0	0
T5	2689	2066	0	0
T6	389510	388518	0	0
T7	17483	622	0	0
T8	39969	2141	0	0
T9	16802	826	0	0
T10	3647	2092	0	0