Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T2,T7
1	1	1	Covered	T1,T7,T8

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T14,T15,T16
1	0	Covered	T7,T14,T16

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T8
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T7,T14,T16

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T17
1	1	Covered	T14,T15,T16

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T14

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T7,T8

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T7,T8
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T18,T19,T20
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T3,T21,T19
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T3,T18,T22
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T6,T23,T24
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T2,T3
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T7,T8,T14
TimeoutSt->Phase0St	172	Covered	T1,T7,T14

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T7,T14,T15
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T8
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T14
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T21,T19
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T18,T22
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T6,T23,T24
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1119	0	0
CheckAccumTrig0_A	2147483647	2321	0	0
CheckAccumTrig1_A	2147483647	106	0	0
CheckClr_A	2147483647	1076	0	0
CheckEn_A	2147483647	1276396492	0	0
CheckPhase0_A	2147483647	2649	0	0
CheckPhase1_A	2147483647	2585	0	0
CheckPhase2_A	2147483647	2541	0	0
CheckPhase3_A	2147483647	2502	0	0
CheckTimeout0_A	2147483647	5861	0	0
CheckTimeoutSt1_A	2147483647	592420	0	0
CheckTimeoutSt2_A	2147483647	5480	0	0
CheckTimeoutStTrig_A	2147483647	271	0	0
ErrorStAllEscAsserted_A	2147483647	5815	0	0
ErrorStIsTerminal_A	2147483647	4855	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1119	0	0
T11	240768	110	0	0
T12	0	242	0	0
T13	0	285	0	0
T23	3181852	0	0	0
T25	0	294	0	0
T26	0	188	0	0
T27	46132	0	0	0
T28	275056	0	0	0
T29	768284	0	0	0
T30	15808	0	0	0
T31	41516	0	0	0
T32	2124660	0	0	0
T33	160080	0	0	0
T34	42888	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2321	0	0
T1	1469116	5	0	0
T2	449100	11	0	0
T3	1405776	11	0	0
T4	237532	5	0	0
T5	10756	1	0	0
T6	1558040	7	0	0
T7	69932	5	0	0
T8	159876	0	0	0
T9	67208	1	0	0
T10	14588	1	0	0
T14	0	18	0	0
T16	0	2	0	0
T35	0	3	0	0
T36	0	2	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	6	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	106	0	0
T7	17483	1	0	0
T8	39969	0	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	292046	1	0	0
T15	172434	0	0	0
T16	352686	1	0	0
T19	193044	4	0	0
T22	154332	0	0	0
T32	0	1	0	0
T35	208150	0	0	0
T36	262402	0	0	0
T37	762492	0	0	0
T38	119310	0	0	0
T39	80954	0	0	0
T40	191424	0	0	0
T41	187016	0	0	0
T42	945615	2	0	0
T43	0	1	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	5	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	0	3	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	1047	0	0	0
T59	92410	0	0	0
T60	15264	0	0	0
T61	66983	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1076	0	0
T1	367279	0	0	0
T2	224550	7	0	0
T3	1054332	5	0	0
T4	237532	4	0	0
T5	10756	0	0	0
T6	1558040	2	0	0
T7	69932	3	0	0
T8	159876	0	0	0
T9	67208	0	0	0
T10	14588	0	0	0
T14	292046	6	0	0
T16	0	8	0	0
T18	0	4	0	0
T19	0	1	0	0
T21	0	1	0	0
T35	624450	0	0	0
T36	131201	0	0	0
T37	0	1	0	0
T42	0	14	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	7	0	0
T69	0	5	0	0
T70	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1276396492	0	0
T1	1469116	47299	0	0
T2	449100	126619	0	0
T3	1405776	706385	0	0
T4	237532	139161	0	0
T5	10756	8182	0	0
T6	1558040	404666	0	0
T7	69932	29629	0	0
T8	159876	58694	0	0
T9	67208	32700	0	0
T10	14588	8282	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2649	0	0
T1	1469116	6	0	0
T2	449100	11	0	0
T3	1405776	11	0	0
T4	237532	5	0	0
T5	10756	1	0	0
T6	1558040	7	0	0
T7	69932	6	0	0
T8	159876	0	0	0
T9	67208	1	0	0
T10	14588	1	0	0
T14	0	20	0	0
T16	0	3	0	0
T35	0	3	0	0
T36	0	2	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	6	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2585	0	0
T1	1469116	6	0	0
T2	449100	11	0	0
T3	1405776	9	0	0
T4	237532	5	0	0
T5	10756	1	0	0
T6	1558040	7	0	0
T7	69932	6	0	0
T8	159876	0	0	0
T9	67208	1	0	0
T10	14588	1	0	0
T14	0	20	0	0
T16	0	3	0	0
T35	0	3	0	0
T36	0	2	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	6	0	0
T41	0	1	0	0
T58	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2541	0	0
T1	1469116	6	0	0
T2	449100	11	0	0
T3	1405776	8	0	0
T4	237532	5	0	0
T5	10756	1	0	0
T6	1558040	7	0	0
T7	69932	6	0	0
T8	159876	0	0	0
T9	67208	1	0	0
T10	14588	1	0	0
T14	0	20	0	0
T16	0	3	0	0
T35	0	3	0	0
T36	0	2	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	6	0	0
T41	0	1	0	0
T58	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2502	0	0
T1	1469116	6	0	0
T2	449100	11	0	0
T3	1405776	7	0	0
T4	237532	5	0	0
T5	10756	1	0	0
T6	1558040	6	0	0
T7	69932	6	0	0
T8	159876	0	0	0
T9	67208	1	0	0
T10	14588	1	0	0
T14	0	20	0	0
T16	0	3	0	0
T35	0	3	0	0
T36	0	2	0	0
T37	0	3	0	0
T38	0	1	0	0
T39	0	5	0	0
T41	0	1	0	0
T58	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5861	0	0
T1	367279	1	0	0
T2	112275	0	0	0
T3	351444	0	0	0
T4	59383	0	0	0
T5	2689	0	0	0
T6	389510	0	0	0
T7	52449	2	0	0
T8	119907	15	0	0
T9	50406	0	0	0
T10	10941	0	0	0
T14	438069	34	0	0
T15	258651	6	0	0
T16	352686	29	0	0
T19	0	4	0	0
T22	0	1	0	0
T27	0	3	0	0
T29	0	10	0	0
T31	0	1	0	0
T35	416300	0	0	0
T36	393603	0	0	0
T37	1143738	3	0	0
T38	178965	0	0	0
T39	80954	0	0	0
T40	191424	0	0	0
T41	187016	0	0	0
T42	0	12	0	0
T58	1047	0	0	0
T61	0	2	0	0
T66	0	1	0	0
T68	0	5	0	0
T71	0	4	0	0
T72	0	1	0	0
T73	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	592420	0	0
T1	367279	2	0	0
T2	112275	0	0	0
T3	351444	0	0	0
T4	59383	0	0	0
T5	2689	0	0	0
T6	389510	0	0	0
T7	34966	15	0	0
T8	119907	2287	0	0
T9	50406	0	0	0
T10	10941	0	0	0
T14	438069	1266	0	0
T15	258651	723	0	0
T16	352686	5624	0	0
T19	0	548	0	0
T22	0	40	0	0
T27	0	409	0	0
T29	0	2280	0	0
T31	0	50	0	0
T35	416300	0	0	0
T36	393603	0	0	0
T37	1143738	320	0	0
T38	178965	0	0	0
T39	161908	0	0	0
T40	191424	0	0	0
T41	187016	0	0	0
T42	0	4155	0	0
T58	1047	0	0	0
T61	0	282	0	0
T66	0	53	0	0
T68	0	629	0	0
T71	0	521	0	0
T72	0	73	0	0
T73	0	153	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5480	0	0
T7	17483	1	0	0
T8	119907	15	0	0
T9	50406	0	0	0
T10	10941	0	0	0
T14	584092	32	0	0
T15	344868	5	0	0
T16	352686	22	0	0
T19	0	1	0	0
T22	0	1	0	0
T23	0	2	0	0
T27	0	3	0	0
T29	0	359	0	0
T31	0	2	0	0
T32	0	6	0	0
T35	624450	0	0	0
T36	524804	0	0	0
T37	1524984	3	0	0
T38	238620	0	0	0
T39	242862	0	0	0
T40	191424	0	0	0
T41	187016	0	0	0
T42	0	5	0	0
T43	0	2	0	0
T58	1047	0	0	0
T61	0	2	0	0
T66	0	1	0	0
T68	0	5	0	0
T71	0	2	0	0
T72	0	1	0	0
T73	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	271	0	0
T14	146023	1	0	0
T15	86217	1	0	0
T16	705372	3	0	0
T19	193044	0	0	0
T22	154332	0	0	0
T23	0	2	0	0
T27	0	2	0	0
T29	0	1	0	0
T32	0	6	0	0
T33	0	3	0	0
T36	131201	0	0	0
T37	381246	0	0	0
T38	59655	0	0	0
T39	80954	0	0	0
T40	191424	0	0	0
T41	187016	0	0	0
T42	945615	2	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T58	1047	0	0	0
T59	92410	0	0	0
T60	15264	0	0	0
T61	66983	0	0	0
T62	32134	0	0	0
T67	14815	0	0	0
T68	679182	0	0	0
T69	102092	0	0	0
T70	561143	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	4	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	5	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5815	0	0
T11	240768	726	0	0
T12	0	1403	0	0
T13	0	1467	0	0
T23	3181852	0	0	0
T25	0	1475	0	0
T26	0	744	0	0
T27	46132	0	0	0
T28	275056	0	0	0
T29	768284	0	0	0
T30	15808	0	0	0
T31	41516	0	0	0
T32	2124660	0	0	0
T33	160080	0	0	0
T34	42888	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4855	0	0
T11	240768	606	0	0
T12	0	1163	0	0
T13	0	1227	0	0
T23	3181852	0	0	0
T25	0	1235	0	0
T26	0	624	0	0
T27	46132	0	0	0
T28	275056	0	0	0
T29	768284	0	0	0
T30	15808	0	0	0
T31	41516	0	0	0
T32	2124660	0	0	0
T33	160080	0	0	0
T34	42888	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1469116	1469080	0	0
T2	449100	448772	0	0
T3	1405776	1405752	0	0
T4	237532	237284	0	0
T5	10756	10376	0	0
T6	1558040	1558016	0	0
T7	69932	69724	0	0
T8	159876	159524	0	0
T9	67208	66904	0	0
T10	14588	14364	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1469116	1469080	0	0
T2	449100	448772	0	0
T3	1405776	1405752	0	0
T4	237532	237284	0	0
T5	10756	10376	0	0
T6	1558040	1558016	0	0
T7	69932	69724	0	0
T8	159876	159524	0	0
T9	67208	66904	0	0
T10	14588	14364	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T2,T7
1	1	1	Covered	T7,T8,T14

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T8,T14,T15
0	1	Covered	T42,T27,T32
1	0	Covered	T7,T16,T43

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T8,T14,T15
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T7,T16,T43

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T14
1	0	Not Covered
1	1	Covered	T42,T27,T32

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T2,T3,T5

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T6

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T42,T19

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T16

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T5,T35,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T5,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T5,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T7,T8,T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T7,T8,T14
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T31,T46,T80
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T3,T81,T82
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T3,T24,T83
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T6,T51,T54
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T3,T7
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T8,T14,T15
TimeoutSt->Phase0St	172	Covered	T7,T16,T42

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T14
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T7,T16,T42
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T8,T14,T15
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T8,T14,T15
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T31,T46,T80
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T81,T84
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T24,T83
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T6,T51,T54
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	709951444	255	0	0
CheckAccumTrig0_A	709951444	508	0	0
CheckAccumTrig1_A	709951444	15	0	0
CheckClr_A	709951444	237	0	0
CheckEn_A	709746788	305742286	0	0
CheckPhase0_A	709951444	589	0	0
CheckPhase1_A	709951444	576	0	0
CheckPhase2_A	709951444	566	0	0
CheckPhase3_A	709951444	556	0	0
CheckTimeout0_A	709951444	1105	0	0
CheckTimeoutSt1_A	709951444	133481	0	0
CheckTimeoutSt2_A	709951444	1020	0	0
CheckTimeoutStTrig_A	709951444	69	0	0
ErrorStAllEscAsserted_A	709951444	1415	0	0
ErrorStIsTerminal_A	709951444	1175	0	0
EscStateOut_A	709745106	709674376	0	0
u_state_regs_A	709951444	709778722	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	255	0	0
T11	60192	10	0	0
T12	0	66	0	0
T13	0	61	0	0
T23	795463	0	0	0
T25	0	67	0	0
T26	0	51	0	0
T27	11533	0	0	0
T28	68764	0	0	0
T29	192071	0	0	0
T30	3952	0	0	0
T31	10379	0	0	0
T32	531165	0	0	0
T33	40020	0	0	0
T34	10722	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	508	0	0
T1	367279	1	0	0
T2	112275	8	0	0
T3	351444	5	0	0
T4	59383	0	0	0
T5	2689	1	0	0
T6	389510	2	0	0
T7	17483	1	0	0
T8	39969	0	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	15	0	0
T7	17483	1	0	0
T8	39969	0	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	146023	0	0	0
T15	86217	0	0	0
T16	0	1	0	0
T35	208150	0	0	0
T36	131201	0	0	0
T37	381246	0	0	0
T38	59655	0	0	0
T43	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	237	0	0
T2	112275	7	0	0
T3	351444	4	0	0
T4	59383	0	0	0
T5	2689	0	0	0
T6	389510	1	0	0
T7	17483	1	0	0
T8	39969	0	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T16	0	2	0	0
T19	0	1	0	0
T35	208150	0	0	0
T42	0	2	0	0
T67	0	1	0	0
T68	0	7	0	0
T70	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709746788	305742286	0	0
T1	367279	16774	0	0
T2	112275	8201	0	0
T3	351444	2007	0	0
T4	59383	12318	0	0
T5	2689	2036	0	0
T6	389510	7262	0	0
T7	17483	7018	0	0
T8	39969	10859	0	0
T9	16802	16725	0	0
T10	3647	2063	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	589	0	0
T1	367279	1	0	0
T2	112275	8	0	0
T3	351444	5	0	0
T4	59383	0	0	0
T5	2689	1	0	0
T6	389510	2	0	0
T7	17483	2	0	0
T8	39969	0	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	576	0	0
T1	367279	1	0	0
T2	112275	8	0	0
T3	351444	4	0	0
T4	59383	0	0	0
T5	2689	1	0	0
T6	389510	2	0	0
T7	17483	2	0	0
T8	39969	0	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	566	0	0
T1	367279	1	0	0
T2	112275	8	0	0
T3	351444	3	0	0
T4	59383	0	0	0
T5	2689	1	0	0
T6	389510	2	0	0
T7	17483	2	0	0
T8	39969	0	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	556	0	0
T1	367279	1	0	0
T2	112275	8	0	0
T3	351444	3	0	0
T4	59383	0	0	0
T5	2689	1	0	0
T6	389510	1	0	0
T7	17483	2	0	0
T8	39969	0	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	1105	0	0
T7	17483	1	0	0
T8	39969	4	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	146023	2	0	0
T15	86217	2	0	0
T16	0	3	0	0
T19	0	1	0	0
T22	0	1	0	0
T35	208150	0	0	0
T36	131201	0	0	0
T37	381246	0	0	0
T38	59655	0	0	0
T42	0	1	0	0
T68	0	2	0	0
T71	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	133481	0	0
T8	39969	648	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	146023	89	0	0
T15	86217	337	0	0
T16	0	233	0	0
T19	0	106	0	0
T22	0	40	0	0
T35	208150	0	0	0
T36	131201	0	0	0
T37	381246	0	0	0
T38	59655	0	0	0
T39	80954	0	0	0
T42	0	781	0	0
T68	0	296	0	0
T71	0	190	0	0
T73	0	116	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	1020	0	0
T8	39969	4	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	146023	2	0	0
T15	86217	2	0	0
T16	0	2	0	0
T19	0	1	0	0
T22	0	1	0	0
T35	208150	0	0	0
T36	131201	0	0	0
T37	381246	0	0	0
T38	59655	0	0	0
T39	80954	0	0	0
T43	0	1	0	0
T68	0	2	0	0
T71	0	1	0	0
T73	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	69	0	0
T19	193044	0	0	0
T22	154332	0	0	0
T27	0	1	0	0
T32	0	4	0	0
T42	945615	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T59	92410	0	0	0
T60	15264	0	0	0
T61	66983	0	0	0
T67	14815	0	0	0
T68	679182	0	0	0
T69	102092	0	0	0
T70	561143	0	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	5	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	1415	0	0
T11	60192	171	0	0
T12	0	343	0	0
T13	0	343	0	0
T23	795463	0	0	0
T25	0	382	0	0
T26	0	176	0	0
T27	11533	0	0	0
T28	68764	0	0	0
T29	192071	0	0	0
T30	3952	0	0	0
T31	10379	0	0	0
T32	531165	0	0	0
T33	40020	0	0	0
T34	10722	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	1175	0	0
T11	60192	141	0	0
T12	0	283	0	0
T13	0	283	0	0
T23	795463	0	0	0
T25	0	322	0	0
T26	0	146	0	0
T27	11533	0	0	0
T28	68764	0	0	0
T29	192071	0	0	0
T30	3952	0	0	0
T31	10379	0	0	0
T32	531165	0	0	0
T33	40020	0	0	0
T34	10722	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709745106	709674376	0	0
T1	367279	367270	0	0
T2	112275	112193	0	0
T3	351444	351438	0	0
T4	59383	59321	0	0
T5	2689	2594	0	0
T6	389510	389504	0	0
T7	17483	17431	0	0
T8	39969	39881	0	0
T9	16802	16726	0	0
T10	3647	3591	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	709778722	0	0
T1	367279	367270	0	0
T2	112275	112193	0	0
T3	351444	351438	0	0
T4	59383	59321	0	0
T5	2689	2594	0	0
T6	389510	389504	0	0
T7	17483	17431	0	0
T8	39969	39881	0	0
T9	16802	16726	0	0
T10	3647	3591	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T9
1	0	1	Covered	T1,T14,T16
1	1	0	Covered	T7,T8,T14
1	1	1	Covered	T14,T37,T16

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T37,T16
0	1	Covered	T16,T29,T32
1	0	Covered	T42,T19,T31

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T14,T37,T16
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T42,T19,T31

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T37,T16
1	0	Not Covered
1	1	Covered	T16,T29,T32

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T14,T16

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T2,T14,T41

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T14
1	Covered	T1,T3,T6

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T38,T42

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T14,T38

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T14,T37,T16

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T14,T37,T16
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T18,T48,T54
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T46,T81,T85
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T18,T44,T52
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T86,T87,T88
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T6,T14
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T14,T37,T16
TimeoutSt->Phase0St	172	Covered	T16,T42,T19

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T37,T16
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T16,T42,T19
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T14,T37,T16
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T14,T37,T16
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T18,T54,T89
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T46,T81,T85
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T18,T44,T52
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T86,T87,T88
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T6,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	709951444	306	0	0
CheckAccumTrig0_A	709951444	490	0	0
CheckAccumTrig1_A	709951444	22	0	0
CheckClr_A	709951444	216	0	0
CheckEn_A	709746788	350393488	0	0
CheckPhase0_A	709951444	560	0	0
CheckPhase1_A	709951444	550	0	0
CheckPhase2_A	709951444	539	0	0
CheckPhase3_A	709951444	536	0	0
CheckTimeout0_A	709951444	1029	0	0
CheckTimeoutSt1_A	709951444	121363	0	0
CheckTimeoutSt2_A	709951444	947	0	0
CheckTimeoutStTrig_A	709951444	60	0	0
ErrorStAllEscAsserted_A	709951444	1428	0	0
ErrorStIsTerminal_A	709951444	1188	0	0
EscStateOut_A	709745106	709674376	0	0
u_state_regs_A	709951444	709778722	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	306	0	0
T11	60192	41	0	0
T12	0	56	0	0
T13	0	89	0	0
T23	795463	0	0	0
T25	0	74	0	0
T26	0	46	0	0
T27	11533	0	0	0
T28	68764	0	0	0
T29	192071	0	0	0
T30	3952	0	0	0
T31	10379	0	0	0
T32	531165	0	0	0
T33	40020	0	0	0
T34	10722	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	490	0	0
T1	367279	1	0	0
T2	112275	1	0	0
T3	351444	1	0	0
T4	59383	0	0	0
T5	2689	0	0	0
T6	389510	2	0	0
T7	17483	0	0	0
T8	39969	0	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	0	7	0	0
T16	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	22	0	0
T19	193044	2	0	0
T22	154332	0	0	0
T42	945615	2	0	0
T48	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T59	92410	0	0	0
T60	15264	0	0	0
T61	66983	0	0	0
T67	14815	0	0	0
T68	679182	0	0	0
T69	102092	0	0	0
T70	561143	0	0	0
T83	0	1	0	0
T85	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	216	0	0
T3	351444	1	0	0
T4	59383	0	0	0
T5	2689	0	0	0
T6	389510	1	0	0
T7	17483	0	0	0
T8	39969	0	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	146023	4	0	0
T18	0	4	0	0
T29	0	1	0	0
T35	208150	0	0	0
T42	0	10	0	0
T64	0	1	0	0
T65	0	1	0	0
T69	0	5	0	0
T93	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709746788	350393488	0	0
T1	367279	10834	0	0
T2	112275	8465	0	0
T3	351444	350896	0	0
T4	59383	59320	0	0
T5	2689	2050	0	0
T6	389510	2110	0	0
T7	17483	17430	0	0
T8	39969	39880	0	0
T9	16802	14335	0	0
T10	3647	2077	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	560	0	0
T1	367279	1	0	0
T2	112275	1	0	0
T3	351444	1	0	0
T4	59383	0	0	0
T5	2689	0	0	0
T6	389510	2	0	0
T7	17483	0	0	0
T8	39969	0	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	0	7	0	0
T16	0	3	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	550	0	0
T1	367279	1	0	0
T2	112275	1	0	0
T3	351444	1	0	0
T4	59383	0	0	0
T5	2689	0	0	0
T6	389510	2	0	0
T7	17483	0	0	0
T8	39969	0	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	0	7	0	0
T16	0	3	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	539	0	0
T1	367279	1	0	0
T2	112275	1	0	0
T3	351444	1	0	0
T4	59383	0	0	0
T5	2689	0	0	0
T6	389510	2	0	0
T7	17483	0	0	0
T8	39969	0	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	0	7	0	0
T16	0	3	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	536	0	0
T1	367279	1	0	0
T2	112275	1	0	0
T3	351444	1	0	0
T4	59383	0	0	0
T5	2689	0	0	0
T6	389510	2	0	0
T7	17483	0	0	0
T8	39969	0	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	0	7	0	0
T16	0	3	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	1029	0	0
T14	146023	4	0	0
T15	86217	0	0	0
T16	352686	6	0	0
T19	0	2	0	0
T27	0	3	0	0
T29	0	10	0	0
T31	0	1	0	0
T36	131201	0	0	0
T37	381246	1	0	0
T38	59655	0	0	0
T39	80954	0	0	0
T40	191424	0	0	0
T41	187016	0	0	0
T42	0	3	0	0
T58	1047	0	0	0
T68	0	3	0	0
T72	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	121363	0	0
T14	146023	171	0	0
T15	86217	0	0	0
T16	352686	1362	0	0
T19	0	37	0	0
T27	0	409	0	0
T29	0	2280	0	0
T31	0	50	0	0
T36	131201	0	0	0
T37	381246	107	0	0
T38	59655	0	0	0
T39	80954	0	0	0
T40	191424	0	0	0
T41	187016	0	0	0
T42	0	228	0	0
T58	1047	0	0	0
T68	0	333	0	0
T72	0	73	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	947	0	0
T14	146023	4	0	0
T15	86217	0	0	0
T16	352686	5	0	0
T27	0	3	0	0
T29	0	9	0	0
T31	0	1	0	0
T32	0	1	0	0
T36	131201	0	0	0
T37	381246	1	0	0
T38	59655	0	0	0
T39	80954	0	0	0
T40	191424	0	0	0
T41	187016	0	0	0
T42	0	1	0	0
T58	1047	0	0	0
T68	0	3	0	0
T72	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	60	0	0
T16	352686	1	0	0
T18	741402	0	0	0
T21	16230	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T62	32134	0	0	0
T63	153799	0	0	0
T71	112163	0	0	0
T76	0	2	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	289330	0	0	0
T97	29998	0	0	0
T98	153817	0	0	0
T99	122857	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	1428	0	0
T11	60192	186	0	0
T12	0	344	0	0
T13	0	375	0	0
T23	795463	0	0	0
T25	0	333	0	0
T26	0	190	0	0
T27	11533	0	0	0
T28	68764	0	0	0
T29	192071	0	0	0
T30	3952	0	0	0
T31	10379	0	0	0
T32	531165	0	0	0
T33	40020	0	0	0
T34	10722	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	1188	0	0
T11	60192	156	0	0
T12	0	284	0	0
T13	0	315	0	0
T23	795463	0	0	0
T25	0	273	0	0
T26	0	160	0	0
T27	11533	0	0	0
T28	68764	0	0	0
T29	192071	0	0	0
T30	3952	0	0	0
T31	10379	0	0	0
T32	531165	0	0	0
T33	40020	0	0	0
T34	10722	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709745106	709674376	0	0
T1	367279	367270	0	0
T2	112275	112193	0	0
T3	351444	351438	0	0
T4	59383	59321	0	0
T5	2689	2594	0	0
T6	389510	389504	0	0
T7	17483	17431	0	0
T8	39969	39881	0	0
T9	16802	16726	0	0
T10	3647	3591	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	709778722	0	0
T1	367279	367270	0	0
T2	112275	112193	0	0
T3	351444	351438	0	0
T4	59383	59321	0	0
T5	2689	2594	0	0
T6	389510	389504	0	0
T7	17483	17431	0	0
T8	39969	39881	0	0
T9	16802	16726	0	0
T10	3647	3591	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T8
1	0	1	Covered	T3,T7,T14
1	1	0	Covered	T2,T14,T37
1	1	1	Covered	T1,T8,T35

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T14
0	1	Covered	T16,T71,T42
1	0	Covered	T1,T76,T100

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T8,T14
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T76,T100

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T14
1	0	Not Covered
1	1	Covered	T16,T71,T42

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T35,T14

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T14

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T16,T66

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T8,T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T8,T14
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T101,T102,T103
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T3,T40,T47
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T49,T104,T91
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T3,T39,T105
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T2,T3
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T8,T14,T37
TimeoutSt->Phase0St	172	Covered	T1,T16,T71

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T8,T35
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T71
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T8,T14
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T8,T14,T37
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T101,T102,T103
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T40,T47
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T49,T104,T91
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T3,T39,T105
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	709951444	280	0	0
CheckAccumTrig0_A	709951444	489	0	0
CheckAccumTrig1_A	709951444	18	0	0
CheckClr_A	709951444	214	0	0
CheckEn_A	709746788	347928627	0	0
CheckPhase0_A	709951444	574	0	0
CheckPhase1_A	709951444	560	0	0
CheckPhase2_A	709951444	552	0	0
CheckPhase3_A	709951444	542	0	0
CheckTimeout0_A	709951444	2131	0	0
CheckTimeoutSt1_A	709951444	196975	0	0
CheckTimeoutSt2_A	709951444	2039	0	0
CheckTimeoutStTrig_A	709951444	71	0	0
ErrorStAllEscAsserted_A	709951444	1444	0	0
ErrorStIsTerminal_A	709951444	1204	0	0
EscStateOut_A	709745106	709674376	0	0
u_state_regs_A	709951444	709778722	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	280	0	0
T11	60192	30	0	0
T12	0	69	0	0
T13	0	63	0	0
T23	795463	0	0	0
T25	0	74	0	0
T26	0	44	0	0
T27	11533	0	0	0
T28	68764	0	0	0
T29	192071	0	0	0
T30	3952	0	0	0
T31	10379	0	0	0
T32	531165	0	0	0
T33	40020	0	0	0
T34	10722	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	489	0	0
T1	367279	2	0	0
T2	112275	1	0	0
T3	351444	5	0	0
T4	59383	0	0	0
T5	2689	0	0	0
T6	389510	2	0	0
T7	17483	1	0	0
T8	39969	0	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	0	4	0	0
T35	0	1	0	0
T37	0	1	0	0
T39	0	5	0	0
T40	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	18	0	0
T1	367279	1	0	0
T2	112275	0	0	0
T3	351444	0	0	0
T4	59383	0	0	0
T5	2689	0	0	0
T6	389510	0	0	0
T7	17483	0	0	0
T8	39969	0	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T55	0	1	0	0
T76	0	1	0	0
T91	0	1	0	0
T100	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	214	0	0
T1	367279	2	0	0
T2	112275	1	0	0
T3	351444	4	0	0
T4	59383	0	0	0
T5	2689	0	0	0
T6	389510	2	0	0
T7	17483	0	0	0
T8	39969	0	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	0	1	0	0
T16	0	1	0	0
T39	0	4	0	0
T40	0	1	0	0
T71	0	1	0	0
T98	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709746788	347928627	0	0
T1	367279	2090	0	0
T2	112275	106989	0	0
T3	351444	2044	0	0
T4	59383	59320	0	0
T5	2689	2066	0	0
T6	389510	388518	0	0
T7	17483	622	0	0
T8	39969	2141	0	0
T9	16802	826	0	0
T10	3647	2092	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	574	0	0
T1	367279	3	0	0
T2	112275	1	0	0
T3	351444	5	0	0
T4	59383	0	0	0
T5	2689	0	0	0
T6	389510	2	0	0
T7	17483	1	0	0
T8	39969	0	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	0	4	0	0
T35	0	1	0	0
T37	0	1	0	0
T39	0	5	0	0
T40	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	560	0	0
T1	367279	3	0	0
T2	112275	1	0	0
T3	351444	4	0	0
T4	59383	0	0	0
T5	2689	0	0	0
T6	389510	2	0	0
T7	17483	1	0	0
T8	39969	0	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	0	4	0	0
T35	0	1	0	0
T37	0	1	0	0
T39	0	5	0	0
T58	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	552	0	0
T1	367279	3	0	0
T2	112275	1	0	0
T3	351444	4	0	0
T4	59383	0	0	0
T5	2689	0	0	0
T6	389510	2	0	0
T7	17483	1	0	0
T8	39969	0	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	0	4	0	0
T35	0	1	0	0
T37	0	1	0	0
T39	0	5	0	0
T58	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	542	0	0
T1	367279	3	0	0
T2	112275	1	0	0
T3	351444	3	0	0
T4	59383	0	0	0
T5	2689	0	0	0
T6	389510	2	0	0
T7	17483	1	0	0
T8	39969	0	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	0	4	0	0
T35	0	1	0	0
T37	0	1	0	0
T39	0	4	0	0
T58	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	2131	0	0
T1	367279	1	0	0
T2	112275	0	0	0
T3	351444	0	0	0
T4	59383	0	0	0
T5	2689	0	0	0
T6	389510	0	0	0
T7	17483	0	0	0
T8	39969	5	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	0	24	0	0
T15	0	1	0	0
T16	0	3	0	0
T19	0	1	0	0
T37	0	1	0	0
T42	0	3	0	0
T71	0	2	0	0
T73	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	196975	0	0
T1	367279	2	0	0
T2	112275	0	0	0
T3	351444	0	0	0
T4	59383	0	0	0
T5	2689	0	0	0
T6	389510	0	0	0
T7	17483	0	0	0
T8	39969	748	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	0	869	0	0
T15	0	123	0	0
T16	0	1178	0	0
T19	0	405	0	0
T37	0	107	0	0
T42	0	1713	0	0
T71	0	164	0	0
T73	0	37	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	2039	0	0
T8	39969	5	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	146023	24	0	0
T15	86217	1	0	0
T23	0	2	0	0
T29	0	350	0	0
T31	0	1	0	0
T32	0	5	0	0
T35	208150	0	0	0
T36	131201	0	0	0
T37	381246	1	0	0
T38	59655	0	0	0
T39	80954	0	0	0
T43	0	1	0	0
T73	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	71	0	0
T16	352686	3	0	0
T18	741402	0	0	0
T19	0	1	0	0
T21	16230	0	0	0
T32	0	1	0	0
T42	0	3	0	0
T44	0	1	0	0
T48	0	7	0	0
T62	32134	0	0	0
T63	153799	0	0	0
T71	112163	2	0	0
T96	289330	0	0	0
T97	29998	0	0	0
T98	153817	0	0	0
T99	122857	0	0	0
T105	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	1444	0	0
T11	60192	188	0	0
T12	0	360	0	0
T13	0	340	0	0
T23	795463	0	0	0
T25	0	359	0	0
T26	0	197	0	0
T27	11533	0	0	0
T28	68764	0	0	0
T29	192071	0	0	0
T30	3952	0	0	0
T31	10379	0	0	0
T32	531165	0	0	0
T33	40020	0	0	0
T34	10722	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	1204	0	0
T11	60192	158	0	0
T12	0	300	0	0
T13	0	280	0	0
T23	795463	0	0	0
T25	0	299	0	0
T26	0	167	0	0
T27	11533	0	0	0
T28	68764	0	0	0
T29	192071	0	0	0
T30	3952	0	0	0
T31	10379	0	0	0
T32	531165	0	0	0
T33	40020	0	0	0
T34	10722	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709745106	709674376	0	0
T1	367279	367270	0	0
T2	112275	112193	0	0
T3	351444	351438	0	0
T4	59383	59321	0	0
T5	2689	2594	0	0
T6	389510	389504	0	0
T7	17483	17431	0	0
T8	39969	39881	0	0
T9	16802	16726	0	0
T10	3647	3591	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	709778722	0	0
T1	367279	367270	0	0
T2	112275	112193	0	0
T3	351444	351438	0	0
T4	59383	59321	0	0
T5	2689	2594	0	0
T6	389510	389504	0	0
T7	17483	17431	0	0
T8	39969	39881	0	0
T9	16802	16726	0	0
T10	3647	3591	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T7
1	0	1	Covered	T10,T14,T36
1	1	0	Covered	T14,T39,T16
1	1	1	Covered	T7,T8,T14

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T14
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T19,T32

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T7,T8,T14
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T14,T19,T32

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T14
1	0	Covered	T17
1	1	Covered	T14,T15,T16

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T10,T14,T37

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T10
1	Covered	T1,T4,T6

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T2,T4,T37

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T14,T36,T16

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T6,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T7,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T4
Phase1St	198	Covered	T1,T2,T4
Phase2St	215	Covered	T1,T2,T4
Phase3St	233	Covered	T1,T2,T4
TerminalSt	249	Covered	T1,T2,T4
TimeoutSt	159	Covered	T7,T8,T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T4
IdleSt->TimeoutSt	159	Covered	T7,T8,T14
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T19,T20,T74
Phase0St->Phase1St	198	Covered	T1,T2,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T21,T19,T111
Phase1St->Phase2St	215	Covered	T1,T2,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T22,T112,T48
Phase2St->Phase3St	233	Covered	T1,T2,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T23,T24,T49
Phase3St->TerminalSt	249	Covered	T1,T2,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T7,T14
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T7,T8,T14
TimeoutSt->Phase0St	172	Covered	T14,T15,T16

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T14
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T14
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T14
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T19,T20,T74
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T21,T19,T111
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T22,T112,T113
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T24,T49
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T7,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	709951444	278	0	0
CheckAccumTrig0_A	709951444	834	0	0
CheckAccumTrig1_A	709951444	51	0	0
CheckClr_A	709951444	409	0	0
CheckEn_A	709746788	272332091	0	0
CheckPhase0_A	709951444	926	0	0
CheckPhase1_A	709951444	899	0	0
CheckPhase2_A	709951444	884	0	0
CheckPhase3_A	709951444	868	0	0
CheckTimeout0_A	709951444	1596	0	0
CheckTimeoutSt1_A	709951444	140601	0	0
CheckTimeoutSt2_A	709951444	1474	0	0
CheckTimeoutStTrig_A	709951444	71	0	0
ErrorStAllEscAsserted_A	709951444	1528	0	0
ErrorStIsTerminal_A	709951444	1288	0	0
EscStateOut_A	709745106	709674376	0	0
u_state_regs_A	709951444	709778722	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	278	0	0
T11	60192	29	0	0
T12	0	51	0	0
T13	0	72	0	0
T23	795463	0	0	0
T25	0	79	0	0
T26	0	47	0	0
T27	11533	0	0	0
T28	68764	0	0	0
T29	192071	0	0	0
T30	3952	0	0	0
T31	10379	0	0	0
T32	531165	0	0	0
T33	40020	0	0	0
T34	10722	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	834	0	0
T1	367279	1	0	0
T2	112275	1	0	0
T3	351444	0	0	0
T4	59383	5	0	0
T5	2689	0	0	0
T6	389510	1	0	0
T7	17483	3	0	0
T8	39969	0	0	0
T9	16802	1	0	0
T10	3647	1	0	0
T14	0	6	0	0
T35	0	1	0	0
T36	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	51	0	0
T14	146023	1	0	0
T15	86217	0	0	0
T16	352686	0	0	0
T19	0	2	0	0
T32	0	1	0	0
T36	131201	0	0	0
T37	381246	0	0	0
T38	59655	0	0	0
T39	80954	0	0	0
T40	191424	0	0	0
T41	187016	0	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	4	0	0
T51	0	1	0	0
T52	0	2	0	0
T58	1047	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	409	0	0
T4	59383	4	0	0
T5	2689	0	0	0
T6	389510	0	0	0
T7	17483	2	0	0
T8	39969	0	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	146023	2	0	0
T16	0	6	0	0
T21	0	1	0	0
T35	208150	0	0	0
T36	131201	0	0	0
T37	0	1	0	0
T42	0	2	0	0
T62	0	2	0	0
T63	0	1	0	0
T66	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709746788	272332091	0	0
T1	367279	17601	0	0
T2	112275	2964	0	0
T3	351444	351438	0	0
T4	59383	8203	0	0
T5	2689	2030	0	0
T6	389510	6776	0	0
T7	17483	4559	0	0
T8	39969	5814	0	0
T9	16802	814	0	0
T10	3647	2050	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	926	0	0
T1	367279	1	0	0
T2	112275	1	0	0
T3	351444	0	0	0
T4	59383	5	0	0
T5	2689	0	0	0
T6	389510	1	0	0
T7	17483	3	0	0
T8	39969	0	0	0
T9	16802	1	0	0
T10	3647	1	0	0
T14	0	8	0	0
T35	0	1	0	0
T36	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	899	0	0
T1	367279	1	0	0
T2	112275	1	0	0
T3	351444	0	0	0
T4	59383	5	0	0
T5	2689	0	0	0
T6	389510	1	0	0
T7	17483	3	0	0
T8	39969	0	0	0
T9	16802	1	0	0
T10	3647	1	0	0
T14	0	8	0	0
T35	0	1	0	0
T36	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	884	0	0
T1	367279	1	0	0
T2	112275	1	0	0
T3	351444	0	0	0
T4	59383	5	0	0
T5	2689	0	0	0
T6	389510	1	0	0
T7	17483	3	0	0
T8	39969	0	0	0
T9	16802	1	0	0
T10	3647	1	0	0
T14	0	8	0	0
T35	0	1	0	0
T36	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	868	0	0
T1	367279	1	0	0
T2	112275	1	0	0
T3	351444	0	0	0
T4	59383	5	0	0
T5	2689	0	0	0
T6	389510	1	0	0
T7	17483	3	0	0
T8	39969	0	0	0
T9	16802	1	0	0
T10	3647	1	0	0
T14	0	8	0	0
T35	0	1	0	0
T36	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	1596	0	0
T7	17483	1	0	0
T8	39969	6	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	146023	4	0	0
T15	86217	3	0	0
T16	0	17	0	0
T35	208150	0	0	0
T36	131201	0	0	0
T37	381246	1	0	0
T38	59655	0	0	0
T42	0	5	0	0
T61	0	2	0	0
T66	0	1	0	0
T71	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	140601	0	0
T7	17483	15	0	0
T8	39969	891	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	146023	137	0	0
T15	86217	263	0	0
T16	0	2851	0	0
T35	208150	0	0	0
T36	131201	0	0	0
T37	381246	106	0	0
T38	59655	0	0	0
T42	0	1433	0	0
T61	0	282	0	0
T66	0	53	0	0
T71	0	167	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	1474	0	0
T7	17483	1	0	0
T8	39969	6	0	0
T9	16802	0	0	0
T10	3647	0	0	0
T14	146023	2	0	0
T15	86217	2	0	0
T16	0	15	0	0
T35	208150	0	0	0
T36	131201	0	0	0
T37	381246	1	0	0
T38	59655	0	0	0
T42	0	4	0	0
T61	0	2	0	0
T66	0	1	0	0
T71	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	71	0	0
T14	146023	1	0	0
T15	86217	1	0	0
T16	352686	2	0	0
T23	0	2	0	0
T27	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T36	131201	0	0	0
T37	381246	0	0	0
T38	59655	0	0	0
T39	80954	0	0	0
T40	191424	0	0	0
T41	187016	0	0	0
T42	0	1	0	0
T58	1047	0	0	0
T74	0	1	0	0
T75	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	1528	0	0
T11	60192	181	0	0
T12	0	356	0	0
T13	0	409	0	0
T23	795463	0	0	0
T25	0	401	0	0
T26	0	181	0	0
T27	11533	0	0	0
T28	68764	0	0	0
T29	192071	0	0	0
T30	3952	0	0	0
T31	10379	0	0	0
T32	531165	0	0	0
T33	40020	0	0	0
T34	10722	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	1288	0	0
T11	60192	151	0	0
T12	0	296	0	0
T13	0	349	0	0
T23	795463	0	0	0
T25	0	341	0	0
T26	0	151	0	0
T27	11533	0	0	0
T28	68764	0	0	0
T29	192071	0	0	0
T30	3952	0	0	0
T31	10379	0	0	0
T32	531165	0	0	0
T33	40020	0	0	0
T34	10722	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709745106	709674376	0	0
T1	367279	367270	0	0
T2	112275	112193	0	0
T3	351444	351438	0	0
T4	59383	59321	0	0
T5	2689	2594	0	0
T6	389510	389504	0	0
T7	17483	17431	0	0
T8	39969	39881	0	0
T9	16802	16726	0	0
T10	3647	3591	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709951444	709778722	0	0
T1	367279	367270	0	0
T2	112275	112193	0	0
T3	351444	351438	0	0
T4	59383	59321	0	0
T5	2689	2594	0	0
T6	389510	389504	0	0
T7	17483	17431	0	0
T8	39969	39881	0	0
T9	16802	16726	0	0
T10	3647	3591	0	0