Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_mubi4_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=6 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en

Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en

Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Module : prim_mubi4_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 70964 70964 0 0
OutputsKnown_A 2147483647 2147483647 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 2147483647 2147483647 0 90432
gen_no_flops.OutputDelay_A 2147483647 2147483647 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 70964 70964 0 0
T1 113 113 0 0
T2 113 113 0 0
T3 113 113 0 0
T4 113 113 0 0
T5 113 113 0 0
T6 113 113 0 0
T7 113 113 0 0
T15 113 113 0 0
T16 113 113 0 0
T17 113 113 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 79911905 79904673 0 0
T2 55926977 55926073 0 0
T3 8204365 8195325 0 0
T4 11312769 11312204 0 0
T5 41588181 41587164 0 0
T6 33081089 33071597 0 0
T7 78546978 78537938 0 0
T15 3312708 3303781 0 0
T16 3316324 3307397 0 0
T17 611330 604098 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 90432
T1 33944880 33941664 0 144
T2 23756592 23756208 0 144
T3 3485040 3481056 0 144
T4 4805424 4805184 0 144
T5 17665776 17665296 0 144
T6 14052144 14047968 0 144
T7 33365088 33361104 0 144
T15 1407168 1403232 0 144
T16 1408704 1404768 0 144
T17 259680 256464 0 144

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 45967025 45962865 0 0
T2 32170385 32169865 0 0
T3 4719325 4714125 0 0
T4 6507345 6507020 0 0
T5 23922405 23921820 0 0
T6 19028945 19023485 0 0
T7 45181890 45176690 0 0
T15 1905540 1900405 0 0
T16 1907620 1902485 0 0
T17 351650 347490 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 680372423 680206173 0 1884


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680206173 0 1884
T1 707185 707118 0 3
T2 494929 494921 0 3
T3 72605 72522 0 3
T4 100113 100108 0 3
T5 368037 368027 0 3
T6 292753 292666 0 3
T7 695106 695023 0 3
T15 29316 29234 0 3
T16 29348 29266 0 3
T17 5410 5343 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 628 628 0 0
OutputsKnown_A 680372423 680213133 0 0
gen_no_flops.OutputDelay_A 680372423 680213133 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 628 628 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 680372423 680213133 0 0
T1 707185 707121 0 0
T2 494929 494921 0 0
T3 72605 72525 0 0
T4 100113 100108 0 0
T5 368037 368028 0 0
T6 292753 292669 0 0
T7 695106 695026 0 0
T15 29316 29237 0 0
T16 29348 29269 0 0
T17 5410 5346 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%