Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T37,T60,T63
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	12947	0	0
DisabledNoTrigBkwd_A	2147483647	790174	0	0
DisabledNoTrigFwd_A	2147483647	1541308560	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12947	0	0
T8	15766	0	0	0
T29	184379	0	0	0
T37	4430	1024	0	0
T60	0	194	0	0
T63	0	900	0	0
T98	107699	0	0	0
T110	0	286	0	0
T178	240244	0	0	0
T200	21201	0	0	0
T201	194773	0	0	0
T202	42028	0	0	0
T203	128051	0	0	0
T204	15948	0	0	0
T205	0	425	0	0
T206	0	807	0	0
T207	4252	608	0	0
T208	1357	575	0	0
T209	0	621	0	0
T210	0	1118	0	0
T211	0	638	0	0
T212	0	1032	0	0
T213	0	812	0	0
T214	0	518	0	0
T215	0	766	0	0
T216	0	340	0	0
T217	0	476	0	0
T218	0	334	0	0
T219	0	1093	0	0
T220	0	380	0	0
T221	180506	0	0	0
T222	346512	0	0	0
T223	189908	0	0	0
T224	785708	0	0	0
T225	84004	0	0	0
T226	32080	0	0	0
T227	268749	0	0	0
T228	103724	0	0	0
T229	30168	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	790174	0	0
T1	707185	4	0	0
T2	989858	2	0	0
T3	217815	9	0	0
T4	400452	444	0	0
T5	1472148	1890	0	0
T6	1171012	3	0	0
T7	2780424	7	0	0
T11	376300	4563	0	0
T12	0	2616	0	0
T13	0	1326	0	0
T14	0	830	0	0
T15	117264	138	0	0
T16	117392	61	0	0
T17	21640	0	0	0
T18	0	81	0	0
T19	0	2722	0	0
T26	38637	22	0	0
T37	4430	18	0	0
T38	0	21	0	0
T39	0	1	0	0
T40	0	87	0	0
T41	0	239	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1541308560	0	0
T1	2828740	1477869	0	0
T2	1979716	1977214	0	0
T3	290420	256146	0	0
T4	400452	1999348	0	0
T5	1472148	1104594	0	0
T6	1171012	411409	0	0
T7	2780424	1632277	0	0
T15	117264	31209	0	0
T16	117392	76083	0	0
T17	21640	20178	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T207,T217,T218
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	680372423	1798	0	0
DisabledNoTrigBkwd_A	680372423	224560	0	0
DisabledNoTrigFwd_A	680372423	383350963	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	1798	0	0
T98	107699	0	0	0
T207	4252	608	0	0
T217	0	476	0	0
T218	0	334	0	0
T220	0	380	0	0
T221	180506	0	0	0
T222	346512	0	0	0
T223	189908	0	0	0
T224	785708	0	0	0
T225	84004	0	0	0
T226	32080	0	0	0
T227	268749	0	0	0
T228	103724	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	224560	0	0
T1	707185	4	0	0
T2	494929	1	0	0
T3	72605	0	0	0
T4	100113	2	0	0
T5	368037	2	0	0
T6	292753	3	0	0
T7	695106	0	0	0
T11	0	672	0	0
T12	0	884	0	0
T13	0	366	0	0
T15	29316	21	0	0
T16	29348	0	0	0
T17	5410	0	0	0
T39	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	383350963	0	0
T1	707185	61587	0	0
T2	494929	492921	0	0
T3	72605	72525	0	0
T4	100113	989899	0	0
T5	368037	367341	0	0
T6	292753	1960	0	0
T7	695106	421380	0	0
T15	29316	582	0	0
T16	29348	28245	0	0
T17	5410	4140	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T208,T209,T214
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T15

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	680372423	3147	0	0
DisabledNoTrigBkwd_A	680372423	204552	0	0
DisabledNoTrigFwd_A	680372423	371223221	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	3147	0	0
T8	15766	0	0	0
T29	184379	0	0	0
T178	240244	0	0	0
T200	21201	0	0	0
T201	194773	0	0	0
T202	42028	0	0	0
T203	128051	0	0	0
T204	15948	0	0	0
T208	1357	575	0	0
T209	0	621	0	0
T214	0	518	0	0
T216	0	340	0	0
T219	0	1093	0	0
T229	30168	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	204552	0	0
T2	494929	1	0	0
T3	72605	0	0	0
T4	100113	2	0	0
T5	368037	3	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T11	0	1566	0	0
T12	0	6	0	0
T13	0	627	0	0
T15	29316	87	0	0
T16	29348	13	0	0
T17	5410	0	0	0
T19	0	2722	0	0
T26	12879	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	371223221	0	0
T1	707185	707121	0	0
T2	494929	494451	0	0
T3	72605	66787	0	0
T4	100113	988695	0	0
T5	368037	366415	0	0
T6	292753	114786	0	0
T7	695106	274554	0	0
T15	29316	586	0	0
T16	29348	16417	0	0
T17	5410	5346	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T15,T16

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T37,T60,T210
1	1	Covered	T3,T15,T16

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T16,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T15,T16

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	680372423	3914	0	0
DisabledNoTrigBkwd_A	680372423	184797	0	0
DisabledNoTrigFwd_A	680372423	386418031	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	3914	0	0
T12	226078	0	0	0
T13	328672	0	0	0
T14	260830	0	0	0
T19	296899	0	0	0
T37	4430	1024	0	0
T38	48048	0	0	0
T39	3806	0	0	0
T40	125405	0	0	0
T57	28343	0	0	0
T58	67857	0	0	0
T60	0	194	0	0
T210	0	1118	0	0
T213	0	812	0	0
T215	0	766	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	184797	0	0
T3	72605	9	0	0
T4	100113	0	0	0
T5	368037	1885	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T11	188150	16	0	0
T12	0	1726	0	0
T13	0	333	0	0
T15	29316	4	0	0
T16	29348	48	0	0
T17	5410	0	0	0
T26	12879	4	0	0
T37	0	18	0	0
T38	0	16	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	386418031	0	0
T1	707185	707121	0	0
T2	494929	494921	0	0
T3	72605	44309	0	0
T4	100113	8491	0	0
T5	368037	2810	0	0
T6	292753	1994	0	0
T7	695106	596058	0	0
T15	29316	26695	0	0
T16	29348	2152	0	0
T17	5410	5346	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T15
1	0	Covered	T2,T3,T4
1	1	Covered	T4,T15,T7

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T63,T110,T205
1	1	Covered	T4,T15,T7

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T15,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T15,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	680372423	4088	0	0
DisabledNoTrigBkwd_A	680372423	176265	0	0
DisabledNoTrigFwd_A	680372423	400316345	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	4088	0	0
T20	650568	0	0	0
T21	249979	0	0	0
T25	223756	0	0	0
T63	1987	900	0	0
T64	83209	0	0	0
T65	10135	0	0	0
T66	6603	0	0	0
T71	10303	0	0	0
T72	36984	0	0	0
T83	135863	0	0	0
T110	0	286	0	0
T205	0	425	0	0
T206	0	807	0	0
T211	0	638	0	0
T212	0	1032	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	176265	0	0
T4	100113	440	0	0
T5	368037	0	0	0
T6	292753	0	0	0
T7	695106	7	0	0
T11	188150	2309	0	0
T14	0	830	0	0
T15	29316	26	0	0
T16	29348	0	0	0
T17	5410	0	0	0
T18	0	81	0	0
T26	12879	15	0	0
T37	4430	0	0	0
T38	0	5	0	0
T40	0	87	0	0
T41	0	239	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	400316345	0	0
T1	707185	2040	0	0
T2	494929	494921	0	0
T3	72605	72525	0	0
T4	100113	12263	0	0
T5	368037	368028	0	0
T6	292753	292669	0	0
T7	695106	340285	0	0
T15	29316	3346	0	0
T16	29348	29269	0	0
T17	5410	5346	0	0