Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.87	100.00	89.36		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	42	89.36
Logical	47	42	89.36
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T15,T16
1	0	1	Covered	T1,T4,T16
1	1	0	Covered	T3,T15,T16
1	1	1	Covered	T3,T15,T16

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T15,T16
0	1	Covered	T3,T11,T18
1	0	Covered	T11,T19,T18

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T15,T16
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T11,T19,T18

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T15,T16
1	0	Not Covered
1	1	Covered	T3,T11,T18

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T15

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T4,T15

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T15

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T15

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T3,T15,T16

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T3,T15,T16
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T20,T21,T22
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T11,T18,T20
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T15,T23,T24
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T15,T20,T25
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T2,T4
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T15,T16,T26
TimeoutSt->Phase0St	172	Covered	T3,T11,T19

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T15,T16
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T11,T19
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T15,T16
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T26
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T20,T21,T22
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T11,T18,T20
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T15,T23,T24
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T15,T20,T25
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1003	0	0
CheckAccumTrig0_A	2147483647	2383	0	0
CheckAccumTrig1_A	2147483647	125	0	0
CheckClr_A	2147483647	1140	0	0
CheckEn_A	2147483647	1151500231	0	0
CheckPhase0_A	2147483647	2717	0	0
CheckPhase1_A	2147483647	2653	0	0
CheckPhase2_A	2147483647	2606	0	0
CheckPhase3_A	2147483647	2558	0	0
CheckTimeout0_A	2147483647	5769	0	0
CheckTimeoutSt1_A	2147483647	613796	0	0
CheckTimeoutSt2_A	2147483647	5372	0	0
CheckTimeoutStTrig_A	2147483647	262	0	0
ErrorStAllEscAsserted_A	2147483647	5088	0	0
ErrorStIsTerminal_A	2147483647	4248	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1003	0	0
T8	63064	144	0	0
T9	63556	137	0	0
T10	0	278	0	0
T27	0	318	0	0
T28	0	126	0	0
T29	737516	0	0	0
T30	85176	0	0	0
T31	2420216	0	0	0
T32	487020	0	0	0
T33	81808	0	0	0
T34	60924	0	0	0
T35	216536	0	0	0
T36	503640	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2383	0	0
T1	707185	2	0	0
T2	989858	2	0	0
T3	217815	1	0	0
T4	400452	4	0	0
T5	1472148	3	0	0
T6	1171012	1	0	0
T7	2780424	1	0	0
T11	376300	16	0	0
T12	0	5	0	0
T13	0	3	0	0
T14	0	2	0	0
T15	117264	18	0	0
T16	117392	2	0	0
T17	21640	0	0	0
T18	0	1	0	0
T19	0	2	0	0
T26	38637	3	0	0
T37	4430	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	125	0	0
T11	188150	1	0	0
T12	226078	0	0	0
T13	328672	0	0	0
T14	260830	0	0	0
T18	848457	1	0	0
T19	296899	1	0	0
T20	0	1	0	0
T23	376378	1	0	0
T24	0	2	0	0
T37	4430	0	0	0
T38	48048	0	0	0
T39	3806	0	0	0
T40	125405	0	0	0
T41	105182	0	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	3	0	0
T48	0	2	0	0
T49	0	3	0	0
T50	0	1	0	0
T51	0	4	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	28343	0	0	0
T58	67857	0	0	0
T59	31196	0	0	0
T60	909	0	0	0
T61	73905	0	0	0
T62	574569	0	0	0
T63	1987	0	0	0
T64	83209	0	0	0
T65	10135	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1140	0	0
T1	707185	1	0	0
T2	989858	1	0	0
T3	145210	0	0	0
T4	200226	1	0	0
T5	1472148	0	0	0
T6	1171012	0	0	0
T7	2780424	0	0	0
T11	376300	5	0	0
T12	452156	2	0	0
T14	0	2	0	0
T15	117264	10	0	0
T16	117392	0	0	0
T17	21640	0	0	0
T18	0	4	0	0
T19	0	2	0	0
T20	0	10	0	0
T21	0	1	0	0
T22	0	2	0	0
T25	0	8	0	0
T26	38637	0	0	0
T37	8860	0	0	0
T39	0	1	0	0
T41	0	4	0	0
T61	0	2	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1151500231	0	0
T1	2828740	1477867	0	0
T2	1979716	1511639	0	0
T3	290420	162719	0	0
T4	400452	43796	0	0
T5	1472148	381044	0	0
T6	1171012	411408	0	0
T7	2780424	1632275	0	0
T15	117264	31208	0	0
T16	117392	61274	0	0
T17	21640	20174	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2717	0	0
T1	707185	2	0	0
T2	989858	2	0	0
T3	217815	2	0	0
T4	400452	4	0	0
T5	1472148	3	0	0
T6	1171012	1	0	0
T7	2780424	1	0	0
T11	376300	18	0	0
T12	0	5	0	0
T13	0	3	0	0
T14	0	2	0	0
T15	117264	19	0	0
T16	117392	2	0	0
T17	21640	0	0	0
T26	38637	3	0	0
T37	4430	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T59	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2653	0	0
T1	707185	2	0	0
T2	989858	2	0	0
T3	217815	2	0	0
T4	400452	4	0	0
T5	1472148	3	0	0
T6	1171012	1	0	0
T7	2780424	1	0	0
T11	376300	17	0	0
T12	0	5	0	0
T13	0	3	0	0
T14	0	2	0	0
T15	117264	19	0	0
T16	117392	2	0	0
T17	21640	0	0	0
T26	38637	3	0	0
T37	4430	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T59	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2606	0	0
T1	707185	2	0	0
T2	989858	2	0	0
T3	217815	2	0	0
T4	400452	4	0	0
T5	1472148	3	0	0
T6	1171012	1	0	0
T7	2780424	1	0	0
T11	376300	17	0	0
T12	0	5	0	0
T13	0	3	0	0
T14	0	2	0	0
T15	117264	17	0	0
T16	117392	2	0	0
T17	21640	0	0	0
T26	38637	3	0	0
T37	4430	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T59	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2558	0	0
T1	707185	2	0	0
T2	989858	2	0	0
T3	217815	2	0	0
T4	400452	4	0	0
T5	1472148	3	0	0
T6	1171012	1	0	0
T7	2780424	1	0	0
T11	376300	17	0	0
T12	0	5	0	0
T13	0	3	0	0
T14	0	2	0	0
T15	117264	16	0	0
T16	117392	2	0	0
T17	21640	0	0	0
T26	38637	3	0	0
T37	4430	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T59	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5769	0	0
T3	72605	1	0	0
T4	100113	0	0	0
T5	1472148	0	0	0
T6	1171012	0	0	0
T7	2780424	0	0	0
T11	752600	5	0	0
T12	678234	0	0	0
T14	0	1	0	0
T15	87948	2	0	0
T16	117392	1	0	0
T17	21640	0	0	0
T18	0	286	0	0
T19	0	7	0	0
T20	0	20	0	0
T22	0	3	0	0
T26	51516	2	0	0
T37	13290	0	0	0
T38	48048	0	0	0
T43	0	4	0	0
T57	0	1	0	0
T58	0	11	0	0
T59	0	14	0	0
T61	0	1	0	0
T66	0	2	0	0
T71	0	6	0	0
T72	0	2	0	0
T73	0	1	0	0
T74	0	15	0	0
T75	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	613796	0	0
T3	72605	804	0	0
T4	100113	0	0	0
T5	1104111	0	0	0
T6	878259	0	0	0
T7	2085318	0	0	0
T11	752600	538	0	0
T12	678234	0	0	0
T13	328672	0	0	0
T14	260830	184	0	0
T15	58632	18	0	0
T16	88044	46	0	0
T17	16230	0	0	0
T18	0	17306	0	0
T19	0	619	0	0
T20	0	1559	0	0
T22	0	895	0	0
T26	38637	205	0	0
T37	13290	0	0	0
T38	96096	0	0	0
T39	3806	0	0	0
T40	125405	0	0	0
T43	0	587	0	0
T57	28343	75	0	0
T58	67857	1434	0	0
T59	0	846	0	0
T61	0	38	0	0
T66	0	35	0	0
T71	0	331	0	0
T72	0	1177	0	0
T73	0	207	0	0
T74	0	5397	0	0
T75	0	421	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5372	0	0
T5	736074	0	0	0
T6	585506	0	0	0
T7	1390212	0	0	0
T11	752600	3	0	0
T12	904312	0	0	0
T13	657344	0	0	0
T14	521660	1	0	0
T15	29316	1	0	0
T16	58696	1	0	0
T17	10820	0	0	0
T18	0	283	0	0
T19	0	6	0	0
T20	0	17	0	0
T22	0	4	0	0
T26	25758	2	0	0
T37	17720	0	0	0
T38	144144	0	0	0
T39	7612	0	0	0
T40	250810	0	0	0
T43	0	8	0	0
T57	56686	1	0	0
T58	135714	11	0	0
T59	0	13	0	0
T61	0	1	0	0
T66	0	1	0	0
T69	0	1	0	0
T71	0	6	0	0
T73	0	2	0	0
T74	0	15	0	0
T75	0	19	0	0
T76	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	262	0	0
T3	72605	1	0	0
T4	100113	0	0	0
T5	368037	0	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T11	188150	1	0	0
T15	29316	0	0	0
T16	29348	0	0	0
T17	5410	0	0	0
T18	848457	2	0	0
T20	650568	1	0	0
T22	0	2	0	0
T24	0	2	0	0
T25	223756	0	0	0
T26	12879	0	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	5	0	0
T48	0	1	0	0
T49	0	1	0	0
T61	73905	0	0	0
T62	574569	0	0	0
T63	1987	0	0	0
T64	83209	0	0	0
T65	10135	0	0	0
T71	10303	0	0	0
T72	0	2	0	0
T74	0	1	0	0
T75	272422	2	0	0
T77	0	1	0	0
T78	0	2	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	135863	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5088	0	0
T8	63064	751	0	0
T9	63556	652	0	0
T10	0	1497	0	0
T27	0	1450	0	0
T28	0	738	0	0
T29	737516	0	0	0
T30	85176	0	0	0
T31	2420216	0	0	0
T32	487020	0	0	0
T33	81808	0	0	0
T34	60924	0	0	0
T35	216536	0	0	0
T36	503640	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4248	0	0
T8	63064	631	0	0
T9	63556	532	0	0
T10	0	1257	0	0
T27	0	1210	0	0
T28	0	618	0	0
T29	737516	0	0	0
T30	85176	0	0	0
T31	2420216	0	0	0
T32	487020	0	0	0
T33	81808	0	0	0
T34	60924	0	0	0
T35	216536	0	0	0
T36	503640	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2828740	2828484	0	0
T2	1979716	1979684	0	0
T3	290420	290100	0	0
T4	400452	400432	0	0
T5	1472148	1472112	0	0
T6	1171012	1170676	0	0
T7	2780424	2780104	0	0
T15	117264	116948	0	0
T16	117392	117076	0	0
T17	21640	21384	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2828740	2828484	0	0
T2	1979716	1979684	0	0
T3	290420	290100	0	0
T4	400452	400432	0	0
T5	1472148	1472112	0	0
T6	1171012	1170676	0	0
T7	2780424	2780104	0	0
T15	117264	116948	0	0
T16	117392	117076	0	0
T17	21640	21384	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T15,T17,T11
1	0	1	Covered	T1,T6,T11
1	1	0	Covered	T3,T16,T26
1	1	1	Covered	T15,T11,T57

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T15,T11,T57
0	1	Covered	T18,T72,T42
1	0	Covered	T11,T18,T43

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T15,T11,T57
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T11,T18,T43

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T11,T57
1	0	Not Covered
1	1	Covered	T18,T72,T42

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T5,T11,T13

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T15,T6

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T4,T15

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T15
1	Covered	T1,T2,T11

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T15,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T15,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T15

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T4
Phase1St	198	Covered	T1,T2,T4
Phase2St	215	Covered	T1,T2,T4
Phase3St	233	Covered	T1,T2,T4
TerminalSt	249	Covered	T1,T2,T4
TimeoutSt	159	Covered	T15,T11,T57

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T2,T4
IdleSt->TimeoutSt	159	Covered	T15,T11,T57
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T20,T22,T49
Phase0St->Phase1St	198	Covered	T1,T2,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T18,T20,T25
Phase1St->Phase2St	215	Covered	T1,T2,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T24,T47,T48
Phase2St->Phase3St	233	Covered	T1,T2,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T15,T20,T84
Phase3St->TerminalSt	249	Covered	T1,T2,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T4,T15
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T15,T57,T14
TimeoutSt->Phase0St	172	Covered	T11,T18,T72

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T11,T57
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T11,T18,T72
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T15,T11,T57
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T15,T57,T14
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T20,T22,T85
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T18,T25,T22
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T24,T47,T48
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T15,T20,T84
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	680372423	266	0	0
CheckAccumTrig0_A	680372423	891	0	0
CheckAccumTrig1_A	680372423	53	0	0
CheckClr_A	680372423	464	0	0
CheckEn_A	680073680	264629744	0	0
CheckPhase0_A	680372423	990	0	0
CheckPhase1_A	680372423	956	0	0
CheckPhase2_A	680372423	936	0	0
CheckPhase3_A	680372423	915	0	0
CheckTimeout0_A	680372423	1404	0	0
CheckTimeoutSt1_A	680372423	163971	0	0
CheckTimeoutSt2_A	680372423	1280	0	0
CheckTimeoutStTrig_A	680372423	68	0	0
ErrorStAllEscAsserted_A	680372423	1241	0	0
ErrorStIsTerminal_A	680372423	1031	0	0
EscStateOut_A	680072205	680002623	0	0
u_state_regs_A	680372423	680213133	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	266	0	0
T8	15766	42	0	0
T9	15889	31	0	0
T10	0	77	0	0
T27	0	88	0	0
T28	0	28	0	0
T29	184379	0	0	0
T30	21294	0	0	0
T31	605054	0	0	0
T32	121755	0	0	0
T33	20452	0	0	0
T34	15231	0	0	0
T35	54134	0	0	0
T36	125910	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	891	0	0
T1	707185	2	0	0
T2	494929	1	0	0
T3	72605	0	0	0
T4	100113	2	0	0
T5	368037	1	0	0
T6	292753	1	0	0
T7	695106	0	0	0
T11	0	4	0	0
T12	0	1	0	0
T13	0	1	0	0
T15	29316	7	0	0
T16	29348	0	0	0
T17	5410	0	0	0
T39	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	53	0	0
T11	188150	1	0	0
T12	226078	0	0	0
T13	328672	0	0	0
T14	260830	0	0	0
T18	0	1	0	0
T24	0	2	0	0
T37	4430	0	0	0
T38	48048	0	0	0
T39	3806	0	0	0
T40	125405	0	0	0
T43	0	2	0	0
T44	0	1	0	0
T46	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T51	0	2	0	0
T52	0	1	0	0
T57	28343	0	0	0
T58	67857	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	464	0	0
T1	707185	1	0	0
T2	494929	0	0	0
T3	72605	0	0	0
T4	100113	1	0	0
T5	368037	0	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T15	29316	6	0	0
T16	29348	0	0	0
T17	5410	0	0	0
T18	0	4	0	0
T20	0	6	0	0
T25	0	3	0	0
T39	0	1	0	0
T41	0	4	0	0
T61	0	1	0	0
T67	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680073680	264629744	0	0
T1	707185	61587	0	0
T2	494929	27346	0	0
T3	72605	72524	0	0
T4	100113	4738	0	0
T5	368037	7430	0	0
T6	292753	1960	0	0
T7	695106	421379	0	0
T15	29316	582	0	0
T16	29348	28244	0	0
T17	5410	4139	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	990	0	0
T1	707185	2	0	0
T2	494929	1	0	0
T3	72605	0	0	0
T4	100113	2	0	0
T5	368037	1	0	0
T6	292753	1	0	0
T7	695106	0	0	0
T11	0	5	0	0
T12	0	1	0	0
T13	0	1	0	0
T15	29316	7	0	0
T16	29348	0	0	0
T17	5410	0	0	0
T39	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	956	0	0
T1	707185	2	0	0
T2	494929	1	0	0
T3	72605	0	0	0
T4	100113	2	0	0
T5	368037	1	0	0
T6	292753	1	0	0
T7	695106	0	0	0
T11	0	5	0	0
T12	0	1	0	0
T13	0	1	0	0
T15	29316	7	0	0
T16	29348	0	0	0
T17	5410	0	0	0
T39	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	936	0	0
T1	707185	2	0	0
T2	494929	1	0	0
T3	72605	0	0	0
T4	100113	2	0	0
T5	368037	1	0	0
T6	292753	1	0	0
T7	695106	0	0	0
T11	0	5	0	0
T12	0	1	0	0
T13	0	1	0	0
T15	29316	7	0	0
T16	29348	0	0	0
T17	5410	0	0	0
T39	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	915	0	0
T1	707185	2	0	0
T2	494929	1	0	0
T3	72605	0	0	0
T4	100113	2	0	0
T5	368037	1	0	0
T6	292753	1	0	0
T7	695106	0	0	0
T11	0	5	0	0
T12	0	1	0	0
T13	0	1	0	0
T15	29316	6	0	0
T16	29348	0	0	0
T17	5410	0	0	0
T39	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	1404	0	0
T5	368037	0	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T11	188150	1	0	0
T12	226078	0	0	0
T14	0	1	0	0
T15	29316	1	0	0
T16	29348	0	0	0
T17	5410	0	0	0
T18	0	89	0	0
T20	0	4	0	0
T26	12879	0	0	0
T37	4430	0	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	6	0	0
T71	0	1	0	0
T72	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	163971	0	0
T5	368037	0	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T11	188150	1	0	0
T12	226078	0	0	0
T14	0	184	0	0
T15	29316	18	0	0
T16	29348	0	0	0
T17	5410	0	0	0
T18	0	4289	0	0
T20	0	432	0	0
T26	12879	0	0	0
T37	4430	0	0	0
T57	0	75	0	0
T58	0	272	0	0
T59	0	347	0	0
T71	0	51	0	0
T72	0	499	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	1280	0	0
T5	368037	0	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T11	188150	0	0	0
T12	226078	0	0	0
T14	0	1	0	0
T15	29316	1	0	0
T16	29348	0	0	0
T17	5410	0	0	0
T18	0	87	0	0
T20	0	4	0	0
T26	12879	0	0	0
T37	4430	0	0	0
T43	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	6	0	0
T71	0	1	0	0
T73	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	68	0	0
T18	848457	1	0	0
T20	650568	0	0	0
T22	0	1	0	0
T24	0	2	0	0
T25	223756	0	0	0
T42	0	2	0	0
T44	0	1	0	0
T61	73905	0	0	0
T62	574569	0	0	0
T63	1987	0	0	0
T64	83209	0	0	0
T65	10135	0	0	0
T71	10303	0	0	0
T72	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T83	135863	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	1241	0	0
T8	15766	195	0	0
T9	15889	163	0	0
T10	0	368	0	0
T27	0	341	0	0
T28	0	174	0	0
T29	184379	0	0	0
T30	21294	0	0	0
T31	605054	0	0	0
T32	121755	0	0	0
T33	20452	0	0	0
T34	15231	0	0	0
T35	54134	0	0	0
T36	125910	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	1031	0	0
T8	15766	165	0	0
T9	15889	133	0	0
T10	0	308	0	0
T27	0	281	0	0
T28	0	144	0	0
T29	184379	0	0	0
T30	21294	0	0	0
T31	605054	0	0	0
T32	121755	0	0	0
T33	20452	0	0	0
T34	15231	0	0	0
T35	54134	0	0	0
T36	125910	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680072205	680002623	0	0
T1	707185	707121	0	0
T2	494929	494921	0	0
T3	72605	72525	0	0
T4	100113	100108	0	0
T5	368037	368028	0	0
T6	292753	292669	0	0
T7	695106	695026	0	0
T15	29316	29237	0	0
T16	29348	29269	0	0
T17	5410	5346	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	680213133	0	0
T1	707185	707121	0	0
T2	494929	494921	0	0
T3	72605	72525	0	0
T4	100113	100108	0	0
T5	368037	368028	0	0
T6	292753	292669	0	0
T7	695106	695026	0	0
T15	29316	29237	0	0
T16	29348	29269	0	0
T17	5410	5346	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T15

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T15,T16
1	0	1	Covered	T4,T6,T5
1	1	0	Covered	T11,T38,T14
1	1	1	Covered	T3,T11,T58

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T58
0	1	Covered	T3,T11,T18
1	0	Covered	T19,T20,T42

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T11,T58
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T19,T20,T42

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T58
1	0	Not Covered
1	1	Covered	T3,T11,T18

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T15,T5
1	Covered	T2,T4,T15

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T15
1	Covered	T3,T11,T68

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T5,T26,T12

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T15,T11,T12

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T4,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T15,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T4
Phase1St	198	Covered	T2,T3,T4
Phase2St	215	Covered	T2,T3,T4
Phase3St	233	Covered	T2,T3,T4
TerminalSt	249	Covered	T2,T3,T4
TimeoutSt	159	Covered	T3,T11,T58

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T2,T4,T15
IdleSt->TimeoutSt	159	Covered	T3,T11,T58
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T21,T47,T53
Phase0St->Phase1St	198	Covered	T2,T3,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T20,T25,T86
Phase1St->Phase2St	215	Covered	T2,T3,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T15,T47,T87
Phase2St->Phase3St	233	Covered	T2,T3,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T25,T66,T81
Phase3St->TerminalSt	249	Covered	T2,T3,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T15,T11
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T11,T58,T19
TimeoutSt->Phase0St	172	Covered	T3,T11,T19

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T15
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T11,T58
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T11,T19
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T11,T58
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T11,T58,T19
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T21,T47,T53
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T20,T25,T86
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T15,T47,T87
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T25,T66,T81
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T15,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	680372423	221	0	0
CheckAccumTrig0_A	680372423	483	0	0
CheckAccumTrig1_A	680372423	26	0	0
CheckClr_A	680372423	219	0	0
CheckEn_A	680073680	283884863	0	0
CheckPhase0_A	680372423	575	0	0
CheckPhase1_A	680372423	568	0	0
CheckPhase2_A	680372423	563	0	0
CheckPhase3_A	680372423	553	0	0
CheckTimeout0_A	680372423	1426	0	0
CheckTimeoutSt1_A	680372423	141152	0	0
CheckTimeoutSt2_A	680372423	1320	0	0
CheckTimeoutStTrig_A	680372423	76	0	0
ErrorStAllEscAsserted_A	680372423	1268	0	0
ErrorStIsTerminal_A	680372423	1058	0	0
EscStateOut_A	680072205	680002623	0	0
u_state_regs_A	680372423	680213133	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	221	0	0
T8	15766	27	0	0
T9	15889	38	0	0
T10	0	70	0	0
T27	0	62	0	0
T28	0	24	0	0
T29	184379	0	0	0
T30	21294	0	0	0
T31	605054	0	0	0
T32	121755	0	0	0
T33	20452	0	0	0
T34	15231	0	0	0
T35	54134	0	0	0
T36	125910	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	483	0	0
T2	494929	1	0	0
T3	72605	0	0	0
T4	100113	1	0	0
T5	368037	1	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T11	0	2	0	0
T12	0	3	0	0
T13	0	1	0	0
T15	29316	4	0	0
T16	29348	1	0	0
T17	5410	0	0	0
T19	0	2	0	0
T26	12879	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	26	0	0
T18	848457	0	0	0
T19	296899	1	0	0
T20	0	1	0	0
T41	105182	0	0	0
T42	0	1	0	0
T45	0	2	0	0
T47	0	3	0	0
T51	0	2	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T59	31196	0	0	0
T60	909	0	0	0
T61	73905	0	0	0
T62	574569	0	0	0
T63	1987	0	0	0
T64	83209	0	0	0
T65	10135	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	219	0	0
T2	494929	1	0	0
T3	72605	0	0	0
T4	100113	0	0	0
T5	368037	0	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T12	0	2	0	0
T15	29316	3	0	0
T16	29348	0	0	0
T17	5410	0	0	0
T19	0	2	0	0
T20	0	2	0	0
T21	0	1	0	0
T25	0	5	0	0
T26	12879	0	0	0
T61	0	1	0	0
T66	0	1	0	0
T68	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680073680	283884863	0	0
T1	707185	707120	0	0
T2	494929	494451	0	0
T3	72605	3158	0	0
T4	100113	18304	0	0
T5	368037	2777	0	0
T6	292753	114786	0	0
T7	695106	274554	0	0
T15	29316	586	0	0
T16	29348	1610	0	0
T17	5410	5345	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	575	0	0
T2	494929	1	0	0
T3	72605	1	0	0
T4	100113	1	0	0
T5	368037	1	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T11	0	3	0	0
T12	0	3	0	0
T13	0	1	0	0
T15	29316	4	0	0
T16	29348	1	0	0
T17	5410	0	0	0
T26	12879	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	568	0	0
T2	494929	1	0	0
T3	72605	1	0	0
T4	100113	1	0	0
T5	368037	1	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T11	0	3	0	0
T12	0	3	0	0
T13	0	1	0	0
T15	29316	4	0	0
T16	29348	1	0	0
T17	5410	0	0	0
T26	12879	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	563	0	0
T2	494929	1	0	0
T3	72605	1	0	0
T4	100113	1	0	0
T5	368037	1	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T11	0	3	0	0
T12	0	3	0	0
T13	0	1	0	0
T15	29316	3	0	0
T16	29348	1	0	0
T17	5410	0	0	0
T26	12879	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	553	0	0
T2	494929	1	0	0
T3	72605	1	0	0
T4	100113	1	0	0
T5	368037	1	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T11	0	3	0	0
T12	0	3	0	0
T13	0	1	0	0
T15	29316	3	0	0
T16	29348	1	0	0
T17	5410	0	0	0
T26	12879	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	1426	0	0
T3	72605	1	0	0
T4	100113	0	0	0
T5	368037	0	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T11	188150	2	0	0
T15	29316	0	0	0
T16	29348	0	0	0
T17	5410	0	0	0
T18	0	40	0	0
T19	0	7	0	0
T20	0	6	0	0
T26	12879	0	0	0
T58	0	1	0	0
T61	0	1	0	0
T66	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	141152	0	0
T3	72605	804	0	0
T4	100113	0	0	0
T5	368037	0	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T11	188150	433	0	0
T15	29316	0	0	0
T16	29348	0	0	0
T17	5410	0	0	0
T18	0	3850	0	0
T19	0	619	0	0
T20	0	323	0	0
T26	12879	0	0	0
T58	0	139	0	0
T61	0	38	0	0
T66	0	33	0	0
T71	0	51	0	0
T72	0	678	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	1320	0	0
T11	188150	1	0	0
T12	226078	0	0	0
T13	328672	0	0	0
T14	260830	0	0	0
T18	0	39	0	0
T19	0	6	0	0
T20	0	4	0	0
T37	4430	0	0	0
T38	48048	0	0	0
T39	3806	0	0	0
T40	125405	0	0	0
T43	0	3	0	0
T57	28343	0	0	0
T58	67857	1	0	0
T61	0	1	0	0
T66	0	1	0	0
T71	0	1	0	0
T76	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	76	0	0
T3	72605	1	0	0
T4	100113	0	0	0
T5	368037	0	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T11	188150	1	0	0
T15	29316	0	0	0
T16	29348	0	0	0
T17	5410	0	0	0
T18	0	1	0	0
T20	0	1	0	0
T22	0	1	0	0
T26	12879	0	0	0
T43	0	1	0	0
T45	0	5	0	0
T72	0	1	0	0
T77	0	1	0	0
T78	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	1268	0	0
T8	15766	166	0	0
T9	15889	136	0	0
T10	0	399	0	0
T27	0	401	0	0
T28	0	166	0	0
T29	184379	0	0	0
T30	21294	0	0	0
T31	605054	0	0	0
T32	121755	0	0	0
T33	20452	0	0	0
T34	15231	0	0	0
T35	54134	0	0	0
T36	125910	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	1058	0	0
T8	15766	136	0	0
T9	15889	106	0	0
T10	0	339	0	0
T27	0	341	0	0
T28	0	136	0	0
T29	184379	0	0	0
T30	21294	0	0	0
T31	605054	0	0	0
T32	121755	0	0	0
T33	20452	0	0	0
T34	15231	0	0	0
T35	54134	0	0	0
T36	125910	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680072205	680002623	0	0
T1	707185	707121	0	0
T2	494929	494921	0	0
T3	72605	72525	0	0
T4	100113	100108	0	0
T5	368037	368028	0	0
T6	292753	292669	0	0
T7	695106	695026	0	0
T15	29316	29237	0	0
T16	29348	29269	0	0
T17	5410	5346	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	680213133	0	0
T1	707185	707121	0	0
T2	494929	494921	0	0
T3	72605	72525	0	0
T4	100113	100108	0	0
T5	368037	368028	0	0
T6	292753	292669	0	0
T7	695106	695026	0	0
T15	29316	29237	0	0
T16	29348	29269	0	0
T17	5410	5346	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T15,T16
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T15,T16

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T4,T15
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T15,T16

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T15,T16
1	0	1	Covered	T16,T6,T5
1	1	0	Covered	T3,T15,T11
1	1	1	Covered	T16,T26,T11

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T16,T26,T11
0	1	Covered	T75,T81,T48
1	0	Covered	T23,T49,T50

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T16,T26,T11
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T23,T49,T50

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T26,T11
1	0	Not Covered
1	1	Covered	T75,T81,T48

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T15,T16
1	Covered	T37,T12,T13

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T16,T5,T26
1	Covered	T3,T15,T11

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T15,T16
1	Covered	T11,T67,T43

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T15,T11
1	Covered	T16,T5,T26

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T15,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T16,T11,T37

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T15,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T15,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T15,T16
Phase1St	198	Covered	T3,T15,T16
Phase2St	215	Covered	T3,T15,T16
Phase3St	233	Covered	T3,T15,T16
TerminalSt	249	Covered	T3,T15,T16
TimeoutSt	159	Covered	T16,T26,T11

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T3,T15,T16
IdleSt->TimeoutSt	159	Covered	T16,T26,T11
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T49,T88,T89
Phase0St->Phase1St	198	Covered	T3,T15,T16
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T11,T90,T91
Phase1St->Phase2St	215	Covered	T3,T15,T16
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T23,T92,T53
Phase2St->Phase3St	233	Covered	T3,T15,T16
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T50,T93,T94
Phase3St->TerminalSt	249	Covered	T3,T15,T16
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T15,T11,T14
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T16,T26,T11
TimeoutSt->Phase0St	172	Covered	T75,T81,T23

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T15,T16
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T26,T11
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T75,T81,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T16,T26,T11
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T16,T26,T11
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T88,T95,T96
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T15,T16
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T15,T16
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T11,T90,T91
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T15,T16
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T15,T16
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T23,T92,T53
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T15,T16
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T15,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T50,T93,T94
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T15,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T15,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T15,T11,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T15,T16
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	680372423	278	0	0
CheckAccumTrig0_A	680372423	505	0	0
CheckAccumTrig1_A	680372423	23	0	0
CheckClr_A	680372423	211	0	0
CheckEn_A	680073680	295828750	0	0
CheckPhase0_A	680372423	579	0	0
CheckPhase1_A	680372423	568	0	0
CheckPhase2_A	680372423	557	0	0
CheckPhase3_A	680372423	548	0	0
CheckTimeout0_A	680372423	1690	0	0
CheckTimeoutSt1_A	680372423	159637	0	0
CheckTimeoutSt2_A	680372423	1606	0	0
CheckTimeoutStTrig_A	680372423	61	0	0
ErrorStAllEscAsserted_A	680372423	1299	0	0
ErrorStIsTerminal_A	680372423	1089	0	0
EscStateOut_A	680072205	680002623	0	0
u_state_regs_A	680372423	680213133	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	278	0	0
T8	15766	55	0	0
T9	15889	35	0	0
T10	0	80	0	0
T27	0	65	0	0
T28	0	43	0	0
T29	184379	0	0	0
T30	21294	0	0	0
T31	605054	0	0	0
T32	121755	0	0	0
T33	20452	0	0	0
T34	15231	0	0	0
T35	54134	0	0	0
T36	125910	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	505	0	0
T3	72605	1	0	0
T4	100113	0	0	0
T5	368037	1	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T11	188150	7	0	0
T12	0	1	0	0
T13	0	1	0	0
T15	29316	1	0	0
T16	29348	1	0	0
T17	5410	0	0	0
T26	12879	1	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	23	0	0
T23	376378	1	0	0
T29	0	1	0	0
T46	504309	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T82	0	1	0	0
T84	113441	0	0	0
T85	0	1	0	0
T88	0	3	0	0
T97	0	1	0	0
T98	0	1	0	0
T99	0	1	0	0
T100	1738	0	0	0
T101	614886	0	0	0
T102	132864	0	0	0
T103	297996	0	0	0
T104	5879	0	0	0
T105	993047	0	0	0
T106	332459	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	211	0	0
T5	368037	0	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T11	188150	5	0	0
T12	226078	0	0	0
T14	0	2	0	0
T15	29316	1	0	0
T16	29348	0	0	0
T17	5410	0	0	0
T20	0	2	0	0
T22	0	2	0	0
T23	0	4	0	0
T26	12879	0	0	0
T37	4430	0	0	0
T44	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T81	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680073680	295828750	0	0
T1	707185	707120	0	0
T2	494929	494921	0	0
T3	72605	14513	0	0
T4	100113	8491	0	0
T5	368037	2810	0	0
T6	292753	1994	0	0
T7	695106	596057	0	0
T15	29316	26694	0	0
T16	29348	2152	0	0
T17	5410	5345	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	579	0	0
T3	72605	1	0	0
T4	100113	0	0	0
T5	368037	1	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T11	188150	7	0	0
T12	0	1	0	0
T13	0	1	0	0
T15	29316	1	0	0
T16	29348	1	0	0
T17	5410	0	0	0
T26	12879	1	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	568	0	0
T3	72605	1	0	0
T4	100113	0	0	0
T5	368037	1	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T11	188150	6	0	0
T12	0	1	0	0
T13	0	1	0	0
T15	29316	1	0	0
T16	29348	1	0	0
T17	5410	0	0	0
T26	12879	1	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	557	0	0
T3	72605	1	0	0
T4	100113	0	0	0
T5	368037	1	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T11	188150	6	0	0
T12	0	1	0	0
T13	0	1	0	0
T15	29316	1	0	0
T16	29348	1	0	0
T17	5410	0	0	0
T26	12879	1	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	548	0	0
T3	72605	1	0	0
T4	100113	0	0	0
T5	368037	1	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T11	188150	6	0	0
T12	0	1	0	0
T13	0	1	0	0
T15	29316	1	0	0
T16	29348	1	0	0
T17	5410	0	0	0
T26	12879	1	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	1690	0	0
T5	368037	0	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T11	188150	1	0	0
T12	226078	0	0	0
T16	29348	1	0	0
T17	5410	0	0	0
T18	0	36	0	0
T20	0	2	0	0
T22	0	3	0	0
T26	12879	2	0	0
T37	4430	0	0	0
T38	48048	0	0	0
T58	0	8	0	0
T59	0	7	0	0
T71	0	2	0	0
T75	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	159637	0	0
T5	368037	0	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T11	188150	60	0	0
T12	226078	0	0	0
T16	29348	46	0	0
T17	5410	0	0	0
T18	0	2037	0	0
T20	0	231	0	0
T22	0	895	0	0
T26	12879	205	0	0
T37	4430	0	0	0
T38	48048	0	0	0
T58	0	1023	0	0
T59	0	469	0	0
T71	0	120	0	0
T75	0	421	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	1606	0	0
T5	368037	0	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T11	188150	1	0	0
T12	226078	0	0	0
T16	29348	1	0	0
T17	5410	0	0	0
T18	0	36	0	0
T20	0	2	0	0
T22	0	3	0	0
T26	12879	2	0	0
T37	4430	0	0	0
T38	48048	0	0	0
T58	0	8	0	0
T59	0	7	0	0
T71	0	2	0	0
T75	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	61	0	0
T44	194226	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T70	956835	0	0	0
T75	272422	1	0	0
T78	28457	0	0	0
T81	0	1	0	0
T82	0	1	0	0
T90	0	1	0	0
T97	0	2	0	0
T98	0	2	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	8137	0	0	0
T110	1175	0	0	0
T111	400025	0	0	0
T112	91706	0	0	0
T113	913310	0	0	0
T114	8695	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	1299	0	0
T8	15766	203	0	0
T9	15889	184	0	0
T10	0	368	0	0
T27	0	348	0	0
T28	0	196	0	0
T29	184379	0	0	0
T30	21294	0	0	0
T31	605054	0	0	0
T32	121755	0	0	0
T33	20452	0	0	0
T34	15231	0	0	0
T35	54134	0	0	0
T36	125910	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	1089	0	0
T8	15766	173	0	0
T9	15889	154	0	0
T10	0	308	0	0
T27	0	288	0	0
T28	0	166	0	0
T29	184379	0	0	0
T30	21294	0	0	0
T31	605054	0	0	0
T32	121755	0	0	0
T33	20452	0	0	0
T34	15231	0	0	0
T35	54134	0	0	0
T36	125910	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680072205	680002623	0	0
T1	707185	707121	0	0
T2	494929	494921	0	0
T3	72605	72525	0	0
T4	100113	100108	0	0
T5	368037	368028	0	0
T6	292753	292669	0	0
T7	695106	695026	0	0
T15	29316	29237	0	0
T16	29348	29269	0	0
T17	5410	5346	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	680213133	0	0
T1	707185	707121	0	0
T2	494929	494921	0	0
T3	72605	72525	0	0
T4	100113	100108	0	0
T5	368037	368028	0	0
T6	292753	292669	0	0
T7	695106	695026	0	0
T15	29316	29237	0	0
T16	29348	29269	0	0
T17	5410	5346	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T15,T7
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T15,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T15,T7

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T15
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T15,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T15,T26,T11
1	0	1	Covered	T4,T7,T11
1	1	0	Covered	T3,T15,T11
1	1	1	Covered	T15,T11,T59

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T11,T59,T18
0	1	Covered	T59,T22,T75
1	0	Covered	T15,T20,T66

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T11,T59,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T15,T20,T66

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T11,T59
1	0	Not Covered
1	1	Covered	T59,T22,T75

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T15,T7
1	Covered	T11,T61,T62

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T15,T7
1	Covered	T11,T14,T41

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T15,T11,T14
1	Covered	T4,T15,T7

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T15,T7
1	Covered	T15,T11,T14

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T15,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T26,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T15,T7,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T15,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T4,T15,T7
Phase1St	198	Covered	T4,T15,T7
Phase2St	215	Covered	T4,T15,T7
Phase3St	233	Covered	T4,T15,T7
TerminalSt	249	Covered	T4,T15,T7
TimeoutSt	159	Covered	T15,T11,T59

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T4,T15,T7
IdleSt->TimeoutSt	159	Covered	T15,T11,T59
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T20,T47,T115
Phase0St->Phase1St	198	Covered	T4,T15,T7
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T77,T24,T116
Phase1St->Phase2St	215	Covered	T4,T15,T7
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T15,T117,T88
Phase2St->Phase3St	233	Covered	T4,T15,T7
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T24,T47,T118
Phase3St->TerminalSt	249	Covered	T4,T15,T7
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T15,T11,T14
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T11,T18,T71
TimeoutSt->Phase0St	172	Covered	T15,T59,T20

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T15,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T11,T59
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T15,T59,T20
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T11,T59,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T11,T18,T71
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T20,T47,T115
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T15,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T15,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T77,T24,T116
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T15,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T15,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T15,T117,T88
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T4,T15,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T15,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T24,T47,T118
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T15,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T15,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T15,T14,T41
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T15,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	680372423	238	0	0
CheckAccumTrig0_A	680372423	504	0	0
CheckAccumTrig1_A	680372423	23	0	0
CheckClr_A	680372423	246	0	0
CheckEn_A	680073680	307156874	0	0
CheckPhase0_A	680372423	573	0	0
CheckPhase1_A	680372423	561	0	0
CheckPhase2_A	680372423	550	0	0
CheckPhase3_A	680372423	542	0	0
CheckTimeout0_A	680372423	1249	0	0
CheckTimeoutSt1_A	680372423	149036	0	0
CheckTimeoutSt2_A	680372423	1166	0	0
CheckTimeoutStTrig_A	680372423	57	0	0
ErrorStAllEscAsserted_A	680372423	1280	0	0
ErrorStIsTerminal_A	680372423	1070	0	0
EscStateOut_A	680072205	680002623	0	0
u_state_regs_A	680372423	680213133	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	238	0	0
T8	15766	20	0	0
T9	15889	33	0	0
T10	0	51	0	0
T27	0	103	0	0
T28	0	31	0	0
T29	184379	0	0	0
T30	21294	0	0	0
T31	605054	0	0	0
T32	121755	0	0	0
T33	20452	0	0	0
T34	15231	0	0	0
T35	54134	0	0	0
T36	125910	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	504	0	0
T4	100113	1	0	0
T5	368037	0	0	0
T6	292753	0	0	0
T7	695106	1	0	0
T11	188150	3	0	0
T14	0	2	0	0
T15	29316	6	0	0
T16	29348	0	0	0
T17	5410	0	0	0
T18	0	1	0	0
T26	12879	1	0	0
T37	4430	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	23	0	0
T5	368037	0	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T11	188150	0	0	0
T12	226078	0	0	0
T15	29316	1	0	0
T16	29348	0	0	0
T17	5410	0	0	0
T20	0	1	0	0
T26	12879	0	0	0
T37	4430	0	0	0
T48	0	2	0	0
T66	0	1	0	0
T84	0	1	0	0
T88	0	1	0	0
T98	0	1	0	0
T115	0	1	0	0
T116	0	1	0	0
T119	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	246	0	0
T5	368037	0	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T11	188150	0	0	0
T12	226078	0	0	0
T14	0	1	0	0
T15	29316	6	0	0
T16	29348	0	0	0
T17	5410	0	0	0
T20	0	2	0	0
T26	12879	0	0	0
T37	4430	0	0	0
T41	0	1	0	0
T44	0	1	0	0
T61	0	2	0	0
T66	0	1	0	0
T67	0	1	0	0
T77	0	8	0	0
T112	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680073680	307156874	0	0
T1	707185	2040	0	0
T2	494929	494921	0	0
T3	72605	72524	0	0
T4	100113	12263	0	0
T5	368037	368027	0	0
T6	292753	292668	0	0
T7	695106	340285	0	0
T15	29316	3346	0	0
T16	29348	29268	0	0
T17	5410	5345	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	573	0	0
T4	100113	1	0	0
T5	368037	0	0	0
T6	292753	0	0	0
T7	695106	1	0	0
T11	188150	3	0	0
T14	0	2	0	0
T15	29316	7	0	0
T16	29348	0	0	0
T17	5410	0	0	0
T26	12879	1	0	0
T37	4430	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T59	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	561	0	0
T4	100113	1	0	0
T5	368037	0	0	0
T6	292753	0	0	0
T7	695106	1	0	0
T11	188150	3	0	0
T14	0	2	0	0
T15	29316	7	0	0
T16	29348	0	0	0
T17	5410	0	0	0
T26	12879	1	0	0
T37	4430	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T59	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	550	0	0
T4	100113	1	0	0
T5	368037	0	0	0
T6	292753	0	0	0
T7	695106	1	0	0
T11	188150	3	0	0
T14	0	2	0	0
T15	29316	6	0	0
T16	29348	0	0	0
T17	5410	0	0	0
T26	12879	1	0	0
T37	4430	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T59	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	542	0	0
T4	100113	1	0	0
T5	368037	0	0	0
T6	292753	0	0	0
T7	695106	1	0	0
T11	188150	3	0	0
T14	0	2	0	0
T15	29316	6	0	0
T16	29348	0	0	0
T17	5410	0	0	0
T26	12879	1	0	0
T37	4430	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T59	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	1249	0	0
T5	368037	0	0	0
T6	292753	0	0	0
T7	695106	0	0	0
T11	188150	1	0	0
T12	226078	0	0	0
T15	29316	1	0	0
T16	29348	0	0	0
T17	5410	0	0	0
T18	0	121	0	0
T20	0	8	0	0
T26	12879	0	0	0
T37	4430	0	0	0
T43	0	4	0	0
T59	0	1	0	0
T66	0	1	0	0
T71	0	2	0	0
T73	0	1	0	0
T74	0	15	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	149036	0	0
T11	188150	44	0	0
T12	226078	0	0	0
T13	328672	0	0	0
T14	260830	0	0	0
T18	0	7130	0	0
T20	0	573	0	0
T37	4430	0	0	0
T38	48048	0	0	0
T39	3806	0	0	0
T40	125405	0	0	0
T43	0	587	0	0
T57	28343	0	0	0
T58	67857	0	0	0
T59	0	30	0	0
T66	0	2	0	0
T69	0	167	0	0
T71	0	109	0	0
T73	0	207	0	0
T74	0	5397	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	1166	0	0
T11	188150	1	0	0
T12	226078	0	0	0
T13	328672	0	0	0
T14	260830	0	0	0
T18	0	121	0	0
T20	0	7	0	0
T22	0	1	0	0
T37	4430	0	0	0
T38	48048	0	0	0
T39	3806	0	0	0
T40	125405	0	0	0
T43	0	4	0	0
T57	28343	0	0	0
T58	67857	0	0	0
T69	0	1	0	0
T71	0	2	0	0
T73	0	1	0	0
T74	0	15	0	0
T75	0	18	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	57	0	0
T18	848457	0	0	0
T20	650568	0	0	0
T22	0	2	0	0
T24	0	1	0	0
T45	0	1	0	0
T49	0	1	0	0
T59	31196	1	0	0
T60	909	0	0	0
T61	73905	0	0	0
T62	574569	0	0	0
T63	1987	0	0	0
T64	83209	0	0	0
T65	10135	0	0	0
T71	10303	0	0	0
T75	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T82	0	1	0	0
T117	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	1280	0	0
T8	15766	187	0	0
T9	15889	169	0	0
T10	0	362	0	0
T27	0	360	0	0
T28	0	202	0	0
T29	184379	0	0	0
T30	21294	0	0	0
T31	605054	0	0	0
T32	121755	0	0	0
T33	20452	0	0	0
T34	15231	0	0	0
T35	54134	0	0	0
T36	125910	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	1070	0	0
T8	15766	157	0	0
T9	15889	139	0	0
T10	0	302	0	0
T27	0	300	0	0
T28	0	172	0	0
T29	184379	0	0	0
T30	21294	0	0	0
T31	605054	0	0	0
T32	121755	0	0	0
T33	20452	0	0	0
T34	15231	0	0	0
T35	54134	0	0	0
T36	125910	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680072205	680002623	0	0
T1	707185	707121	0	0
T2	494929	494921	0	0
T3	72605	72525	0	0
T4	100113	100108	0	0
T5	368037	368028	0	0
T6	292753	292669	0	0
T7	695106	695026	0	0
T15	29316	29237	0	0
T16	29348	29269	0	0
T17	5410	5346	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680372423	680213133	0	0
T1	707185	707121	0	0
T2	494929	494921	0	0
T3	72605	72525	0	0
T4	100113	100108	0	0
T5	368037	368028	0	0
T6	292753	292669	0	0
T7	695106	695026	0	0
T15	29316	29237	0	0
T16	29348	29269	0	0
T17	5410	5346	0	0