Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	80714	1			T20	108		T8	4		T21	11
class_i[0x1]	69825	1			T4	2		T20	257		T21	8
class_i[0x2]	57806	1			T12	4855		T21	13		T7	16
class_i[0x3]	61583	1			T1	559		T4	3		T13	4612

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	65594	1			T20	244		T8	1		T12	1156
alert[0x1]	65618	1			T1	551		T4	3		T20	94
alert[0x2]	68397	1			T1	8		T20	4		T8	1
alert[0x3]	70319	1			T4	2		T20	23		T8	1

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

269700

1

T1

559

T4

3

T20

365

esc_ping_fail

228

1

T4

2

T8

4

T7

6

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	65538	1			T20	244		T12	1156		T13	1189
esc_integrity_fail	alert[0x1]	65552	1			T1	551		T4	2		T20	94
esc_integrity_fail	alert[0x2]	68342	1			T1	8		T20	4		T12	1284
esc_integrity_fail	alert[0x3]	70268	1			T4	1		T20	23		T12	1218
esc_ping_fail	alert[0x0]	56	1			T8	1		T83	1		T239	1
esc_ping_fail	alert[0x1]	66	1			T4	1		T8	1		T7	2
esc_ping_fail	alert[0x2]	55	1			T8	1		T7	1		T239	1
esc_ping_fail	alert[0x3]	51	1			T4	1		T8	1		T7	3

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	80658	1			T20	108		T21	11		T47	2717
esc_integrity_fail	class_i[0x1]	69761	1			T20	257		T21	8		T25	64
esc_integrity_fail	class_i[0x2]	57740	1			T12	4855		T21	13		T7	10
esc_integrity_fail	class_i[0x3]	61541	1			T1	559		T4	3		T13	4612
esc_ping_fail	class_i[0x0]	56	1			T8	4		T83	4		T65	3
esc_ping_fail	class_i[0x1]	64	1			T4	2		T83	1		T278	1
esc_ping_fail	class_i[0x2]	66	1			T7	6		T83	1		T278	11
esc_ping_fail	class_i[0x3]	42	1			T239	4		T225	5		T298	9