Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	688995679	0	0	625
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	688995679	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	688995679	688846745	0	0
tb.dut.CheckAccuCntDw	0	0	625	625	0	0
tb.dut.CheckEscCntDw	0	0	625	625	0	0
tb.dut.CheckNAlerts	0	0	625	625	0	0
tb.dut.CheckNClasses	0	0	625	625	0	0
tb.dut.CheckNEscSev	0	0	625	625	0	0
tb.dut.CrashdumpKnownO_A	0	0	688995679	688846745	0	0
tb.dut.EdnKnownO_A	0	0	688995679	688846745	0	0
tb.dut.EscPKnownO_A	0	0	688995679	688846745	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	688995679	60	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	688995679	60	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	688995679	60	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	688995679	60	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	688995679	60	0	0
tb.dut.IrqAKnownO_A	0	0	688995679	688846745	0	0
tb.dut.IrqBKnownO_A	0	0	688995679	688846745	0	0
tb.dut.IrqCKnownO_A	0	0	688995679	688846745	0	0
tb.dut.IrqDKnownO_A	0	0	688995679	688846745	0	0
tb.dut.TlAReadyKnownO_A	0	0	688995679	688846745	0	0
tb.dut.TlDValidKnownO_A	0	0	688995679	688846745	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	712981015	2892963	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	712981015	7716	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	712981015	8149	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	712981015	8093	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	712981015	7910	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	712981015	9484	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	712981015	8969	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	712981015	8056	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	712981015	8008	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	712981015	8800	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	712981015	9218	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	712981015	9118	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	712981015	7748	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	712981015	8070	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	712981015	8106	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	712981015	8002	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	712981015	8880	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	712981015	8164	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	712981015	7699	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	712981015	8092	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	712981015	8936	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	712981015	8098	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	712981015	9016	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	712981015	9149	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	712981015	7992	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	712981015	8007	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	712981015	7767	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	712981015	8183	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	712981015	8348	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	712981015	8141	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	712981015	7958	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	712981015	7870	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	712981015	7911	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	712981015	9217	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	712981015	7911	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	712981015	7833	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	712981015	7863	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	712981015	7940	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	712981015	7930	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	712981015	9154	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	712981015	7881	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	712981015	8216	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	712981015	7826	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	712981015	7731	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	712981015	8785	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	712981015	7937	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	712981015	8085	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	712981015	8072	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	712981015	7926	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	712981015	8042	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	712981015	9327	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	712981015	8875	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	712981015	8096	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	712981015	7973	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	712981015	9170	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	712981015	7927	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	712981015	7843	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	712981015	7919	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	712981015	8989	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	712981015	9204	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	712981015	7867	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	712981015	8044	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	712981015	9370	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	712981015	7908	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	712981015	8763	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	712981015	8028	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	712981015	8853	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	712981015	9210	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	712981015	7831	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	712981015	7732	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	712981015	13705	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	712981015	8134	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	712981015	8976	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	712981015	9136	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	712981015	7974	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	712981015	8086	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	712981015	9053	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	712981015	7914	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	712981015	8079	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	688995679	60	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	688995679	60	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	688995679	60	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	688995679	1494	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	688995679	238995	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	688995679	324873664	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	688995679	214	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	688995679	832	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	688995679	52	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	688995679	411	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	688846277	245378947	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	688995679	926	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	688995679	904	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	688995679	892	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	688995679	869	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	688995679	883	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	688995679	110511	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	688995679	768	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	688995679	60	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	688995679	1073	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	688995679	893	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	688844635	688772694	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	625	625	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	688995679	688846745	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	688995679	60	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	688995679	60	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	688995679	60	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	688995679	1147	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	688995679	159207	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	688995679	416096826	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	688995679	207	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	688995679	476	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	688995679	20	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	688995679	169	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	688846277	314036106	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	688995679	545	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	688995679	539	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	688995679	529	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	688995679	522	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	688995679	895	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	688995679	111071	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	688995679	818	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	688995679	55	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	688995679	1081	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	688995679	901	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	688844635	688772694	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	625	625	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	688995679	688846745	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	688995679	60	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	688995679	60	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	688995679	60	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	688995679	6026	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	688995679	203396	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	688995679	407453138	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	688995679	257	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	688995679	518	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	688995679	26	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	688995679	241	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	688846277	295180224	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	688995679	603	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	688995679	594	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	688995679	585	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	688995679	573	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	688995679	814	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	688995679	98077	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	688995679	720	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	688995679	66	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	688995679	1109	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	688995679	929	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	688844635	688772694	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	625	625	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	688995679	688846745	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	688995679	60	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	688995679	60	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	688995679	60	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	688995679	5018	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	688995679	219533	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	688995679	385429208	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	688995679	223	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	688995679	497	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	688995679	29	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	688995679	213	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	688846277	276779652	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	688995679	584	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	688995679	570	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	688995679	558	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	688995679	544	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	688995679	731	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	688995679	102503	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	688995679	638	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	688995679	62	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	688995679	1101	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	688995679	921	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	688844635	688772694	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	625	625	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	688995679	688846745	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	712981015	133746401	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	712981015	712312486	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	712981015	712312486	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	712981015	192212782	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	712981015	712312486	0	0
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tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	830	830	0	0
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	830	830	0	0

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