Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	3	37	92.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	3	37	92.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	60	1			T17	1		T25	4		T62	1
class_index[0x1]	55	1			T20	1		T21	1		T25	3
class_index[0x2]	65	1			T21	1		T25	2		T62	2
class_index[0x3]	62	1			T17	1		T21	2		T25	4

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	99	1			T17	2		T21	2		T25	3
intr_timeout_cnt[1]	41	1			T25	7		T26	3		T32	1
intr_timeout_cnt[2]	21	1			T32	1		T79	2		T38	1
intr_timeout_cnt[3]	15	1			T62	2		T79	1		T199	1
intr_timeout_cnt[4]	13	1			T20	1		T62	2		T48	1
intr_timeout_cnt[5]	21	1			T25	2		T32	2		T52	3
intr_timeout_cnt[6]	12	1			T81	2		T102	1		T112	1
intr_timeout_cnt[7]	10	1			T25	1		T70	1		T32	1
intr_timeout_cnt[8]	4	1			T21	1		T52	1		T84	1
intr_timeout_cnt[9]	6	1			T21	1		T107	1		T97	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	3	37	92.50	3

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	27	1			T17	1		T32	1		T75	1
class_index[0x0]	intr_timeout_cnt[1]	9	1			T25	3		T32	1		T249	1
class_index[0x0]	intr_timeout_cnt[2]	9	1			T79	2		T180	1		T250	1
class_index[0x0]	intr_timeout_cnt[3]	6	1			T62	1		T79	1		T57	1
class_index[0x0]	intr_timeout_cnt[4]	2	1			T48	1		T251	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	1	1			T84	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	2	1			T112	1		T22	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	3	1			T25	1		T252	1		T253	1
class_index[0x0]	intr_timeout_cnt[9]	1	1			T244	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	20	1			T75	1		T163	1		T254	1
class_index[0x1]	intr_timeout_cnt[1]	12	1			T25	3		T26	1		T79	1
class_index[0x1]	intr_timeout_cnt[2]	4	1			T180	1		T243	2		T255	1
class_index[0x1]	intr_timeout_cnt[3]	2	1			T62	1		T84	1		-	-
class_index[0x1]	intr_timeout_cnt[4]	4	1			T20	1		T49	1		T81	1
class_index[0x1]	intr_timeout_cnt[5]	8	1			T32	1		T97	1		T256	3
class_index[0x1]	intr_timeout_cnt[7]	1	1			T32	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	2	1			T84	1		T22	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	2	1			T21	1		T107	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	24	1			T71	1		T77	1		T52	2
class_index[0x2]	intr_timeout_cnt[1]	12	1			T26	1		T76	1		T77	1
class_index[0x2]	intr_timeout_cnt[2]	4	1			T249	1		T242	1		T243	1
class_index[0x2]	intr_timeout_cnt[3]	3	1			T97	1		T257	1		T258	1
class_index[0x2]	intr_timeout_cnt[4]	4	1			T62	2		T91	1		T24	1
class_index[0x2]	intr_timeout_cnt[5]	9	1			T25	2		T32	1		T52	3
class_index[0x2]	intr_timeout_cnt[6]	6	1			T81	1		T102	1		T244	4
class_index[0x2]	intr_timeout_cnt[7]	2	1			T70	1		T97	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	1	1			T21	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	28	1			T17	1		T21	2		T25	3
class_index[0x3]	intr_timeout_cnt[1]	8	1			T25	1		T26	1		T180	1
class_index[0x3]	intr_timeout_cnt[2]	4	1			T32	1		T38	1		T243	1
class_index[0x3]	intr_timeout_cnt[3]	4	1			T199	1		T91	1		T105	1
class_index[0x3]	intr_timeout_cnt[4]	3	1			T79	1		T253	1		T259	1
class_index[0x3]	intr_timeout_cnt[5]	3	1			T260	2		T261	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	4	1			T81	1		T84	1		T105	2
class_index[0x3]	intr_timeout_cnt[7]	4	1			T262	1		T258	2		T24	1
class_index[0x3]	intr_timeout_cnt[8]	1	1			T52	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	3	1			T97	1		T263	1		T24	1