Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	357490	1			T1	1272		T2	2		T3	27
all_values[1]	357490	1			T1	1272		T2	2		T3	27
all_values[2]	357490	1			T1	1272		T2	2		T3	27
all_values[3]	357490	1			T1	1272		T2	2		T3	27

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

710586

1

T1

2511

T2

4

T3

55

auto[1]

719374

1

T1

2577

T2

4

T3

53

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

843121

1

T1

2626

T2

5

T3

58

auto[1]

586839

1

T1

2462

T2

3

T3

50

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	100990	1			T1	322		T3	7		T17	4
all_values[0]	auto[0]	auto[1]	76528	1			T1	317		T3	7		T17	4
all_values[0]	auto[1]	auto[0]	102514	1			T1	319		T2	1		T3	8
all_values[0]	auto[1]	auto[1]	77458	1			T1	314		T2	1		T3	5
all_values[1]	auto[0]	auto[0]	106323	1			T1	328		T2	2		T3	9
all_values[1]	auto[0]	auto[1]	71874	1			T1	313		T3	6		T17	4
all_values[1]	auto[1]	auto[0]	107467	1			T1	322		T3	6		T4	11
all_values[1]	auto[1]	auto[1]	71826	1			T1	309		T3	6		T4	2
all_values[2]	auto[0]	auto[0]	104935	1			T1	322		T2	1		T3	9
all_values[2]	auto[0]	auto[1]	72831	1			T1	304		T2	1		T3	8
all_values[2]	auto[1]	auto[0]	106529	1			T1	337		T3	5		T4	9
all_values[2]	auto[1]	auto[1]	73195	1			T1	309		T3	5		T4	4
all_values[3]	auto[0]	auto[0]	105965	1			T1	320		T3	5		T17	4
all_values[3]	auto[0]	auto[1]	71140	1			T1	285		T3	4		T17	3
all_values[3]	auto[1]	auto[0]	108398	1			T1	356		T2	1		T3	9
all_values[3]	auto[1]	auto[1]	71987	1			T1	311		T2	1		T3	9