Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	357490	1			T1	1272		T2	2		T3	27
all_pins[1]	357490	1			T1	1272		T2	2		T3	27
all_pins[2]	357490	1			T1	1272		T2	2		T3	27
all_pins[3]	357490	1			T1	1272		T2	2		T3	27

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1135494	1			T1	3845		T2	6		T3	83
values[0x1]	294466	1			T1	1243		T2	2		T3	25
transitions[0x0=>0x1]	194888	1			T1	795		T2	1		T3	16
transitions[0x1=>0x0]	195144	1			T1	795		T2	2		T3	17

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	280032	1			T1	958		T2	1		T3	22
all_pins[0]	values[0x1]	77458	1			T1	314		T2	1		T3	5
all_pins[0]	transitions[0x0=>0x1]	76797	1			T1	312		T3	4		T17	3
all_pins[0]	transitions[0x1=>0x0]	71582	1			T1	309		T2	1		T3	9
all_pins[1]	values[0x0]	285664	1			T1	963		T2	2		T3	21
all_pins[1]	values[0x1]	71826	1			T1	309		T3	6		T4	2
all_pins[1]	transitions[0x0=>0x1]	38614	1			T1	159		T3	3		T4	2
all_pins[1]	transitions[0x1=>0x0]	44246	1			T1	164		T2	1		T3	2
all_pins[2]	values[0x0]	284295	1			T1	963		T2	2		T3	22
all_pins[2]	values[0x1]	73195	1			T1	309		T3	5		T4	4
all_pins[2]	transitions[0x0=>0x1]	40490	1			T1	155		T3	3		T4	4
all_pins[2]	transitions[0x1=>0x0]	39121	1			T1	155		T3	4		T4	2
all_pins[3]	values[0x0]	285503	1			T1	961		T2	1		T3	18
all_pins[3]	values[0x1]	71987	1			T1	311		T2	1		T3	9
all_pins[3]	transitions[0x0=>0x1]	38987	1			T1	169		T2	1		T3	6
all_pins[3]	transitions[0x1=>0x0]	40195	1			T1	167		T3	2		T4	4