Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	95307	1			T1	509		T6	52		T12	1340
accum_cnt_1000	224566	1			T1	845		T19	105		T5	648
accum_cnt_100	25085	1			T1	36		T19	38		T5	49
accum_cnt_50	80108	1			T1	61		T3	17		T17	14
accum_cnt_10	193232	1			T1	89		T2	2		T3	12
accum_cnt_0	382179	1			T1	1953		T2	6		T3	23

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	262778	1			T1	963		T2	2		T3	13
class_index[0x1]	262778	1			T1	963		T2	2		T3	13
class_index[0x2]	262778	1			T1	963		T2	2		T3	13
class_index[0x3]	262778	1			T1	963		T2	2		T3	13

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	26886	1			T1	231		T12	449		T13	601
class_index[0x0]	accum_cnt_1000	65127	1			T1	609		T12	411		T13	662
class_index[0x0]	accum_cnt_100	7430	1			T1	28		T20	12		T12	25
class_index[0x0]	accum_cnt_50	20654	1			T1	35		T17	8		T12	20
class_index[0x0]	accum_cnt_10	40691	1			T1	38		T2	2		T17	8
class_index[0x0]	accum_cnt_0	87118	1			T1	22		T3	13		T4	9
class_index[0x1]	accum_cnt_2000	22157	1			T1	278		T12	648		T68	509
class_index[0x1]	accum_cnt_1000	51755	1			T1	235		T19	55		T5	648
class_index[0x1]	accum_cnt_100	6584	1			T1	8		T19	17		T5	49
class_index[0x1]	accum_cnt_50	18525	1			T1	15		T3	2		T19	15
class_index[0x1]	accum_cnt_10	52356	1			T1	18		T3	6		T17	16
class_index[0x1]	accum_cnt_0	103662	1			T1	50		T2	2		T3	5
class_index[0x2]	accum_cnt_2000	24170	1			T6	52		T12	243		T13	604
class_index[0x2]	accum_cnt_1000	54467	1			T6	844		T12	216		T13	667
class_index[0x2]	accum_cnt_100	5271	1			T6	45		T12	15		T13	34
class_index[0x2]	accum_cnt_50	21272	1			T1	10		T3	7		T6	40
class_index[0x2]	accum_cnt_10	51682	1			T1	19		T3	3		T4	4
class_index[0x2]	accum_cnt_0	93922	1			T1	934		T2	2		T3	3
class_index[0x3]	accum_cnt_2000	22094	1			T14	116		T68	475		T115	315
class_index[0x3]	accum_cnt_1000	53217	1			T1	1		T19	50		T14	117
class_index[0x3]	accum_cnt_100	5800	1			T19	21		T14	6		T25	63
class_index[0x3]	accum_cnt_50	19657	1			T1	1		T3	8		T17	6
class_index[0x3]	accum_cnt_10	48503	1			T1	14		T3	3		T4	1
class_index[0x3]	accum_cnt_0	97477	1			T1	947		T2	2		T3	2