Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	9727	1			T12	9		T14	632		T47	1
alert[0x1]	9230	1			T7	2		T14	562		T238	2
alert[0x2]	4491	1			T1	101		T2	1		T13	2
alert[0x3]	6158	1			T1	933		T13	6		T14	2273
alert[0x4]	4320	1			T83	1		T239	1		T278	1
alert[0x5]	7970	1			T1	2		T8	1		T47	2
alert[0x6]	3635	1			T1	97		T7	1		T15	1
alert[0x7]	7469	1			T14	73		T47	2		T240	1
alert[0x8]	4596	1			T8	3		T14	523		T83	1
alert[0x9]	10172	1			T21	2		T14	131		T47	2
alert[0xa]	6029	1			T1	145		T8	1		T7	1
alert[0xb]	5702	1			T7	1		T70	13		T270	5
alert[0xc]	12233	1			T47	3		T83	1		T278	1
alert[0xd]	2923	1			T1	54		T83	1		T274	1
alert[0xe]	2749	1			T1	67		T2	4		T8	1
alert[0xf]	8551	1			T1	53		T8	1		T7	1
alert[0x10]	6735	1			T1	17		T12	10		T14	237
alert[0x11]	3892	1			T1	27		T4	1		T20	9
alert[0x12]	2015	1			T1	15		T8	1		T12	2
alert[0x13]	20400	1			T14	2040		T47	2		T63	1
alert[0x14]	5475	1			T51	4		T293	287		T294	1
alert[0x15]	6197	1			T12	2		T25	1		T62	3
alert[0x16]	11274	1			T12	7		T13	2		T21	4
alert[0x17]	6449	1			T5	1		T12	3		T14	182
alert[0x18]	2940	1			T14	108		T51	11		T295	30
alert[0x19]	5814	1			T47	1		T83	1		T278	2
alert[0x1a]	8923	1			T5	1		T20	2		T7	1
alert[0x1b]	11967	1			T1	7		T47	1		T83	1
alert[0x1c]	6112	1			T7	1		T14	124		T116	36
alert[0x1d]	9438	1			T1	81		T47	11		T70	1
alert[0x1e]	10375	1			T14	2092		T83	1		T70	4
alert[0x1f]	6866	1			T1	31		T12	1		T7	1
alert[0x20]	5044	1			T7	2		T51	2		T296	4
alert[0x21]	8407	1			T14	112		T239	2		T51	23
alert[0x22]	10805	1			T1	57		T21	1		T83	2
alert[0x23]	6600	1			T1	47		T14	1319		T278	1
alert[0x24]	3319	1			T14	19		T26	3		T70	3
alert[0x25]	5692	1			T1	261		T13	4		T47	1
alert[0x26]	6544	1			T1	61		T20	1		T7	1
alert[0x27]	15625	1			T1	81		T4	1		T14	19
alert[0x28]	4102	1			T5	2		T8	1		T12	2
alert[0x29]	3137	1			T4	1		T14	66		T83	1
alert[0x2a]	5425	1			T14	113		T278	1		T51	4
alert[0x2b]	7257	1			T1	20		T6	1		T7	2
alert[0x2c]	4452	1			T1	45		T21	19		T14	135
alert[0x2d]	5646	1			T1	32		T12	2		T278	1
alert[0x2e]	12712	1			T4	1		T7	1		T47	8
alert[0x2f]	7751	1			T13	1		T274	1		T65	1
alert[0x30]	4213	1			T1	236		T14	42		T63	1
alert[0x31]	3812	1			T12	2		T21	2		T83	1
alert[0x32]	9110	1			T14	129		T83	1		T70	5
alert[0x33]	8351	1			T21	9		T48	2		T294	1
alert[0x34]	2591	1			T1	30		T14	72		T70	1
alert[0x35]	7530	1			T1	495		T8	1		T12	1
alert[0x36]	2405	1			T1	98		T12	2		T47	1
alert[0x37]	4620	1			T12	7		T83	1		T116	276
alert[0x38]	11646	1			T8	1		T14	403		T116	71
alert[0x39]	7965	1			T1	186		T8	1		T13	2
alert[0x3a]	5133	1			T14	30		T116	696		T27	1256
alert[0x3b]	8919	1			T1	24		T21	9		T14	2204
alert[0x3c]	5147	1			T49	1		T51	1		T295	83
alert[0x3d]	8021	1			T47	2		T274	1		T32	18
alert[0x3e]	11067	1			T8	1		T25	1		T116	141
alert[0x3f]	3151	1			T14	88		T27	243		T32	8
alert[0x40]	5284	1			T1	91		T12	3		T13	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	97040	1			T1	3		T5	4		T8	12
class_i[0x1]	107879	1			T1	3365		T8	1		T6	1
class_i[0x2]	97484	1			T2	5		T4	4		T20	12
class_i[0x3]	149907	1			T1	26		T13	6		T21	30

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

451718

1

T1

3394

T2

5

T20

12

alert_ping_fail

592

1

T4

4

T5

4

T8

13

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	9722	1			T12	9		T14	632		T47	1
alert_integrity_fail	alert[0x1]	9221	1			T14	562		T238	2		T68	2
alert_integrity_fail	alert[0x2]	4485	1			T1	101		T2	1		T13	2
alert_integrity_fail	alert[0x3]	6150	1			T1	933		T13	6		T14	2273
alert_integrity_fail	alert[0x4]	4311	1			T26	12		T32	2		T295	75
alert_integrity_fail	alert[0x5]	7963	1			T1	2		T47	2		T68	21
alert_integrity_fail	alert[0x6]	3624	1			T1	97		T70	1		T116	49
alert_integrity_fail	alert[0x7]	7458	1			T14	73		T47	2		T27	23
alert_integrity_fail	alert[0x8]	4583	1			T14	523		T270	4		T110	482
alert_integrity_fail	alert[0x9]	10168	1			T21	2		T14	131		T47	2
alert_integrity_fail	alert[0xa]	6008	1			T1	145		T14	33		T25	6
alert_integrity_fail	alert[0xb]	5698	1			T70	13		T270	5		T297	4
alert_integrity_fail	alert[0xc]	12222	1			T47	3		T70	4		T27	11
alert_integrity_fail	alert[0xd]	2915	1			T1	54		T49	9		T293	50
alert_integrity_fail	alert[0xe]	2739	1			T1	67		T2	4		T14	298
alert_integrity_fail	alert[0xf]	8540	1			T1	53		T14	518		T295	20
alert_integrity_fail	alert[0x10]	6729	1			T1	17		T12	10		T14	237
alert_integrity_fail	alert[0x11]	3886	1			T1	27		T20	9		T80	2
alert_integrity_fail	alert[0x12]	2003	1			T1	15		T12	2		T21	1
alert_integrity_fail	alert[0x13]	20386	1			T14	2040		T47	2		T116	8
alert_integrity_fail	alert[0x14]	5465	1			T51	4		T293	287		T53	3
alert_integrity_fail	alert[0x15]	6183	1			T12	2		T25	1		T62	3
alert_integrity_fail	alert[0x16]	11265	1			T12	7		T13	2		T21	4
alert_integrity_fail	alert[0x17]	6440	1			T12	3		T14	182		T51	12
alert_integrity_fail	alert[0x18]	2932	1			T14	108		T51	11		T295	30
alert_integrity_fail	alert[0x19]	5802	1			T47	1		T116	7		T51	113
alert_integrity_fail	alert[0x1a]	8911	1			T20	2		T62	5		T68	2
alert_integrity_fail	alert[0x1b]	11958	1			T1	7		T47	1		T26	6
alert_integrity_fail	alert[0x1c]	6103	1			T14	124		T116	36		T27	41
alert_integrity_fail	alert[0x1d]	9432	1			T1	81		T47	11		T70	1
alert_integrity_fail	alert[0x1e]	10369	1			T14	2092		T70	4		T27	54
alert_integrity_fail	alert[0x1f]	6862	1			T1	31		T12	1		T51	14
alert_integrity_fail	alert[0x20]	5039	1			T51	2		T296	4		T293	40
alert_integrity_fail	alert[0x21]	8393	1			T14	112		T51	23		T108	5
alert_integrity_fail	alert[0x22]	10794	1			T1	57		T21	1		T70	1
alert_integrity_fail	alert[0x23]	6596	1			T1	47		T14	1319		T70	9
alert_integrity_fail	alert[0x24]	3309	1			T14	19		T26	3		T70	3
alert_integrity_fail	alert[0x25]	5687	1			T1	261		T13	4		T47	1
alert_integrity_fail	alert[0x26]	6528	1			T1	61		T20	1		T14	179
alert_integrity_fail	alert[0x27]	15617	1			T1	81		T14	19		T116	157
alert_integrity_fail	alert[0x28]	4090	1			T12	2		T116	6		T49	13
alert_integrity_fail	alert[0x29]	3129	1			T14	66		T27	16		T51	8
alert_integrity_fail	alert[0x2a]	5417	1			T14	113		T51	4		T295	94
alert_integrity_fail	alert[0x2b]	7244	1			T1	20		T14	2		T68	4
alert_integrity_fail	alert[0x2c]	4438	1			T1	45		T21	19		T14	135
alert_integrity_fail	alert[0x2d]	5633	1			T1	32		T12	2		T64	3
alert_integrity_fail	alert[0x2e]	12701	1			T47	8		T25	1		T70	7
alert_integrity_fail	alert[0x2f]	7739	1			T13	1		T51	1		T295	213
alert_integrity_fail	alert[0x30]	4200	1			T1	236		T14	42		T295	190
alert_integrity_fail	alert[0x31]	3805	1			T12	2		T21	2		T116	19
alert_integrity_fail	alert[0x32]	9107	1			T14	129		T70	5		T116	9
alert_integrity_fail	alert[0x33]	8343	1			T21	9		T48	2		T110	20
alert_integrity_fail	alert[0x34]	2585	1			T1	30		T14	72		T70	1
alert_integrity_fail	alert[0x35]	7517	1			T1	495		T12	1		T13	4
alert_integrity_fail	alert[0x36]	2391	1			T1	98		T12	2		T47	1
alert_integrity_fail	alert[0x37]	4612	1			T12	7		T116	276		T51	1
alert_integrity_fail	alert[0x38]	11637	1			T14	403		T116	71		T27	42
alert_integrity_fail	alert[0x39]	7956	1			T1	186		T13	2		T14	28
alert_integrity_fail	alert[0x3a]	5126	1			T14	30		T116	696		T27	1256
alert_integrity_fail	alert[0x3b]	8912	1			T1	24		T21	9		T14	2204
alert_integrity_fail	alert[0x3c]	5141	1			T49	1		T51	1		T295	83
alert_integrity_fail	alert[0x3d]	8015	1			T47	2		T32	18		T49	3
alert_integrity_fail	alert[0x3e]	11060	1			T25	1		T116	141		T27	369
alert_integrity_fail	alert[0x3f]	3144	1			T14	88		T27	243		T32	8
alert_integrity_fail	alert[0x40]	5280	1			T1	91		T12	3		T13	1
alert_ping_fail	alert[0x0]	5	1			T298	1		T202	1		T299	1
alert_ping_fail	alert[0x1]	9	1			T7	2		T189	1		T197	2
alert_ping_fail	alert[0x2]	6	1			T65	1		T300	1		T301	1
alert_ping_fail	alert[0x3]	8	1			T302	1		T303	1		T202	1
alert_ping_fail	alert[0x4]	9	1			T83	1		T239	1		T278	1
alert_ping_fail	alert[0x5]	7	1			T8	1		T304	1		T305	1
alert_ping_fail	alert[0x6]	11	1			T7	1		T15	1		T239	1
alert_ping_fail	alert[0x7]	11	1			T240	1		T225	1		T298	1
alert_ping_fail	alert[0x8]	13	1			T8	3		T83	1		T305	1
alert_ping_fail	alert[0x9]	4	1			T225	1		T306	1		T302	1
alert_ping_fail	alert[0xa]	21	1			T8	1		T7	1		T83	1
alert_ping_fail	alert[0xb]	4	1			T7	1		T307	2		T308	1
alert_ping_fail	alert[0xc]	11	1			T83	1		T278	1		T189	1
alert_ping_fail	alert[0xd]	8	1			T83	1		T274	1		T65	1
alert_ping_fail	alert[0xe]	10	1			T8	1		T7	1		T274	1
alert_ping_fail	alert[0xf]	11	1			T8	1		T7	1		T274	1
alert_ping_fail	alert[0x10]	6	1			T239	1		T278	1		T65	1
alert_ping_fail	alert[0x11]	6	1			T4	1		T37	1		T298	1
alert_ping_fail	alert[0x12]	12	1			T8	1		T278	1		T189	1
alert_ping_fail	alert[0x13]	14	1			T63	1		T278	2		T225	1
alert_ping_fail	alert[0x14]	10	1			T294	1		T309	3		T197	1
alert_ping_fail	alert[0x15]	14	1			T240	2		T274	1		T225	1
alert_ping_fail	alert[0x16]	9	1			T278	1		T225	1		T306	1
alert_ping_fail	alert[0x17]	9	1			T5	1		T306	1		T310	1
alert_ping_fail	alert[0x18]	8	1			T37	1		T197	2		T307	1
alert_ping_fail	alert[0x19]	12	1			T83	1		T278	2		T274	1
alert_ping_fail	alert[0x1a]	12	1			T5	1		T7	1		T197	1
alert_ping_fail	alert[0x1b]	9	1			T83	1		T65	1		T311	1
alert_ping_fail	alert[0x1c]	9	1			T7	1		T292	1		T312	1
alert_ping_fail	alert[0x1d]	6	1			T274	1		T225	1		T306	1
alert_ping_fail	alert[0x1e]	6	1			T83	1		T313	1		T298	1
alert_ping_fail	alert[0x1f]	4	1			T7	1		T313	1		T306	1
alert_ping_fail	alert[0x20]	5	1			T7	2		T298	1		T306	1
alert_ping_fail	alert[0x21]	14	1			T239	2		T36	2		T304	1
alert_ping_fail	alert[0x22]	11	1			T83	2		T240	1		T274	1
alert_ping_fail	alert[0x23]	4	1			T278	1		T314	1		T315	1
alert_ping_fail	alert[0x24]	10	1			T315	1		T316	1		T299	1
alert_ping_fail	alert[0x25]	5	1			T197	1		T311	1		T317	1
alert_ping_fail	alert[0x26]	16	1			T7	1		T83	1		T274	1
alert_ping_fail	alert[0x27]	8	1			T4	1		T65	1		T304	1
alert_ping_fail	alert[0x28]	12	1			T5	2		T8	1		T15	1
alert_ping_fail	alert[0x29]	8	1			T4	1		T83	1		T298	1
alert_ping_fail	alert[0x2a]	8	1			T278	1		T298	1		T306	1
alert_ping_fail	alert[0x2b]	13	1			T6	1		T7	2		T278	1
alert_ping_fail	alert[0x2c]	14	1			T63	1		T274	1		T37	1
alert_ping_fail	alert[0x2d]	13	1			T278	1		T65	2		T225	1
alert_ping_fail	alert[0x2e]	11	1			T4	1		T7	1		T318	1
alert_ping_fail	alert[0x2f]	12	1			T274	1		T65	1		T304	2
alert_ping_fail	alert[0x30]	13	1			T63	1		T278	1		T274	1
alert_ping_fail	alert[0x31]	7	1			T83	1		T304	1		T307	1
alert_ping_fail	alert[0x32]	3	1			T83	1		T302	1		T200	1
alert_ping_fail	alert[0x33]	8	1			T294	1		T319	1		T314	1
alert_ping_fail	alert[0x34]	6	1			T313	1		T303	2		T320	1
alert_ping_fail	alert[0x35]	13	1			T8	1		T239	1		T313	1
alert_ping_fail	alert[0x36]	14	1			T239	1		T278	1		T274	1
alert_ping_fail	alert[0x37]	8	1			T83	1		T202	1		T315	1
alert_ping_fail	alert[0x38]	9	1			T8	1		T307	2		T310	1
alert_ping_fail	alert[0x39]	9	1			T8	1		T7	1		T225	1
alert_ping_fail	alert[0x3a]	7	1			T65	1		T225	1		T298	1
alert_ping_fail	alert[0x3b]	7	1			T304	1		T319	1		T307	1
alert_ping_fail	alert[0x3c]	6	1			T319	1		T197	1		T321	1
alert_ping_fail	alert[0x3d]	6	1			T274	1		T37	1		T298	1
alert_ping_fail	alert[0x3e]	7	1			T8	1		T306	1		T303	1
alert_ping_fail	alert[0x3f]	7	1			T37	1		T225	1		T202	1
alert_ping_fail	alert[0x40]	4	1			T298	1		T317	2		T322	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	96810	1			T1	3		T12	10		T13	3
alert_integrity_fail	class_i[0x1]	107802	1			T1	3365		T12	10		T47	25
alert_integrity_fail	class_i[0x2]	97375	1			T2	5		T20	12		T12	33
alert_integrity_fail	class_i[0x3]	149731	1			T1	26		T13	6		T21	30
alert_ping_fail	class_i[0x0]	230	1			T5	4		T8	12		T7	2
alert_ping_fail	class_i[0x1]	77	1			T8	1		T6	1		T7	2
alert_ping_fail	class_i[0x2]	109	1			T4	4		T83	1		T239	7
alert_ping_fail	class_i[0x3]	176	1			T7	13		T83	15		T189	4