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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.67 99.99 98.77 100.00 100.00 100.00 99.38 99.52


Total test records in report: 830
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T133 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2981877794 May 30 01:15:15 PM PDT 24 May 30 01:20:00 PM PDT 24 13100074671 ps
T132 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3040827925 May 30 01:14:36 PM PDT 24 May 30 01:21:01 PM PDT 24 5483229339 ps
T775 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.963286040 May 30 01:14:50 PM PDT 24 May 30 01:14:57 PM PDT 24 41207314 ps
T159 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2510606767 May 30 01:15:14 PM PDT 24 May 30 01:16:23 PM PDT 24 926979176 ps
T776 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2814965375 May 30 01:15:29 PM PDT 24 May 30 01:15:32 PM PDT 24 17892677 ps
T777 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3381251467 May 30 01:14:51 PM PDT 24 May 30 01:15:05 PM PDT 24 1441945673 ps
T778 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.506236728 May 30 01:15:13 PM PDT 24 May 30 01:15:54 PM PDT 24 509896694 ps
T142 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1172911091 May 30 01:14:26 PM PDT 24 May 30 01:19:28 PM PDT 24 8204172603 ps
T779 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.4094783575 May 30 01:14:52 PM PDT 24 May 30 01:19:15 PM PDT 24 13469529863 ps
T148 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3093947463 May 30 01:15:14 PM PDT 24 May 30 01:27:04 PM PDT 24 9032399606 ps
T144 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.15397316 May 30 01:15:30 PM PDT 24 May 30 01:20:20 PM PDT 24 7136218927 ps
T124 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.442417906 May 30 01:15:29 PM PDT 24 May 30 01:24:52 PM PDT 24 4572880518 ps
T147 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.4046154291 May 30 01:14:37 PM PDT 24 May 30 01:16:10 PM PDT 24 1566763329 ps
T780 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.4170153848 May 30 01:15:29 PM PDT 24 May 30 01:15:31 PM PDT 24 14523561 ps
T781 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3740051568 May 30 01:15:29 PM PDT 24 May 30 01:15:36 PM PDT 24 128964302 ps
T782 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2338242597 May 30 01:15:26 PM PDT 24 May 30 01:15:48 PM PDT 24 542282762 ps
T783 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.209930880 May 30 01:15:15 PM PDT 24 May 30 01:15:21 PM PDT 24 33450532 ps
T784 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.98354194 May 30 01:15:34 PM PDT 24 May 30 01:15:52 PM PDT 24 150118797 ps
T785 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1384701460 May 30 01:15:33 PM PDT 24 May 30 01:15:36 PM PDT 24 17311624 ps
T786 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3892776408 May 30 01:14:42 PM PDT 24 May 30 01:14:52 PM PDT 24 90770334 ps
T787 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1645900145 May 30 01:14:29 PM PDT 24 May 30 01:14:33 PM PDT 24 305898974 ps
T146 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1262098423 May 30 01:14:53 PM PDT 24 May 30 01:16:22 PM PDT 24 3045623848 ps
T788 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2047586583 May 30 01:14:36 PM PDT 24 May 30 01:17:23 PM PDT 24 4951621075 ps
T789 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.724185940 May 30 01:15:13 PM PDT 24 May 30 01:15:15 PM PDT 24 21884466 ps
T790 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1415059099 May 30 01:14:58 PM PDT 24 May 30 01:15:03 PM PDT 24 33108945 ps
T791 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1996937063 May 30 01:15:29 PM PDT 24 May 30 01:15:38 PM PDT 24 857354519 ps
T792 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1859258031 May 30 01:14:52 PM PDT 24 May 30 01:14:54 PM PDT 24 18317719 ps
T151 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1322518614 May 30 01:15:30 PM PDT 24 May 30 01:20:44 PM PDT 24 9296739468 ps
T176 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1448654293 May 30 01:15:29 PM PDT 24 May 30 01:16:54 PM PDT 24 4739947010 ps
T793 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2708060167 May 30 01:15:36 PM PDT 24 May 30 01:15:38 PM PDT 24 26112186 ps
T794 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.690511660 May 30 01:14:51 PM PDT 24 May 30 01:15:04 PM PDT 24 89520935 ps
T795 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2032294082 May 30 01:14:43 PM PDT 24 May 30 01:14:48 PM PDT 24 21694568 ps
T145 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.11786956 May 30 01:15:31 PM PDT 24 May 30 01:21:37 PM PDT 24 11497043076 ps
T141 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1031452317 May 30 01:15:29 PM PDT 24 May 30 01:20:35 PM PDT 24 3918136731 ps
T796 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.384989239 May 30 01:15:32 PM PDT 24 May 30 01:15:35 PM PDT 24 10921445 ps
T160 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.344472437 May 30 01:14:37 PM PDT 24 May 30 01:14:42 PM PDT 24 92986990 ps
T797 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2596284745 May 30 01:14:38 PM PDT 24 May 30 01:14:46 PM PDT 24 295462288 ps
T798 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.38020752 May 30 01:14:37 PM PDT 24 May 30 01:21:12 PM PDT 24 18451195567 ps
T799 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3083408958 May 30 01:15:14 PM PDT 24 May 30 01:15:16 PM PDT 24 9073672 ps
T800 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1581425286 May 30 01:14:29 PM PDT 24 May 30 01:15:13 PM PDT 24 8939451655 ps
T801 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2408871812 May 30 01:15:15 PM PDT 24 May 30 01:15:26 PM PDT 24 1004618137 ps
T802 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.41799933 May 30 01:14:38 PM PDT 24 May 30 01:14:49 PM PDT 24 369476616 ps
T355 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2587724937 May 30 01:14:51 PM PDT 24 May 30 01:23:23 PM PDT 24 6750527620 ps
T803 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.903365206 May 30 01:15:30 PM PDT 24 May 30 01:15:34 PM PDT 24 49614982 ps
T168 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1527516818 May 30 01:14:39 PM PDT 24 May 30 01:14:44 PM PDT 24 96841851 ps
T161 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.921653967 May 30 01:14:29 PM PDT 24 May 30 01:14:33 PM PDT 24 36284275 ps
T804 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3529934786 May 30 01:14:38 PM PDT 24 May 30 01:14:44 PM PDT 24 65011923 ps
T805 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.4103399249 May 30 01:14:52 PM PDT 24 May 30 01:15:02 PM PDT 24 475365595 ps
T806 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.4232880392 May 30 01:15:39 PM PDT 24 May 30 01:15:41 PM PDT 24 7128333 ps
T807 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2093137071 May 30 01:15:29 PM PDT 24 May 30 01:15:36 PM PDT 24 61619347 ps
T808 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3154377806 May 30 01:14:51 PM PDT 24 May 30 01:15:06 PM PDT 24 198482016 ps
T152 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1441529953 May 30 01:14:52 PM PDT 24 May 30 01:17:43 PM PDT 24 11587875224 ps
T809 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2152934618 May 30 01:15:29 PM PDT 24 May 30 01:15:34 PM PDT 24 187096022 ps
T810 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1811382015 May 30 01:15:15 PM PDT 24 May 30 01:15:17 PM PDT 24 8660403 ps
T811 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3933847033 May 30 01:14:58 PM PDT 24 May 30 01:15:23 PM PDT 24 1391160028 ps
T812 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.690661484 May 30 01:15:29 PM PDT 24 May 30 01:15:35 PM PDT 24 67304118 ps
T813 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1919109391 May 30 01:14:38 PM PDT 24 May 30 01:14:41 PM PDT 24 25929037 ps
T814 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1240204387 May 30 01:14:50 PM PDT 24 May 30 01:16:17 PM PDT 24 1703753619 ps
T815 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1170934519 May 30 01:14:51 PM PDT 24 May 30 01:15:12 PM PDT 24 565171155 ps
T816 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.279251627 May 30 01:15:37 PM PDT 24 May 30 01:15:45 PM PDT 24 470931944 ps
T166 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1629421570 May 30 01:14:50 PM PDT 24 May 30 01:15:39 PM PDT 24 458461358 ps
T817 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.4057963217 May 30 01:14:38 PM PDT 24 May 30 01:14:47 PM PDT 24 349679899 ps
T818 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3037814390 May 30 01:15:27 PM PDT 24 May 30 01:15:31 PM PDT 24 20867601 ps
T357 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.34852254 May 30 01:14:43 PM PDT 24 May 30 01:20:21 PM PDT 24 30885065684 ps
T819 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1144756331 May 30 01:15:15 PM PDT 24 May 30 01:15:25 PM PDT 24 66406711 ps
T820 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.114246564 May 30 01:14:51 PM PDT 24 May 30 01:14:57 PM PDT 24 42462105 ps
T821 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2337304984 May 30 01:15:13 PM PDT 24 May 30 01:15:39 PM PDT 24 354078095 ps
T149 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2501480766 May 30 01:14:37 PM PDT 24 May 30 01:30:01 PM PDT 24 25085763434 ps
T822 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.419952242 May 30 01:15:31 PM PDT 24 May 30 01:15:39 PM PDT 24 303279447 ps
T823 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.2218772238 May 30 01:15:30 PM PDT 24 May 30 01:15:33 PM PDT 24 6183433 ps
T824 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3461574415 May 30 01:14:28 PM PDT 24 May 30 01:14:34 PM PDT 24 31862164 ps
T825 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3793222673 May 30 01:14:37 PM PDT 24 May 30 01:14:45 PM PDT 24 346833100 ps
T162 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.992686016 May 30 01:14:53 PM PDT 24 May 30 01:15:36 PM PDT 24 620476259 ps
T826 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.355660319 May 30 01:15:29 PM PDT 24 May 30 01:15:32 PM PDT 24 10962540 ps
T827 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.548750207 May 30 01:14:55 PM PDT 24 May 30 01:15:40 PM PDT 24 5367784162 ps
T828 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3559280687 May 30 01:14:49 PM PDT 24 May 30 01:14:52 PM PDT 24 10165642 ps
T356 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1826780218 May 30 01:14:52 PM PDT 24 May 30 01:32:09 PM PDT 24 13649337173 ps
T829 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2994749149 May 30 01:15:27 PM PDT 24 May 30 01:15:35 PM PDT 24 77606760 ps
T830 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2995394950 May 30 01:14:39 PM PDT 24 May 30 01:18:28 PM PDT 24 3366782333 ps
T150 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1557176199 May 30 01:15:12 PM PDT 24 May 30 01:19:54 PM PDT 24 16169146795 ps

Test location /workspace/coverage/default/2.alert_handler_stress_all.1015599261
Short name T1
Test name
Test status
Simulation time 8430749608 ps
CPU time 891.36 seconds
Started May 30 01:19:31 PM PDT 24
Finished May 30 01:34:23 PM PDT 24
Peak memory 273392 kb
Host smart-7c0c9af8-9466-44bc-ba67-65b6916af829
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015599261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1015599261
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.2787155523
Short name T25
Test name
Test status
Simulation time 37743292163 ps
CPU time 2053.41 seconds
Started May 30 01:20:51 PM PDT 24
Finished May 30 01:55:06 PM PDT 24
Peak memory 281336 kb
Host smart-52933886-bfa8-4c6f-b52f-92dd86f3cdea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787155523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.2787155523
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.941297226
Short name T9
Test name
Test status
Simulation time 1999514543 ps
CPU time 24.57 seconds
Started May 30 01:19:32 PM PDT 24
Finished May 30 01:19:58 PM PDT 24
Peak memory 270104 kb
Host smart-7de52a4d-ea62-457c-aea8-daead515c6bc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=941297226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.941297226
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.2942883417
Short name T49
Test name
Test status
Simulation time 17008585048 ps
CPU time 172.52 seconds
Started May 30 01:22:23 PM PDT 24
Finished May 30 01:25:17 PM PDT 24
Peak memory 265112 kb
Host smart-3c7e7982-34fa-4e23-8747-ba319967bd6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942883417 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.2942883417
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2591943023
Short name T154
Test name
Test status
Simulation time 1312539586 ps
CPU time 37.52 seconds
Started May 30 01:15:28 PM PDT 24
Finished May 30 01:16:06 PM PDT 24
Peak memory 240508 kb
Host smart-ea3425cd-db37-40eb-acc6-5645e770b70e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2591943023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2591943023
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.3854266228
Short name T26
Test name
Test status
Simulation time 252024045814 ps
CPU time 3622.12 seconds
Started May 30 01:21:45 PM PDT 24
Finished May 30 02:22:08 PM PDT 24
Peak memory 289584 kb
Host smart-42930178-56f7-42c2-8748-c335bcece16d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854266228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.3854266228
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1633893145
Short name T88
Test name
Test status
Simulation time 44598741013 ps
CPU time 2651.24 seconds
Started May 30 01:21:32 PM PDT 24
Finished May 30 02:05:44 PM PDT 24
Peak memory 289652 kb
Host smart-8b3e6a10-20ff-4cd1-9531-5e3b200cb023
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633893145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1633893145
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.445296460
Short name T119
Test name
Test status
Simulation time 4389797313 ps
CPU time 685.1 seconds
Started May 30 01:15:30 PM PDT 24
Finished May 30 01:26:57 PM PDT 24
Peak memory 265436 kb
Host smart-4260b585-63f9-4a5b-98f5-02f64b84d75e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445296460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.445296460
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1105021341
Short name T63
Test name
Test status
Simulation time 144318502926 ps
CPU time 3106.94 seconds
Started May 30 01:20:31 PM PDT 24
Finished May 30 02:12:19 PM PDT 24
Peak memory 287892 kb
Host smart-93c567ee-3b4f-4c29-9825-fa4e50af5d36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105021341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1105021341
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.683488133
Short name T29
Test name
Test status
Simulation time 95610134378 ps
CPU time 2048.17 seconds
Started May 30 01:21:06 PM PDT 24
Finished May 30 01:55:15 PM PDT 24
Peak memory 297624 kb
Host smart-055d7fb1-2f75-479f-a1ee-2a52a920a689
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683488133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_han
dler_stress_all.683488133
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.4072264022
Short name T129
Test name
Test status
Simulation time 3903996203 ps
CPU time 307.77 seconds
Started May 30 01:14:36 PM PDT 24
Finished May 30 01:19:44 PM PDT 24
Peak memory 265456 kb
Host smart-c6be4aed-926a-400a-82d3-63d70636ae98
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4072264022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.4072264022
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3326895405
Short name T251
Test name
Test status
Simulation time 43963914771 ps
CPU time 2734.29 seconds
Started May 30 01:21:18 PM PDT 24
Finished May 30 02:06:53 PM PDT 24
Peak memory 289784 kb
Host smart-aef507e8-9faa-46f7-ba29-08c307eca892
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326895405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3326895405
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.2212350670
Short name T574
Test name
Test status
Simulation time 174925504003 ps
CPU time 1986.52 seconds
Started May 30 01:20:50 PM PDT 24
Finished May 30 01:53:57 PM PDT 24
Peak memory 281540 kb
Host smart-ae7535ac-ae76-4cff-b310-ec8cfb990971
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212350670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.2212350670
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.4142597861
Short name T127
Test name
Test status
Simulation time 4331672819 ps
CPU time 308.16 seconds
Started May 30 01:15:29 PM PDT 24
Finished May 30 01:20:39 PM PDT 24
Peak memory 264752 kb
Host smart-904a37e1-8c63-4fc6-81e2-f5d6f1e08f14
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4142597861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.4142597861
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2238417952
Short name T14
Test name
Test status
Simulation time 38489899754 ps
CPU time 2534.77 seconds
Started May 30 01:21:47 PM PDT 24
Finished May 30 02:04:02 PM PDT 24
Peak memory 289440 kb
Host smart-1ccfcb94-9a78-4d06-88dd-4c8f9c7c38fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238417952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2238417952
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.2717687805
Short name T102
Test name
Test status
Simulation time 53922999578 ps
CPU time 3165.45 seconds
Started May 30 01:19:55 PM PDT 24
Finished May 30 02:12:41 PM PDT 24
Peak memory 298148 kb
Host smart-7409a99d-6096-426c-98b1-eeee7119cc48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717687805 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.2717687805
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.120012428
Short name T126
Test name
Test status
Simulation time 20652683837 ps
CPU time 1169.12 seconds
Started May 30 01:14:50 PM PDT 24
Finished May 30 01:34:20 PM PDT 24
Peak memory 272736 kb
Host smart-a0df66dd-bc1d-424b-8991-11185b9dc490
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120012428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.120012428
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1825302324
Short name T36
Test name
Test status
Simulation time 231326865479 ps
CPU time 3393.37 seconds
Started May 30 01:20:16 PM PDT 24
Finished May 30 02:16:51 PM PDT 24
Peak memory 288564 kb
Host smart-9174629a-fbcb-4ba4-9440-e3090eee699c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825302324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1825302324
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.4091420254
Short name T83
Test name
Test status
Simulation time 9775098258 ps
CPU time 379.09 seconds
Started May 30 01:20:16 PM PDT 24
Finished May 30 01:26:37 PM PDT 24
Peak memory 248264 kb
Host smart-ac050b88-326a-4f58-bc9b-07739ed0e6ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091420254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.4091420254
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1172911091
Short name T142
Test name
Test status
Simulation time 8204172603 ps
CPU time 301.17 seconds
Started May 30 01:14:26 PM PDT 24
Finished May 30 01:19:28 PM PDT 24
Peak memory 265456 kb
Host smart-b45316d2-7ce9-4d0b-8e2c-d064ed46294b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1172911091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1172911091
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.4255551444
Short name T347
Test name
Test status
Simulation time 28175952 ps
CPU time 1.48 seconds
Started May 30 01:15:37 PM PDT 24
Finished May 30 01:15:39 PM PDT 24
Peak memory 236072 kb
Host smart-089a408d-64a3-4fcc-b956-ecfaeb108c82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4255551444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.4255551444
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.4161569033
Short name T231
Test name
Test status
Simulation time 1867614537 ps
CPU time 21.73 seconds
Started May 30 01:20:14 PM PDT 24
Finished May 30 01:20:37 PM PDT 24
Peak memory 240548 kb
Host smart-90a14985-9a3c-4c59-93a0-79931a86f5ca
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4161569033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.4161569033
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.2818156381
Short name T309
Test name
Test status
Simulation time 48084085280 ps
CPU time 2811.93 seconds
Started May 30 01:22:01 PM PDT 24
Finished May 30 02:08:54 PM PDT 24
Peak memory 289128 kb
Host smart-ced6361c-1b0c-42b5-a6ce-c61ba7c6f4c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818156381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2818156381
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3093947463
Short name T148
Test name
Test status
Simulation time 9032399606 ps
CPU time 709.09 seconds
Started May 30 01:15:14 PM PDT 24
Finished May 30 01:27:04 PM PDT 24
Peak memory 265428 kb
Host smart-912d2141-a39b-4790-8654-a39df113a78c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093947463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3093947463
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2316508436
Short name T7
Test name
Test status
Simulation time 12867064408 ps
CPU time 518.63 seconds
Started May 30 01:21:34 PM PDT 24
Finished May 30 01:30:13 PM PDT 24
Peak memory 247360 kb
Host smart-8bc640a6-5945-4cee-b1bf-8f8d1f31b6d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316508436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2316508436
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2981877794
Short name T133
Test name
Test status
Simulation time 13100074671 ps
CPU time 284.47 seconds
Started May 30 01:15:15 PM PDT 24
Finished May 30 01:20:00 PM PDT 24
Peak memory 265500 kb
Host smart-a9d4be12-8ee0-4c10-b72f-ab3eec867e46
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2981877794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.2981877794
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.994539456
Short name T298
Test name
Test status
Simulation time 12871600477 ps
CPU time 542.14 seconds
Started May 30 01:20:14 PM PDT 24
Finished May 30 01:29:18 PM PDT 24
Peak memory 247076 kb
Host smart-af976a17-e3d4-4c78-855b-fa4946eff9a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994539456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.994539456
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3669251010
Short name T21
Test name
Test status
Simulation time 3003607323 ps
CPU time 42.13 seconds
Started May 30 01:20:11 PM PDT 24
Finished May 30 01:20:54 PM PDT 24
Peak memory 248804 kb
Host smart-1c07bb67-8a10-4840-bd78-ec64d61dc570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36692
51010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3669251010
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2294053244
Short name T118
Test name
Test status
Simulation time 9269899582 ps
CPU time 284.62 seconds
Started May 30 01:15:29 PM PDT 24
Finished May 30 01:20:16 PM PDT 24
Peak memory 269824 kb
Host smart-0d9b0fd4-a6c7-4106-9782-803ba3ebf3e1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294053244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2294053244
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.1839329776
Short name T327
Test name
Test status
Simulation time 148449803048 ps
CPU time 2046.93 seconds
Started May 30 01:20:13 PM PDT 24
Finished May 30 01:54:22 PM PDT 24
Peak memory 269380 kb
Host smart-0a9214dd-4ece-48f7-851f-28563be5948c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839329776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1839329776
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1557176199
Short name T150
Test name
Test status
Simulation time 16169146795 ps
CPU time 281.18 seconds
Started May 30 01:15:12 PM PDT 24
Finished May 30 01:19:54 PM PDT 24
Peak memory 273260 kb
Host smart-173198c0-7f46-48b7-bb9d-7d5fa2d4c604
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1557176199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.1557176199
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.613502619
Short name T84
Test name
Test status
Simulation time 90095615066 ps
CPU time 2561.3 seconds
Started May 30 01:20:10 PM PDT 24
Finished May 30 02:02:52 PM PDT 24
Peak memory 286156 kb
Host smart-30d686b3-2cbd-4b64-8e2a-8e9b00ba156b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613502619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_han
dler_stress_all.613502619
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.1349271089
Short name T332
Test name
Test status
Simulation time 170499236311 ps
CPU time 1436.28 seconds
Started May 30 01:20:11 PM PDT 24
Finished May 30 01:44:08 PM PDT 24
Peak memory 272832 kb
Host smart-2df74de9-c902-474d-8804-2b52aa8357e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349271089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.1349271089
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.4229875370
Short name T303
Test name
Test status
Simulation time 52742627523 ps
CPU time 522.5 seconds
Started May 30 01:19:55 PM PDT 24
Finished May 30 01:28:38 PM PDT 24
Peak memory 248028 kb
Host smart-4374a65b-6393-4267-84bc-83d00950b298
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229875370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.4229875370
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.2319276095
Short name T243
Test name
Test status
Simulation time 50323578259 ps
CPU time 3302.79 seconds
Started May 30 01:19:37 PM PDT 24
Finished May 30 02:14:41 PM PDT 24
Peak memory 296964 kb
Host smart-624c7be7-f902-4347-929e-da32f013932c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319276095 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.2319276095
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.3157397565
Short name T236
Test name
Test status
Simulation time 20835963 ps
CPU time 1.3 seconds
Started May 30 01:15:33 PM PDT 24
Finished May 30 01:15:36 PM PDT 24
Peak memory 235004 kb
Host smart-e820bdc7-dc6d-4d21-a1ce-e58004e6e63f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3157397565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.3157397565
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.2761655499
Short name T686
Test name
Test status
Simulation time 10473328601 ps
CPU time 422.44 seconds
Started May 30 01:21:59 PM PDT 24
Finished May 30 01:29:02 PM PDT 24
Peak memory 247056 kb
Host smart-021d42a1-6ca2-4172-8710-4f2a1af68953
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761655499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.2761655499
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.2621592710
Short name T51
Test name
Test status
Simulation time 26070141753 ps
CPU time 1829.2 seconds
Started May 30 01:20:49 PM PDT 24
Finished May 30 01:51:19 PM PDT 24
Peak memory 289420 kb
Host smart-7e8e6da0-45cc-405a-97e4-d25cc262f7d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621592710 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.2621592710
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2501480766
Short name T149
Test name
Test status
Simulation time 25085763434 ps
CPU time 923.42 seconds
Started May 30 01:14:37 PM PDT 24
Finished May 30 01:30:01 PM PDT 24
Peak memory 272920 kb
Host smart-25b7e30e-474b-4e43-a8a1-d49d23b1e42b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501480766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.2501480766
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1974547223
Short name T125
Test name
Test status
Simulation time 61550896260 ps
CPU time 965.33 seconds
Started May 30 01:15:29 PM PDT 24
Finished May 30 01:31:36 PM PDT 24
Peak memory 265464 kb
Host smart-4a91faff-b95a-4bd6-9cad-6db3d3af891a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974547223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.1974547223
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.2543370022
Short name T595
Test name
Test status
Simulation time 44224320439 ps
CPU time 2471.07 seconds
Started May 30 01:21:20 PM PDT 24
Finished May 30 02:02:32 PM PDT 24
Peak memory 282600 kb
Host smart-9af65aa8-3773-44c5-b4aa-43e38684b662
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543370022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2543370022
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.1878520307
Short name T91
Test name
Test status
Simulation time 51204384387 ps
CPU time 2822.63 seconds
Started May 30 01:22:24 PM PDT 24
Finished May 30 02:09:27 PM PDT 24
Peak memory 289852 kb
Host smart-7effb1df-91d9-496f-ac5f-ed942db13dc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878520307 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.1878520307
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1598618343
Short name T97
Test name
Test status
Simulation time 116858551907 ps
CPU time 3588.95 seconds
Started May 30 01:22:38 PM PDT 24
Finished May 30 02:22:29 PM PDT 24
Peak memory 289212 kb
Host smart-c90ae4a1-92b3-4498-9ff1-0c24755ab1f4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598618343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1598618343
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2143878608
Short name T155
Test name
Test status
Simulation time 336141113 ps
CPU time 3.26 seconds
Started May 30 01:14:51 PM PDT 24
Finished May 30 01:14:55 PM PDT 24
Peak memory 236968 kb
Host smart-78ae6884-f517-4176-bb37-b2d6794362bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2143878608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2143878608
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.143388451
Short name T277
Test name
Test status
Simulation time 226798550728 ps
CPU time 5570.04 seconds
Started May 30 01:21:18 PM PDT 24
Finished May 30 02:54:10 PM PDT 24
Peak memory 354592 kb
Host smart-16642859-5ed3-4520-b1af-28d01df4a5fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143388451 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.143388451
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2735943236
Short name T16
Test name
Test status
Simulation time 23847897 ps
CPU time 2.6 seconds
Started May 30 01:20:15 PM PDT 24
Finished May 30 01:20:19 PM PDT 24
Peak memory 248952 kb
Host smart-9e4666fb-6d48-4c89-a1c9-0bbe06bbc567
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2735943236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2735943236
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2983262343
Short name T733
Test name
Test status
Simulation time 14474194 ps
CPU time 1.23 seconds
Started May 30 01:15:30 PM PDT 24
Finished May 30 01:15:33 PM PDT 24
Peak memory 235048 kb
Host smart-8ce17890-088b-49c3-a893-dd7fff687570
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2983262343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2983262343
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3825966730
Short name T278
Test name
Test status
Simulation time 22705607004 ps
CPU time 479.32 seconds
Started May 30 01:19:20 PM PDT 24
Finished May 30 01:27:21 PM PDT 24
Peak memory 247116 kb
Host smart-28c6e40e-6faa-48a4-8a08-c35c150fce77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825966730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3825966730
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.3065104348
Short name T112
Test name
Test status
Simulation time 28331038455 ps
CPU time 1725.75 seconds
Started May 30 01:21:05 PM PDT 24
Finished May 30 01:49:52 PM PDT 24
Peak memory 272648 kb
Host smart-e4209984-a455-4839-b6c3-6daafc557150
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065104348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3065104348
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.3236706684
Short name T335
Test name
Test status
Simulation time 48290725252 ps
CPU time 2544.82 seconds
Started May 30 01:22:01 PM PDT 24
Finished May 30 02:04:27 PM PDT 24
Peak memory 285180 kb
Host smart-3a8359dd-ebd5-4378-a67c-a51b67afe2e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236706684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.3236706684
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.2899514672
Short name T184
Test name
Test status
Simulation time 151799418 ps
CPU time 3.52 seconds
Started May 30 01:19:32 PM PDT 24
Finished May 30 01:19:37 PM PDT 24
Peak memory 248912 kb
Host smart-3c6c1ddd-b9db-4d05-8966-610c153e8ba6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2899514672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2899514672
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.2283105803
Short name T59
Test name
Test status
Simulation time 20047666254 ps
CPU time 1191.62 seconds
Started May 30 01:20:36 PM PDT 24
Finished May 30 01:40:28 PM PDT 24
Peak memory 265400 kb
Host smart-8def3c6c-7038-414d-bfd4-6d1de84a482b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283105803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2283105803
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2498221505
Short name T353
Test name
Test status
Simulation time 37974300 ps
CPU time 5.65 seconds
Started May 30 01:14:36 PM PDT 24
Finished May 30 01:14:43 PM PDT 24
Peak memory 244400 kb
Host smart-ef093883-2594-4798-8079-4d31e5ba45eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498221505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.2498221505
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1847527406
Short name T171
Test name
Test status
Simulation time 1023771704 ps
CPU time 70.07 seconds
Started May 30 01:15:28 PM PDT 24
Finished May 30 01:16:40 PM PDT 24
Peak memory 237216 kb
Host smart-b6bf5e48-bf65-430e-be8d-3e89fb3ddf75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1847527406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1847527406
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2625362291
Short name T216
Test name
Test status
Simulation time 32191169 ps
CPU time 3.67 seconds
Started May 30 01:19:27 PM PDT 24
Finished May 30 01:19:31 PM PDT 24
Peak memory 248512 kb
Host smart-3cf0ee26-c80a-433d-9cb0-20c63b3a0d8f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2625362291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2625362291
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3901698897
Short name T213
Test name
Test status
Simulation time 51720936 ps
CPU time 2.6 seconds
Started May 30 01:20:11 PM PDT 24
Finished May 30 01:20:14 PM PDT 24
Peak memory 248916 kb
Host smart-687c5a9a-d5b4-460e-ab05-6f679c743c98
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3901698897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3901698897
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1200748678
Short name T322
Test name
Test status
Simulation time 37828593647 ps
CPU time 353.27 seconds
Started May 30 01:20:13 PM PDT 24
Finished May 30 01:26:08 PM PDT 24
Peak memory 248000 kb
Host smart-6933bf11-acaa-492d-9899-189586dacf66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200748678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1200748678
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.746698225
Short name T79
Test name
Test status
Simulation time 105053158655 ps
CPU time 1309.97 seconds
Started May 30 01:20:11 PM PDT 24
Finished May 30 01:42:02 PM PDT 24
Peak memory 282876 kb
Host smart-b45439a2-19fd-48d7-916f-277ca15f12d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746698225 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.746698225
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1194292480
Short name T240
Test name
Test status
Simulation time 52721674787 ps
CPU time 3277.45 seconds
Started May 30 01:20:17 PM PDT 24
Finished May 30 02:14:56 PM PDT 24
Peak memory 289276 kb
Host smart-b116cead-b3b3-48fb-9ef6-92e63593925e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194292480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1194292480
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.3294617492
Short name T342
Test name
Test status
Simulation time 107723192613 ps
CPU time 1756.43 seconds
Started May 30 01:20:39 PM PDT 24
Finished May 30 01:49:57 PM PDT 24
Peak memory 271420 kb
Host smart-b02c3058-22fd-42a4-a93f-4a8b5f4cd8f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294617492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3294617492
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.1428810581
Short name T244
Test name
Test status
Simulation time 25252930383 ps
CPU time 1198.42 seconds
Started May 30 01:20:38 PM PDT 24
Finished May 30 01:40:38 PM PDT 24
Peak memory 273488 kb
Host smart-b5674451-3fbc-4738-aaa8-e6343d3aff32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428810581 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.1428810581
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.2056188511
Short name T677
Test name
Test status
Simulation time 11451554651 ps
CPU time 216.56 seconds
Started May 30 01:22:00 PM PDT 24
Finished May 30 01:25:38 PM PDT 24
Peak memory 254652 kb
Host smart-8694e860-01fe-450f-b1b1-e32c54309501
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056188511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.2056188511
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.781697731
Short name T117
Test name
Test status
Simulation time 2143272823 ps
CPU time 343.05 seconds
Started May 30 01:15:19 PM PDT 24
Finished May 30 01:21:03 PM PDT 24
Peak memory 265376 kb
Host smart-6a775496-f30c-4641-98da-2360b8b4e4f3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781697731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.781697731
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.34852254
Short name T357
Test name
Test status
Simulation time 30885065684 ps
CPU time 337.66 seconds
Started May 30 01:14:43 PM PDT 24
Finished May 30 01:20:21 PM PDT 24
Peak memory 269892 kb
Host smart-6f90a588-230c-4b78-b1b4-26eaef840476
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34852254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.34852254
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.3246162894
Short name T24
Test name
Test status
Simulation time 114735909320 ps
CPU time 3920.18 seconds
Started May 30 01:20:59 PM PDT 24
Finished May 30 02:26:20 PM PDT 24
Peak memory 321944 kb
Host smart-2dbb3353-d8b4-40dc-889f-79698689c365
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246162894 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.3246162894
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.3112736522
Short name T261
Test name
Test status
Simulation time 59021514686 ps
CPU time 1422.28 seconds
Started May 30 01:19:27 PM PDT 24
Finished May 30 01:43:10 PM PDT 24
Peak memory 286296 kb
Host smart-480a52a1-05b6-4ef0-a38f-ff00f1b1436a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112736522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.3112736522
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1200147502
Short name T185
Test name
Test status
Simulation time 16833272833 ps
CPU time 1180.19 seconds
Started May 30 01:19:32 PM PDT 24
Finished May 30 01:39:13 PM PDT 24
Peak memory 273420 kb
Host smart-91299fab-8b4c-4528-be42-9acf3a88ad3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200147502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1200147502
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.460675761
Short name T306
Test name
Test status
Simulation time 7912122426 ps
CPU time 312.19 seconds
Started May 30 01:19:37 PM PDT 24
Finished May 30 01:24:50 PM PDT 24
Peak memory 247164 kb
Host smart-2dc4776c-4a4d-481e-9ca5-adac2cf04a86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460675761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.460675761
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.1774682518
Short name T272
Test name
Test status
Simulation time 32437607271 ps
CPU time 2167.57 seconds
Started May 30 01:19:37 PM PDT 24
Finished May 30 01:55:46 PM PDT 24
Peak memory 289460 kb
Host smart-3c9a7946-3c35-44d8-9aaa-6e058d385009
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774682518 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.1774682518
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.1280990510
Short name T290
Test name
Test status
Simulation time 137808364461 ps
CPU time 2361.71 seconds
Started May 30 01:20:10 PM PDT 24
Finished May 30 01:59:32 PM PDT 24
Peak memory 321780 kb
Host smart-2159f9e1-1408-4630-aecf-6dfb2400c717
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280990510 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.1280990510
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.968533288
Short name T285
Test name
Test status
Simulation time 271895148 ps
CPU time 29.07 seconds
Started May 30 01:20:16 PM PDT 24
Finished May 30 01:20:47 PM PDT 24
Peak memory 248764 kb
Host smart-2bbd33f8-ea8c-44be-98aa-fd424ef5d29d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96853
3288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.968533288
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.3071536366
Short name T52
Test name
Test status
Simulation time 156621056682 ps
CPU time 2339.42 seconds
Started May 30 01:20:26 PM PDT 24
Finished May 30 01:59:27 PM PDT 24
Peak memory 286560 kb
Host smart-d0029355-f24b-4d59-a97c-56a6e36636cc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071536366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.3071536366
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.1445438801
Short name T248
Test name
Test status
Simulation time 269136113169 ps
CPU time 3185.81 seconds
Started May 30 01:20:15 PM PDT 24
Finished May 30 02:13:23 PM PDT 24
Peak memory 305912 kb
Host smart-f88b8e49-0ef0-480a-af95-db9a9eaaf5c2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445438801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.1445438801
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2221391288
Short name T15
Test name
Test status
Simulation time 20960018301 ps
CPU time 1218.85 seconds
Started May 30 01:20:24 PM PDT 24
Finished May 30 01:40:44 PM PDT 24
Peak memory 282932 kb
Host smart-cab6afa3-f2d4-4f61-a77a-616929a467e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221391288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2221391288
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.2317299725
Short name T288
Test name
Test status
Simulation time 16547010994 ps
CPU time 659.35 seconds
Started May 30 01:20:33 PM PDT 24
Finished May 30 01:31:34 PM PDT 24
Peak memory 273172 kb
Host smart-0e87ec74-6d6e-4dfb-bc8d-14f0c2b86ebe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317299725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2317299725
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2064489724
Short name T32
Test name
Test status
Simulation time 81429633226 ps
CPU time 3637.35 seconds
Started May 30 01:21:44 PM PDT 24
Finished May 30 02:22:23 PM PDT 24
Peak memory 289764 kb
Host smart-d4dcc4c2-950a-408b-a7c5-57c8c8e8a964
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064489724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2064489724
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3534058527
Short name T325
Test name
Test status
Simulation time 165920395327 ps
CPU time 2611.36 seconds
Started May 30 01:22:36 PM PDT 24
Finished May 30 02:06:08 PM PDT 24
Peak memory 289008 kb
Host smart-08fadcd7-372f-48c6-832a-227ee0482645
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534058527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3534058527
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1099877570
Short name T104
Test name
Test status
Simulation time 79217294 ps
CPU time 9.27 seconds
Started May 30 01:21:20 PM PDT 24
Finished May 30 01:21:31 PM PDT 24
Peak memory 247436 kb
Host smart-682c673e-a24a-4080-9e7e-70fe4f1722c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10998
77570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1099877570
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1448654293
Short name T176
Test name
Test status
Simulation time 4739947010 ps
CPU time 83.46 seconds
Started May 30 01:15:29 PM PDT 24
Finished May 30 01:16:54 PM PDT 24
Peak memory 239716 kb
Host smart-03863020-e442-46b3-8c38-03dfe40f07be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1448654293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1448654293
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.11786956
Short name T145
Test name
Test status
Simulation time 11497043076 ps
CPU time 365.56 seconds
Started May 30 01:15:31 PM PDT 24
Finished May 30 01:21:37 PM PDT 24
Peak memory 265600 kb
Host smart-d14d0dd9-2768-464f-81cf-97330686fab2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=11786956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_error
s.11786956
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3610911457
Short name T164
Test name
Test status
Simulation time 3162533336 ps
CPU time 63.1 seconds
Started May 30 01:15:29 PM PDT 24
Finished May 30 01:16:33 PM PDT 24
Peak memory 245768 kb
Host smart-c7b30e43-b025-4b45-a121-e638c1311159
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3610911457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3610911457
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3470669650
Short name T165
Test name
Test status
Simulation time 85370049 ps
CPU time 5.62 seconds
Started May 30 01:14:38 PM PDT 24
Finished May 30 01:14:45 PM PDT 24
Peak memory 236980 kb
Host smart-0388bcdf-bcd6-43d4-a60d-74f2447f5309
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3470669650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3470669650
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2510606767
Short name T159
Test name
Test status
Simulation time 926979176 ps
CPU time 68.81 seconds
Started May 30 01:15:14 PM PDT 24
Finished May 30 01:16:23 PM PDT 24
Peak memory 240480 kb
Host smart-46742b22-871e-4e54-a2fd-f0e827c09c4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2510606767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.2510606767
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2133663725
Short name T170
Test name
Test status
Simulation time 35876469 ps
CPU time 3.55 seconds
Started May 30 01:15:29 PM PDT 24
Finished May 30 01:15:34 PM PDT 24
Peak memory 236920 kb
Host smart-b26e4b87-3bf1-4dc9-b3c5-db95aa56ccbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2133663725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2133663725
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1527516818
Short name T168
Test name
Test status
Simulation time 96841851 ps
CPU time 3.72 seconds
Started May 30 01:14:39 PM PDT 24
Finished May 30 01:14:44 PM PDT 24
Peak memory 236052 kb
Host smart-4ace48b1-3973-4887-b5ba-4d4d9996a494
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1527516818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1527516818
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3304708090
Short name T135
Test name
Test status
Simulation time 1625723494 ps
CPU time 194.22 seconds
Started May 30 01:15:12 PM PDT 24
Finished May 30 01:18:27 PM PDT 24
Peak memory 265344 kb
Host smart-77c201db-8f40-43b2-8521-cff9461ec420
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3304708090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3304708090
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1829512066
Short name T169
Test name
Test status
Simulation time 887318465 ps
CPU time 69.7 seconds
Started May 30 01:15:15 PM PDT 24
Finished May 30 01:16:26 PM PDT 24
Peak memory 237048 kb
Host smart-17e3ca4d-fbc1-4bd8-8ef3-9b017af327cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1829512066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1829512066
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3818233377
Short name T153
Test name
Test status
Simulation time 54758783 ps
CPU time 4.52 seconds
Started May 30 01:15:29 PM PDT 24
Finished May 30 01:15:35 PM PDT 24
Peak memory 236956 kb
Host smart-fdcb642b-bfb5-4f55-8604-4f44aa347fa7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3818233377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3818233377
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.15397316
Short name T144
Test name
Test status
Simulation time 7136218927 ps
CPU time 289.31 seconds
Started May 30 01:15:30 PM PDT 24
Finished May 30 01:20:20 PM PDT 24
Peak memory 265416 kb
Host smart-eaa23306-340c-40dc-98ec-93d98923ce9f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=15397316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_error
s.15397316
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.658949014
Short name T167
Test name
Test status
Simulation time 330816516 ps
CPU time 42.53 seconds
Started May 30 01:14:38 PM PDT 24
Finished May 30 01:15:22 PM PDT 24
Peak memory 248668 kb
Host smart-25bf9e20-a994-40c0-8c13-664d5eb5c337
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=658949014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.658949014
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1629421570
Short name T166
Test name
Test status
Simulation time 458461358 ps
CPU time 48 seconds
Started May 30 01:14:50 PM PDT 24
Finished May 30 01:15:39 PM PDT 24
Peak memory 240500 kb
Host smart-bfec166c-c5d0-4aa8-b8ce-3ed53245884a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1629421570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.1629421570
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.921653967
Short name T161
Test name
Test status
Simulation time 36284275 ps
CPU time 3.27 seconds
Started May 30 01:14:29 PM PDT 24
Finished May 30 01:14:33 PM PDT 24
Peak memory 236964 kb
Host smart-0e0d15b8-20f3-46ec-b3e3-f388dfdd0194
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=921653967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.921653967
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3454110499
Short name T179
Test name
Test status
Simulation time 7017128376 ps
CPU time 85.19 seconds
Started May 30 01:15:14 PM PDT 24
Finished May 30 01:16:40 PM PDT 24
Peak memory 248732 kb
Host smart-831dd7e1-7874-48d3-aed7-b2e882e53c2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3454110499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3454110499
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.344472437
Short name T160
Test name
Test status
Simulation time 92986990 ps
CPU time 3.49 seconds
Started May 30 01:14:37 PM PDT 24
Finished May 30 01:14:42 PM PDT 24
Peak memory 236004 kb
Host smart-97c481c3-b5b3-451e-bbb2-85810924a95d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=344472437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.344472437
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.992686016
Short name T162
Test name
Test status
Simulation time 620476259 ps
CPU time 42.49 seconds
Started May 30 01:14:53 PM PDT 24
Finished May 30 01:15:36 PM PDT 24
Peak memory 237076 kb
Host smart-3d6d3d6a-2130-4d79-8a34-fd4fbb8c9d2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=992686016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.992686016
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.432711843
Short name T172
Test name
Test status
Simulation time 3747573660 ps
CPU time 64.94 seconds
Started May 30 01:14:50 PM PDT 24
Finished May 30 01:15:55 PM PDT 24
Peak memory 248784 kb
Host smart-a6e553f4-543a-4582-9135-93cb044aaf5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=432711843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.432711843
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3180807494
Short name T22
Test name
Test status
Simulation time 180568100570 ps
CPU time 2228.43 seconds
Started May 30 01:20:13 PM PDT 24
Finished May 30 01:57:23 PM PDT 24
Peak memory 281584 kb
Host smart-9d0b5d6b-2e71-4034-8e9f-ccdd1860a970
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180807494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3180807494
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.4103008824
Short name T23
Test name
Test status
Simulation time 120315997 ps
CPU time 10.68 seconds
Started May 30 01:19:32 PM PDT 24
Finished May 30 01:19:44 PM PDT 24
Peak memory 248712 kb
Host smart-307d0d4a-d24b-4ec7-8e20-5a01e2881146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41030
08824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.4103008824
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.875128432
Short name T761
Test name
Test status
Simulation time 1125121413 ps
CPU time 145.09 seconds
Started May 30 01:14:27 PM PDT 24
Finished May 30 01:16:53 PM PDT 24
Peak memory 240040 kb
Host smart-7fc97706-c538-4058-802c-9fb9c5a40975
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=875128432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.875128432
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1926618640
Short name T173
Test name
Test status
Simulation time 25167482236 ps
CPU time 268.82 seconds
Started May 30 01:14:28 PM PDT 24
Finished May 30 01:18:58 PM PDT 24
Peak memory 236820 kb
Host smart-a625c283-981a-4e26-9b29-d8904ccd5bd3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1926618640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1926618640
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1530556535
Short name T766
Test name
Test status
Simulation time 40349152 ps
CPU time 6.43 seconds
Started May 30 01:14:29 PM PDT 24
Finished May 30 01:14:36 PM PDT 24
Peak memory 240292 kb
Host smart-7c8b2b57-d7eb-429d-ba66-88aa8cdefb89
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1530556535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1530556535
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3461574415
Short name T824
Test name
Test status
Simulation time 31862164 ps
CPU time 5.45 seconds
Started May 30 01:14:28 PM PDT 24
Finished May 30 01:14:34 PM PDT 24
Peak memory 256860 kb
Host smart-d3a0e346-a97f-4eba-8908-0d30c784f6e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461574415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.3461574415
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1645900145
Short name T787
Test name
Test status
Simulation time 305898974 ps
CPU time 3.44 seconds
Started May 30 01:14:29 PM PDT 24
Finished May 30 01:14:33 PM PDT 24
Peak memory 239584 kb
Host smart-73503020-3503-4d9b-ac3d-a169ccd91d11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1645900145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.1645900145
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1230363180
Short name T158
Test name
Test status
Simulation time 6455225 ps
CPU time 1.45 seconds
Started May 30 01:14:32 PM PDT 24
Finished May 30 01:14:35 PM PDT 24
Peak memory 235032 kb
Host smart-d05805fb-b1de-4b36-8f73-68772b662753
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1230363180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.1230363180
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1581425286
Short name T800
Test name
Test status
Simulation time 8939451655 ps
CPU time 42.82 seconds
Started May 30 01:14:29 PM PDT 24
Finished May 30 01:15:13 PM PDT 24
Peak memory 248764 kb
Host smart-a4e0a390-165b-41e6-b9b6-8ac34638aea0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1581425286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1581425286
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3917612070
Short name T130
Test name
Test status
Simulation time 6554656885 ps
CPU time 500.88 seconds
Started May 30 01:14:29 PM PDT 24
Finished May 30 01:22:51 PM PDT 24
Peak memory 265500 kb
Host smart-ad7ccc13-f674-45c8-b0c0-cfbed9ccdbd0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917612070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.3917612070
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3277198839
Short name T712
Test name
Test status
Simulation time 70734442 ps
CPU time 4.8 seconds
Started May 30 01:14:29 PM PDT 24
Finished May 30 01:14:35 PM PDT 24
Peak memory 248604 kb
Host smart-259dbae1-16ec-467f-8090-2d94fc4a7808
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3277198839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3277198839
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2047586583
Short name T788
Test name
Test status
Simulation time 4951621075 ps
CPU time 166.52 seconds
Started May 30 01:14:36 PM PDT 24
Finished May 30 01:17:23 PM PDT 24
Peak memory 240528 kb
Host smart-40073390-1710-407f-82fe-fc72e83008f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2047586583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2047586583
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.38020752
Short name T798
Test name
Test status
Simulation time 18451195567 ps
CPU time 394.17 seconds
Started May 30 01:14:37 PM PDT 24
Finished May 30 01:21:12 PM PDT 24
Peak memory 236016 kb
Host smart-8c9fd6e1-05b7-4220-9cb7-88cba189ecf8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=38020752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.38020752
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1225736167
Short name T743
Test name
Test status
Simulation time 145175835 ps
CPU time 6.46 seconds
Started May 30 01:14:36 PM PDT 24
Finished May 30 01:14:44 PM PDT 24
Peak memory 240440 kb
Host smart-6aff81e8-b432-4654-a21b-e1440cded604
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1225736167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1225736167
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3529934786
Short name T804
Test name
Test status
Simulation time 65011923 ps
CPU time 4.69 seconds
Started May 30 01:14:38 PM PDT 24
Finished May 30 01:14:44 PM PDT 24
Peak memory 235940 kb
Host smart-ce5bc50a-0314-4d62-875a-c1184b8f6b0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3529934786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3529934786
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.4055465198
Short name T734
Test name
Test status
Simulation time 6226140 ps
CPU time 1.34 seconds
Started May 30 01:14:37 PM PDT 24
Finished May 30 01:14:39 PM PDT 24
Peak memory 235056 kb
Host smart-ac8d6d34-13bc-4a89-9b5c-2142e6fee37e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4055465198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.4055465198
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1685005955
Short name T747
Test name
Test status
Simulation time 673671591 ps
CPU time 42.36 seconds
Started May 30 01:14:43 PM PDT 24
Finished May 30 01:15:26 PM PDT 24
Peak memory 245168 kb
Host smart-b7276443-ad20-4056-ae02-1ce528fbb32f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1685005955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1685005955
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.4046154291
Short name T147
Test name
Test status
Simulation time 1566763329 ps
CPU time 91.18 seconds
Started May 30 01:14:37 PM PDT 24
Finished May 30 01:16:10 PM PDT 24
Peak memory 257228 kb
Host smart-48655130-c65b-4bc8-9f42-b33f583d112c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4046154291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.4046154291
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1734674373
Short name T718
Test name
Test status
Simulation time 327827166 ps
CPU time 20.63 seconds
Started May 30 01:14:37 PM PDT 24
Finished May 30 01:14:59 PM PDT 24
Peak memory 252876 kb
Host smart-db5a4f99-3e8a-4a4d-b984-4450ccdcf342
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1734674373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1734674373
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2078563501
Short name T725
Test name
Test status
Simulation time 139199632 ps
CPU time 5.34 seconds
Started May 30 01:15:14 PM PDT 24
Finished May 30 01:15:21 PM PDT 24
Peak memory 256948 kb
Host smart-d2d0ac18-44ad-4d6b-87f0-d74e0f04d897
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078563501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2078563501
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.209930880
Short name T783
Test name
Test status
Simulation time 33450532 ps
CPU time 4.76 seconds
Started May 30 01:15:15 PM PDT 24
Finished May 30 01:15:21 PM PDT 24
Peak memory 235948 kb
Host smart-953c2265-8181-4552-ac44-778f1e5be8a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=209930880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.209930880
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.724185940
Short name T789
Test name
Test status
Simulation time 21884466 ps
CPU time 1.44 seconds
Started May 30 01:15:13 PM PDT 24
Finished May 30 01:15:15 PM PDT 24
Peak memory 235980 kb
Host smart-2c7cd2e7-fcb3-491a-8501-9e6f6b77b02f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=724185940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.724185940
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.506236728
Short name T778
Test name
Test status
Simulation time 509896694 ps
CPU time 40.33 seconds
Started May 30 01:15:13 PM PDT 24
Finished May 30 01:15:54 PM PDT 24
Peak memory 245176 kb
Host smart-da9b1ba1-7a9e-4859-b52a-101bc910ace3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=506236728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_out
standing.506236728
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1144756331
Short name T819
Test name
Test status
Simulation time 66406711 ps
CPU time 8.5 seconds
Started May 30 01:15:15 PM PDT 24
Finished May 30 01:15:25 PM PDT 24
Peak memory 248276 kb
Host smart-3d05a1a1-7521-4731-8de1-f6901c59ea72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1144756331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1144756331
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1070912954
Short name T741
Test name
Test status
Simulation time 683224962 ps
CPU time 8.89 seconds
Started May 30 01:15:13 PM PDT 24
Finished May 30 01:15:23 PM PDT 24
Peak memory 238064 kb
Host smart-4c238ab1-eae8-4ba0-8f2a-201ae8d87a4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070912954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1070912954
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3183074962
Short name T748
Test name
Test status
Simulation time 209371898 ps
CPU time 4.45 seconds
Started May 30 01:15:14 PM PDT 24
Finished May 30 01:15:20 PM PDT 24
Peak memory 236836 kb
Host smart-3a45d945-431f-471f-9514-563f10b926d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3183074962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.3183074962
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1802132621
Short name T757
Test name
Test status
Simulation time 8503784 ps
CPU time 1.67 seconds
Started May 30 01:15:14 PM PDT 24
Finished May 30 01:15:16 PM PDT 24
Peak memory 237008 kb
Host smart-9fb77183-2c6e-4217-a9d0-4edcbc0e2f3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1802132621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1802132621
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2337304984
Short name T821
Test name
Test status
Simulation time 354078095 ps
CPU time 24.34 seconds
Started May 30 01:15:13 PM PDT 24
Finished May 30 01:15:39 PM PDT 24
Peak memory 245096 kb
Host smart-c0aaeec5-68a6-490f-82ac-fe52f79fe64b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2337304984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.2337304984
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2658854192
Short name T730
Test name
Test status
Simulation time 587501867 ps
CPU time 22.46 seconds
Started May 30 01:15:14 PM PDT 24
Finished May 30 01:15:37 PM PDT 24
Peak memory 248932 kb
Host smart-a03fabe7-6c95-44dd-b3eb-6af153ada804
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2658854192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2658854192
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2093137071
Short name T807
Test name
Test status
Simulation time 61619347 ps
CPU time 5.35 seconds
Started May 30 01:15:29 PM PDT 24
Finished May 30 01:15:36 PM PDT 24
Peak memory 241148 kb
Host smart-1cfe76a4-6222-459f-976c-9707f7aeccd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093137071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.2093137071
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2930475995
Short name T204
Test name
Test status
Simulation time 162316585 ps
CPU time 5 seconds
Started May 30 01:15:15 PM PDT 24
Finished May 30 01:15:21 PM PDT 24
Peak memory 235840 kb
Host smart-6390b012-553f-4581-afb6-532690b705fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2930475995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2930475995
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3083408958
Short name T799
Test name
Test status
Simulation time 9073672 ps
CPU time 1.37 seconds
Started May 30 01:15:14 PM PDT 24
Finished May 30 01:15:16 PM PDT 24
Peak memory 236948 kb
Host smart-7a5379e9-43e0-49b7-a277-94c9fd8cfe40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3083408958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3083408958
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.4290995224
Short name T175
Test name
Test status
Simulation time 1329876299 ps
CPU time 41.96 seconds
Started May 30 01:15:27 PM PDT 24
Finished May 30 01:16:10 PM PDT 24
Peak memory 248656 kb
Host smart-ab900b73-9aeb-4d76-9a47-eee7db030088
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4290995224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.4290995224
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2157178795
Short name T134
Test name
Test status
Simulation time 2165666431 ps
CPU time 305.97 seconds
Started May 30 01:15:14 PM PDT 24
Finished May 30 01:20:21 PM PDT 24
Peak memory 265400 kb
Host smart-7fe77d70-efab-4c4f-a895-34a4c93e0c8c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157178795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2157178795
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1752924052
Short name T722
Test name
Test status
Simulation time 4020046971 ps
CPU time 25.22 seconds
Started May 30 01:15:15 PM PDT 24
Finished May 30 01:15:41 PM PDT 24
Peak memory 248852 kb
Host smart-d4a87175-d45d-4dc0-ba31-742f47715516
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1752924052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1752924052
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.4189374023
Short name T751
Test name
Test status
Simulation time 504539811 ps
CPU time 11.73 seconds
Started May 30 01:15:29 PM PDT 24
Finished May 30 01:15:42 PM PDT 24
Peak memory 254380 kb
Host smart-c412491f-0a3d-4eee-8853-83a11f5a4cd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189374023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.4189374023
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3234310805
Short name T354
Test name
Test status
Simulation time 181961276 ps
CPU time 4.23 seconds
Started May 30 01:15:27 PM PDT 24
Finished May 30 01:15:32 PM PDT 24
Peak memory 235964 kb
Host smart-d80311a1-ec8d-4159-a6a0-5908ca3dc735
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3234310805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3234310805
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3404462581
Short name T736
Test name
Test status
Simulation time 14651920 ps
CPU time 1.77 seconds
Started May 30 01:15:29 PM PDT 24
Finished May 30 01:15:33 PM PDT 24
Peak memory 236012 kb
Host smart-5a847a68-fcee-49dd-8d80-0a2f33d45036
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3404462581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3404462581
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2338242597
Short name T782
Test name
Test status
Simulation time 542282762 ps
CPU time 21.51 seconds
Started May 30 01:15:26 PM PDT 24
Finished May 30 01:15:48 PM PDT 24
Peak memory 240508 kb
Host smart-a37d3bd2-18ee-4f1e-961e-c627d380cf76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2338242597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2338242597
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.442417906
Short name T124
Test name
Test status
Simulation time 4572880518 ps
CPU time 561.49 seconds
Started May 30 01:15:29 PM PDT 24
Finished May 30 01:24:52 PM PDT 24
Peak memory 265476 kb
Host smart-01d1bf11-b32f-4795-b714-affdc2ad5faf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442417906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.442417906
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1996937063
Short name T791
Test name
Test status
Simulation time 857354519 ps
CPU time 7.93 seconds
Started May 30 01:15:29 PM PDT 24
Finished May 30 01:15:38 PM PDT 24
Peak memory 248796 kb
Host smart-38d844d7-e6b4-4b1b-8fc5-78a68600923b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1996937063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1996937063
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3172506415
Short name T768
Test name
Test status
Simulation time 610327130 ps
CPU time 13.4 seconds
Started May 30 01:15:29 PM PDT 24
Finished May 30 01:15:44 PM PDT 24
Peak memory 255016 kb
Host smart-ecffef8c-fc5a-4d77-8b36-5ea296d7c7de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172506415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3172506415
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3037814390
Short name T818
Test name
Test status
Simulation time 20867601 ps
CPU time 3.51 seconds
Started May 30 01:15:27 PM PDT 24
Finished May 30 01:15:31 PM PDT 24
Peak memory 239564 kb
Host smart-9bde0dde-e76b-4b29-b2a8-5634737594cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3037814390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3037814390
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.4170153848
Short name T780
Test name
Test status
Simulation time 14523561 ps
CPU time 1.29 seconds
Started May 30 01:15:29 PM PDT 24
Finished May 30 01:15:31 PM PDT 24
Peak memory 234952 kb
Host smart-8e2f5829-fa48-4843-a834-5830c62ad666
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4170153848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.4170153848
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2035356900
Short name T749
Test name
Test status
Simulation time 350433458 ps
CPU time 12.35 seconds
Started May 30 01:15:27 PM PDT 24
Finished May 30 01:15:40 PM PDT 24
Peak memory 245168 kb
Host smart-f09bb9b9-5d2f-48a7-9b40-8fad5aa9c14b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2035356900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.2035356900
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.496492863
Short name T123
Test name
Test status
Simulation time 1610293615 ps
CPU time 117.85 seconds
Started May 30 01:15:29 PM PDT 24
Finished May 30 01:17:28 PM PDT 24
Peak memory 257300 kb
Host smart-ec415135-95fd-4660-b4f5-cec35d2dadab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=496492863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_erro
rs.496492863
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1128062003
Short name T762
Test name
Test status
Simulation time 184280211 ps
CPU time 11.93 seconds
Started May 30 01:15:31 PM PDT 24
Finished May 30 01:15:44 PM PDT 24
Peak memory 251956 kb
Host smart-067f85e9-c21b-475c-b355-71b020b94cb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1128062003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1128062003
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2994749149
Short name T829
Test name
Test status
Simulation time 77606760 ps
CPU time 7.1 seconds
Started May 30 01:15:27 PM PDT 24
Finished May 30 01:15:35 PM PDT 24
Peak memory 239396 kb
Host smart-8f73943e-e66b-4b7b-9866-3fa3b6737429
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994749149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2994749149
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.783748473
Short name T753
Test name
Test status
Simulation time 50297672 ps
CPU time 5.84 seconds
Started May 30 01:15:30 PM PDT 24
Finished May 30 01:15:37 PM PDT 24
Peak memory 240420 kb
Host smart-1e47fa38-d26d-40b5-b940-ef3dd87438b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=783748473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.783748473
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3345138455
Short name T726
Test name
Test status
Simulation time 730518974 ps
CPU time 41.58 seconds
Started May 30 01:15:31 PM PDT 24
Finished May 30 01:16:14 PM PDT 24
Peak memory 245172 kb
Host smart-bfe266ab-c8bc-44ba-9086-47f1f3e98698
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3345138455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.3345138455
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1031452317
Short name T141
Test name
Test status
Simulation time 3918136731 ps
CPU time 304.1 seconds
Started May 30 01:15:29 PM PDT 24
Finished May 30 01:20:35 PM PDT 24
Peak memory 265348 kb
Host smart-5a889ae4-992f-4498-b24e-c7aeaccff106
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1031452317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1031452317
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.793143607
Short name T140
Test name
Test status
Simulation time 7802250999 ps
CPU time 568.44 seconds
Started May 30 01:15:27 PM PDT 24
Finished May 30 01:24:57 PM PDT 24
Peak memory 265408 kb
Host smart-72a3c0ed-affe-4966-9f48-3fb97b6cb3e0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793143607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.793143607
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.98354194
Short name T784
Test name
Test status
Simulation time 150118797 ps
CPU time 17.91 seconds
Started May 30 01:15:34 PM PDT 24
Finished May 30 01:15:52 PM PDT 24
Peak memory 248752 kb
Host smart-74eba376-3c44-4dfc-996b-ffe07d629ee1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=98354194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.98354194
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3716944638
Short name T737
Test name
Test status
Simulation time 145921305 ps
CPU time 5.02 seconds
Started May 30 01:15:29 PM PDT 24
Finished May 30 01:15:36 PM PDT 24
Peak memory 240568 kb
Host smart-87bf205a-332b-4220-83de-a1366549a56f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716944638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.3716944638
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.414692560
Short name T738
Test name
Test status
Simulation time 20097230 ps
CPU time 3.52 seconds
Started May 30 01:15:28 PM PDT 24
Finished May 30 01:15:32 PM PDT 24
Peak memory 236852 kb
Host smart-d8e0c7f9-691b-4c17-879b-b2efc7d7d96e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=414692560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.414692560
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.225980763
Short name T763
Test name
Test status
Simulation time 9294044 ps
CPU time 1.46 seconds
Started May 30 01:15:31 PM PDT 24
Finished May 30 01:15:34 PM PDT 24
Peak memory 236980 kb
Host smart-8ed3e177-4ed5-4189-8ea4-0112fef75d52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=225980763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.225980763
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.242926947
Short name T192
Test name
Test status
Simulation time 716255201 ps
CPU time 42.13 seconds
Started May 30 01:15:32 PM PDT 24
Finished May 30 01:16:16 PM PDT 24
Peak memory 245140 kb
Host smart-e0ecfc4e-2f59-4fb7-a0d0-310f56bd812b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=242926947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_out
standing.242926947
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3230142822
Short name T136
Test name
Test status
Simulation time 988473382 ps
CPU time 105.95 seconds
Started May 30 01:15:30 PM PDT 24
Finished May 30 01:17:18 PM PDT 24
Peak memory 265472 kb
Host smart-ed396fd0-255f-46a3-82fb-c2b7b11a0528
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3230142822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3230142822
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3497633477
Short name T714
Test name
Test status
Simulation time 667258509 ps
CPU time 21.64 seconds
Started May 30 01:15:28 PM PDT 24
Finished May 30 01:15:50 PM PDT 24
Peak memory 253880 kb
Host smart-528636a8-78bf-43e3-ba8a-c9fe95086d8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3497633477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3497633477
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2152934618
Short name T809
Test name
Test status
Simulation time 187096022 ps
CPU time 3.77 seconds
Started May 30 01:15:29 PM PDT 24
Finished May 30 01:15:34 PM PDT 24
Peak memory 240516 kb
Host smart-7e351085-4811-401c-bd89-dd8bba43f10d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152934618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.2152934618
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.690661484
Short name T812
Test name
Test status
Simulation time 67304118 ps
CPU time 5.26 seconds
Started May 30 01:15:29 PM PDT 24
Finished May 30 01:15:35 PM PDT 24
Peak memory 236824 kb
Host smart-4336da41-b648-45bc-885b-454b7016eec6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=690661484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.690661484
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3669607445
Short name T235
Test name
Test status
Simulation time 6362528 ps
CPU time 1.34 seconds
Started May 30 01:15:28 PM PDT 24
Finished May 30 01:15:31 PM PDT 24
Peak memory 237004 kb
Host smart-58c5c902-a059-48e9-af3c-2da3b4f60fc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3669607445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3669607445
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3408660787
Short name T194
Test name
Test status
Simulation time 97724073 ps
CPU time 12.26 seconds
Started May 30 01:15:30 PM PDT 24
Finished May 30 01:15:44 PM PDT 24
Peak memory 248716 kb
Host smart-41c4dbff-217d-4933-b7e5-30a381e2ceb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3408660787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.3408660787
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.795415222
Short name T131
Test name
Test status
Simulation time 3294281677 ps
CPU time 315.96 seconds
Started May 30 01:15:29 PM PDT 24
Finished May 30 01:20:47 PM PDT 24
Peak memory 267564 kb
Host smart-0d5df7ca-c703-4197-b24a-49ddc00b16d3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795415222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.795415222
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2198811674
Short name T744
Test name
Test status
Simulation time 104015621 ps
CPU time 4.38 seconds
Started May 30 01:15:27 PM PDT 24
Finished May 30 01:15:32 PM PDT 24
Peak memory 247792 kb
Host smart-8ce391f5-dbe3-47b6-92cc-544a06f83f32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2198811674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2198811674
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3019509493
Short name T358
Test name
Test status
Simulation time 96951123 ps
CPU time 9.87 seconds
Started May 30 01:15:30 PM PDT 24
Finished May 30 01:15:41 PM PDT 24
Peak memory 254344 kb
Host smart-3fa54c64-2c20-4fc0-995e-8b64a7cfdee2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019509493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3019509493
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3740051568
Short name T781
Test name
Test status
Simulation time 128964302 ps
CPU time 5.23 seconds
Started May 30 01:15:29 PM PDT 24
Finished May 30 01:15:36 PM PDT 24
Peak memory 236892 kb
Host smart-02c6d980-71c8-4467-b921-25e2f90731cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3740051568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3740051568
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.917411552
Short name T731
Test name
Test status
Simulation time 6250322 ps
CPU time 1.41 seconds
Started May 30 01:15:29 PM PDT 24
Finished May 30 01:15:31 PM PDT 24
Peak memory 236944 kb
Host smart-a325bb1d-6df6-4915-989e-1fbed28b8a5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=917411552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.917411552
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1802632309
Short name T177
Test name
Test status
Simulation time 1051526271 ps
CPU time 18.07 seconds
Started May 30 01:15:34 PM PDT 24
Finished May 30 01:15:53 PM PDT 24
Peak memory 244208 kb
Host smart-571b6179-e233-4ecf-8a8c-9fa298401ef6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1802632309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1802632309
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2475198437
Short name T137
Test name
Test status
Simulation time 7909792740 ps
CPU time 133.83 seconds
Started May 30 01:15:30 PM PDT 24
Finished May 30 01:17:45 PM PDT 24
Peak memory 257272 kb
Host smart-faab2f02-9c5c-4123-9d1b-7a8d5bed364e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2475198437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.2475198437
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1322518614
Short name T151
Test name
Test status
Simulation time 9296739468 ps
CPU time 313.09 seconds
Started May 30 01:15:30 PM PDT 24
Finished May 30 01:20:44 PM PDT 24
Peak memory 265500 kb
Host smart-cf269586-d350-4cce-b6d6-3e4821275e01
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322518614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1322518614
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.419952242
Short name T822
Test name
Test status
Simulation time 303279447 ps
CPU time 6.49 seconds
Started May 30 01:15:31 PM PDT 24
Finished May 30 01:15:39 PM PDT 24
Peak memory 248652 kb
Host smart-1f4e6ecb-ca14-40a6-b26f-9c69010aecc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=419952242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.419952242
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.903365206
Short name T803
Test name
Test status
Simulation time 49614982 ps
CPU time 2.51 seconds
Started May 30 01:15:30 PM PDT 24
Finished May 30 01:15:34 PM PDT 24
Peak memory 237292 kb
Host smart-98b6fb6e-83cf-4ba5-8912-62d33281f173
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=903365206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.903365206
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.279251627
Short name T816
Test name
Test status
Simulation time 470931944 ps
CPU time 8.01 seconds
Started May 30 01:15:37 PM PDT 24
Finished May 30 01:15:45 PM PDT 24
Peak memory 240868 kb
Host smart-6dcba650-d3d1-4ebd-8322-4d42190b9589
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279251627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.279251627
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.260216497
Short name T195
Test name
Test status
Simulation time 23796796 ps
CPU time 3.36 seconds
Started May 30 01:15:36 PM PDT 24
Finished May 30 01:15:40 PM PDT 24
Peak memory 235960 kb
Host smart-c0f252ff-57d9-43ff-ae2c-139f68aa8ea3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=260216497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.260216497
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1384701460
Short name T785
Test name
Test status
Simulation time 17311624 ps
CPU time 1.31 seconds
Started May 30 01:15:33 PM PDT 24
Finished May 30 01:15:36 PM PDT 24
Peak memory 236996 kb
Host smart-ef699bfb-2515-4262-8274-04d0fc05d59f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1384701460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1384701460
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3840175656
Short name T755
Test name
Test status
Simulation time 734266615 ps
CPU time 23.37 seconds
Started May 30 01:15:28 PM PDT 24
Finished May 30 01:15:53 PM PDT 24
Peak memory 245172 kb
Host smart-630075c4-ab71-44be-8d3b-36964aea0d17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3840175656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3840175656
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.1630230562
Short name T713
Test name
Test status
Simulation time 188440140 ps
CPU time 12.75 seconds
Started May 30 01:15:33 PM PDT 24
Finished May 30 01:15:47 PM PDT 24
Peak memory 248868 kb
Host smart-508e0495-b659-4d17-8634-d4e1fcb633bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1630230562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.1630230562
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.111959645
Short name T773
Test name
Test status
Simulation time 6664036839 ps
CPU time 106.97 seconds
Started May 30 01:14:42 PM PDT 24
Finished May 30 01:16:30 PM PDT 24
Peak memory 240484 kb
Host smart-9c0b8821-245a-4e63-9391-b5fd9e8f0e46
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=111959645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.111959645
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2657912538
Short name T190
Test name
Test status
Simulation time 8914555498 ps
CPU time 520.67 seconds
Started May 30 01:14:42 PM PDT 24
Finished May 30 01:23:24 PM PDT 24
Peak memory 240508 kb
Host smart-1eb88709-bbf7-434d-83bc-ac1719ab1cbd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2657912538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2657912538
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2596284745
Short name T797
Test name
Test status
Simulation time 295462288 ps
CPU time 6.28 seconds
Started May 30 01:14:38 PM PDT 24
Finished May 30 01:14:46 PM PDT 24
Peak memory 240412 kb
Host smart-e748e94e-2a1c-48be-a8db-2284a425642a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2596284745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2596284745
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2671621008
Short name T174
Test name
Test status
Simulation time 112094130 ps
CPU time 4.48 seconds
Started May 30 01:14:37 PM PDT 24
Finished May 30 01:14:43 PM PDT 24
Peak memory 241736 kb
Host smart-a898bacf-9f18-4a44-94e3-d0857fd38476
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671621008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2671621008
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.4057963217
Short name T817
Test name
Test status
Simulation time 349679899 ps
CPU time 7.33 seconds
Started May 30 01:14:38 PM PDT 24
Finished May 30 01:14:47 PM PDT 24
Peak memory 236900 kb
Host smart-e4ebbb61-fea5-4d48-8969-9a4f1216c7f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4057963217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.4057963217
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1919109391
Short name T813
Test name
Test status
Simulation time 25929037 ps
CPU time 1.45 seconds
Started May 30 01:14:38 PM PDT 24
Finished May 30 01:14:41 PM PDT 24
Peak memory 236980 kb
Host smart-644af0c8-c294-4d84-978c-596dee85b0a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1919109391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1919109391
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3759344057
Short name T771
Test name
Test status
Simulation time 4107215860 ps
CPU time 41.09 seconds
Started May 30 01:14:38 PM PDT 24
Finished May 30 01:15:21 PM PDT 24
Peak memory 248724 kb
Host smart-cb80dc6b-d7a6-4429-b23c-3c9f53a0c02c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3759344057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3759344057
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.86049353
Short name T120
Test name
Test status
Simulation time 17834370054 ps
CPU time 349.34 seconds
Started May 30 01:14:37 PM PDT 24
Finished May 30 01:20:28 PM PDT 24
Peak memory 265396 kb
Host smart-76784659-2dc5-4e56-83c8-ad93818bbb58
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=86049353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_errors
.86049353
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3558995009
Short name T143
Test name
Test status
Simulation time 13882487497 ps
CPU time 560.96 seconds
Started May 30 01:14:37 PM PDT 24
Finished May 30 01:23:59 PM PDT 24
Peak memory 269932 kb
Host smart-8228f668-f441-42b8-9479-b1028983b6b7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558995009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.3558995009
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3793222673
Short name T825
Test name
Test status
Simulation time 346833100 ps
CPU time 7.35 seconds
Started May 30 01:14:37 PM PDT 24
Finished May 30 01:14:45 PM PDT 24
Peak memory 249872 kb
Host smart-25e3b46c-b656-43aa-acdb-f8c56f40e0f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3793222673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.3793222673
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2814965375
Short name T776
Test name
Test status
Simulation time 17892677 ps
CPU time 1.27 seconds
Started May 30 01:15:29 PM PDT 24
Finished May 30 01:15:32 PM PDT 24
Peak memory 236940 kb
Host smart-90c1f4bb-4de5-4fca-8eab-e3444adf7cca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2814965375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2814965375
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3636966571
Short name T750
Test name
Test status
Simulation time 14083129 ps
CPU time 1.64 seconds
Started May 30 01:15:32 PM PDT 24
Finished May 30 01:15:35 PM PDT 24
Peak memory 235980 kb
Host smart-b57e60c9-8911-43b8-b40b-0d08a1a92644
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3636966571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.3636966571
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2141860447
Short name T350
Test name
Test status
Simulation time 10789966 ps
CPU time 1.61 seconds
Started May 30 01:15:36 PM PDT 24
Finished May 30 01:15:38 PM PDT 24
Peak memory 236060 kb
Host smart-a1bbc604-3004-45c6-91f8-352e2469711d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2141860447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2141860447
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.355660319
Short name T826
Test name
Test status
Simulation time 10962540 ps
CPU time 1.32 seconds
Started May 30 01:15:29 PM PDT 24
Finished May 30 01:15:32 PM PDT 24
Peak memory 236052 kb
Host smart-7a0264ee-3415-4162-bac2-d016a9513855
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=355660319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.355660319
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2708060167
Short name T793
Test name
Test status
Simulation time 26112186 ps
CPU time 1.46 seconds
Started May 30 01:15:36 PM PDT 24
Finished May 30 01:15:38 PM PDT 24
Peak memory 237004 kb
Host smart-97c929bd-af1b-4e3d-adc1-c3c4066de9c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2708060167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2708060167
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.2218772238
Short name T823
Test name
Test status
Simulation time 6183433 ps
CPU time 1.38 seconds
Started May 30 01:15:30 PM PDT 24
Finished May 30 01:15:33 PM PDT 24
Peak memory 236940 kb
Host smart-d7777b65-4b13-4ad3-a031-284409c1b9f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2218772238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.2218772238
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2901640913
Short name T352
Test name
Test status
Simulation time 26398792 ps
CPU time 1.57 seconds
Started May 30 01:15:36 PM PDT 24
Finished May 30 01:15:39 PM PDT 24
Peak memory 236996 kb
Host smart-08572092-8791-455e-b464-65370c50be7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2901640913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2901640913
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1014096501
Short name T765
Test name
Test status
Simulation time 30360763 ps
CPU time 1.38 seconds
Started May 30 01:15:32 PM PDT 24
Finished May 30 01:15:35 PM PDT 24
Peak memory 236064 kb
Host smart-fb122654-bb4e-4a40-b877-427f97c5bf11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1014096501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1014096501
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1008051572
Short name T723
Test name
Test status
Simulation time 9602828 ps
CPU time 1.22 seconds
Started May 30 01:15:32 PM PDT 24
Finished May 30 01:15:35 PM PDT 24
Peak memory 236944 kb
Host smart-b9b89180-d469-4205-b4ef-af4162a1c67c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1008051572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.1008051572
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2995394950
Short name T830
Test name
Test status
Simulation time 3366782333 ps
CPU time 227.84 seconds
Started May 30 01:14:39 PM PDT 24
Finished May 30 01:18:28 PM PDT 24
Peak memory 240516 kb
Host smart-8655931b-6309-4cc5-be34-ccafaa141c88
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2995394950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2995394950
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3179215477
Short name T191
Test name
Test status
Simulation time 5721637087 ps
CPU time 354.97 seconds
Started May 30 01:14:38 PM PDT 24
Finished May 30 01:20:34 PM PDT 24
Peak memory 236048 kb
Host smart-d834aa47-6120-41da-a13a-0706ef83a3fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3179215477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3179215477
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3648678800
Short name T193
Test name
Test status
Simulation time 41026473 ps
CPU time 6.78 seconds
Started May 30 01:14:37 PM PDT 24
Finished May 30 01:14:45 PM PDT 24
Peak memory 240460 kb
Host smart-1f20f03d-a81e-423a-85a5-164b174e7496
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3648678800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3648678800
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2352921280
Short name T756
Test name
Test status
Simulation time 189614219 ps
CPU time 4.55 seconds
Started May 30 01:14:43 PM PDT 24
Finished May 30 01:14:48 PM PDT 24
Peak memory 237092 kb
Host smart-5179c302-5e1d-4165-b14d-6ddf4b1a754e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352921280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2352921280
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3892776408
Short name T786
Test name
Test status
Simulation time 90770334 ps
CPU time 8.57 seconds
Started May 30 01:14:42 PM PDT 24
Finished May 30 01:14:52 PM PDT 24
Peak memory 236880 kb
Host smart-2d5f16e1-afa7-4256-8d1f-2eb2139746ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3892776408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3892776408
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.441691583
Short name T758
Test name
Test status
Simulation time 27788047 ps
CPU time 1.41 seconds
Started May 30 01:14:37 PM PDT 24
Finished May 30 01:14:39 PM PDT 24
Peak memory 236968 kb
Host smart-f70ebee6-b78d-453b-bb50-f0474835668c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=441691583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.441691583
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1387274356
Short name T196
Test name
Test status
Simulation time 262686808 ps
CPU time 26.41 seconds
Started May 30 01:14:37 PM PDT 24
Finished May 30 01:15:05 PM PDT 24
Peak memory 245176 kb
Host smart-bfedcc28-df06-448d-97a4-bdcff3d41307
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1387274356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1387274356
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1485046565
Short name T717
Test name
Test status
Simulation time 33528634 ps
CPU time 4.8 seconds
Started May 30 01:14:39 PM PDT 24
Finished May 30 01:14:45 PM PDT 24
Peak memory 248544 kb
Host smart-5d7dbb3b-22fa-4553-9675-04fef840446f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1485046565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1485046565
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1483816011
Short name T348
Test name
Test status
Simulation time 6583551 ps
CPU time 1.33 seconds
Started May 30 01:15:31 PM PDT 24
Finished May 30 01:15:33 PM PDT 24
Peak memory 235008 kb
Host smart-cc7fc3b8-8311-4ca6-9256-707db4f1cdd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1483816011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1483816011
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1150085405
Short name T767
Test name
Test status
Simulation time 13165642 ps
CPU time 1.37 seconds
Started May 30 01:15:40 PM PDT 24
Finished May 30 01:15:42 PM PDT 24
Peak memory 235036 kb
Host smart-32a3f217-9b07-4e5e-9843-cdec1f4bd2f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1150085405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.1150085405
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1794348237
Short name T752
Test name
Test status
Simulation time 32029133 ps
CPU time 1.39 seconds
Started May 30 01:15:32 PM PDT 24
Finished May 30 01:15:35 PM PDT 24
Peak memory 236924 kb
Host smart-6b697437-9610-4970-9894-a8fc606a39ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1794348237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1794348237
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1541020299
Short name T346
Test name
Test status
Simulation time 9008437 ps
CPU time 1.4 seconds
Started May 30 01:15:40 PM PDT 24
Finished May 30 01:15:42 PM PDT 24
Peak memory 237008 kb
Host smart-a1db282d-74fa-4fc7-9df4-88c4d16796e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1541020299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.1541020299
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2071231673
Short name T764
Test name
Test status
Simulation time 9107095 ps
CPU time 1.21 seconds
Started May 30 01:15:37 PM PDT 24
Finished May 30 01:15:39 PM PDT 24
Peak memory 237008 kb
Host smart-364c72ca-14f4-479a-b83c-ed5b2d42ca60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2071231673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2071231673
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1644161709
Short name T349
Test name
Test status
Simulation time 6462485 ps
CPU time 1.37 seconds
Started May 30 01:15:34 PM PDT 24
Finished May 30 01:15:36 PM PDT 24
Peak memory 234972 kb
Host smart-47689823-3c63-426d-af2c-eb1a71bff78d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1644161709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1644161709
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2914414451
Short name T351
Test name
Test status
Simulation time 8559591 ps
CPU time 1.52 seconds
Started May 30 01:15:32 PM PDT 24
Finished May 30 01:15:35 PM PDT 24
Peak memory 235988 kb
Host smart-f9df175e-2c6f-4a60-8a98-662aae0b3aa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2914414451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.2914414451
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.4232880392
Short name T806
Test name
Test status
Simulation time 7128333 ps
CPU time 1.46 seconds
Started May 30 01:15:39 PM PDT 24
Finished May 30 01:15:41 PM PDT 24
Peak memory 237008 kb
Host smart-c00e920e-7a2e-4548-86f2-fc399dc6c32d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4232880392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.4232880392
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2436910479
Short name T729
Test name
Test status
Simulation time 31702884 ps
CPU time 1.37 seconds
Started May 30 01:15:33 PM PDT 24
Finished May 30 01:15:35 PM PDT 24
Peak memory 236128 kb
Host smart-99e3c9ff-927a-4a11-8ffc-e3ed7119977d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2436910479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2436910479
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.4094783575
Short name T779
Test name
Test status
Simulation time 13469529863 ps
CPU time 261.61 seconds
Started May 30 01:14:52 PM PDT 24
Finished May 30 01:19:15 PM PDT 24
Peak memory 240416 kb
Host smart-003a5af6-d92c-4e91-9b41-e9220d263ee6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4094783575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.4094783575
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2047527608
Short name T205
Test name
Test status
Simulation time 2866575092 ps
CPU time 219.27 seconds
Started May 30 01:14:38 PM PDT 24
Finished May 30 01:18:19 PM PDT 24
Peak memory 236960 kb
Host smart-a7b8070c-d437-4dfd-a06c-428dd61f749e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2047527608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2047527608
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2032294082
Short name T795
Test name
Test status
Simulation time 21694568 ps
CPU time 4.02 seconds
Started May 30 01:14:43 PM PDT 24
Finished May 30 01:14:48 PM PDT 24
Peak memory 240460 kb
Host smart-da33b58c-e536-4f05-9d37-86991e3d12d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2032294082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2032294082
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3154377806
Short name T808
Test name
Test status
Simulation time 198482016 ps
CPU time 13.91 seconds
Started May 30 01:14:51 PM PDT 24
Finished May 30 01:15:06 PM PDT 24
Peak memory 242628 kb
Host smart-5f157e19-aef9-4a1f-a63b-aed382dccb67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154377806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.3154377806
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.41799933
Short name T802
Test name
Test status
Simulation time 369476616 ps
CPU time 9.1 seconds
Started May 30 01:14:38 PM PDT 24
Finished May 30 01:14:49 PM PDT 24
Peak memory 240444 kb
Host smart-85a67aa2-b7bb-43e1-8bb3-1ae6cdb486e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=41799933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.41799933
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1610923752
Short name T745
Test name
Test status
Simulation time 8052533 ps
CPU time 1.46 seconds
Started May 30 01:14:43 PM PDT 24
Finished May 30 01:14:45 PM PDT 24
Peak memory 236996 kb
Host smart-259f88d5-a0c5-499d-afb4-07314b1ed1f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1610923752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1610923752
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.690511660
Short name T794
Test name
Test status
Simulation time 89520935 ps
CPU time 12.08 seconds
Started May 30 01:14:51 PM PDT 24
Finished May 30 01:15:04 PM PDT 24
Peak memory 245168 kb
Host smart-b31e3132-d357-46ce-b142-85046452ab3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=690511660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outs
tanding.690511660
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3040827925
Short name T132
Test name
Test status
Simulation time 5483229339 ps
CPU time 384.32 seconds
Started May 30 01:14:36 PM PDT 24
Finished May 30 01:21:01 PM PDT 24
Peak memory 265392 kb
Host smart-8e532e48-22a7-4d6f-a3cf-5d3a46b22490
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3040827925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3040827925
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.717345410
Short name T128
Test name
Test status
Simulation time 4657115396 ps
CPU time 606.36 seconds
Started May 30 01:14:38 PM PDT 24
Finished May 30 01:24:46 PM PDT 24
Peak memory 265428 kb
Host smart-c6f3d8c8-e465-4646-ae59-0105cb0af7bf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717345410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.717345410
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.4258279450
Short name T715
Test name
Test status
Simulation time 51512107 ps
CPU time 8.15 seconds
Started May 30 01:14:38 PM PDT 24
Finished May 30 01:14:48 PM PDT 24
Peak memory 248676 kb
Host smart-e1eb6b76-1754-48af-ab47-ff51e76385a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4258279450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.4258279450
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2261989485
Short name T156
Test name
Test status
Simulation time 9922842 ps
CPU time 1.27 seconds
Started May 30 01:15:32 PM PDT 24
Finished May 30 01:15:35 PM PDT 24
Peak memory 236128 kb
Host smart-fdb1ab9f-39a7-4a94-aae6-492d4e4f8be1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2261989485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2261989485
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1080345218
Short name T728
Test name
Test status
Simulation time 9494703 ps
CPU time 1.5 seconds
Started May 30 01:15:32 PM PDT 24
Finished May 30 01:15:35 PM PDT 24
Peak memory 236128 kb
Host smart-a8d87c25-aa3e-4283-aa2a-181e59b7761d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1080345218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1080345218
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2303455189
Short name T774
Test name
Test status
Simulation time 13685839 ps
CPU time 1.49 seconds
Started May 30 01:15:33 PM PDT 24
Finished May 30 01:15:36 PM PDT 24
Peak memory 236032 kb
Host smart-a036b986-dfe8-4e7a-be23-f3f3fceb775f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2303455189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2303455189
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1368890485
Short name T727
Test name
Test status
Simulation time 10424603 ps
CPU time 1.26 seconds
Started May 30 01:15:33 PM PDT 24
Finished May 30 01:15:36 PM PDT 24
Peak memory 236028 kb
Host smart-0ae7b328-308b-4da7-bd1a-e8efe1ae8194
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1368890485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1368890485
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1648786937
Short name T735
Test name
Test status
Simulation time 14929729 ps
CPU time 1.48 seconds
Started May 30 01:15:32 PM PDT 24
Finished May 30 01:15:35 PM PDT 24
Peak memory 236008 kb
Host smart-98a25883-62ec-4a30-8ef0-0554ccb28cc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1648786937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1648786937
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.384989239
Short name T796
Test name
Test status
Simulation time 10921445 ps
CPU time 1.3 seconds
Started May 30 01:15:32 PM PDT 24
Finished May 30 01:15:35 PM PDT 24
Peak memory 235980 kb
Host smart-04837989-69f5-45d0-89ab-7754ef5b2eae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=384989239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.384989239
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2823055828
Short name T740
Test name
Test status
Simulation time 10560984 ps
CPU time 1.44 seconds
Started May 30 01:15:33 PM PDT 24
Finished May 30 01:15:35 PM PDT 24
Peak memory 236912 kb
Host smart-9062af6e-8a79-4570-ae91-12dfcb4550ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2823055828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2823055828
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.4272574225
Short name T746
Test name
Test status
Simulation time 9815204 ps
CPU time 1.62 seconds
Started May 30 01:15:33 PM PDT 24
Finished May 30 01:15:36 PM PDT 24
Peak memory 236068 kb
Host smart-2be97129-1ea1-4563-b204-a8a494708eaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4272574225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.4272574225
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1871095148
Short name T719
Test name
Test status
Simulation time 25241050 ps
CPU time 1.47 seconds
Started May 30 01:15:33 PM PDT 24
Finished May 30 01:15:36 PM PDT 24
Peak memory 236980 kb
Host smart-083b9d87-47fe-41f9-8e2e-f6c05d80d6c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1871095148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1871095148
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1149308301
Short name T157
Test name
Test status
Simulation time 16903185 ps
CPU time 1.44 seconds
Started May 30 01:15:32 PM PDT 24
Finished May 30 01:15:35 PM PDT 24
Peak memory 236036 kb
Host smart-49bac467-98bb-40db-94a1-61f6e4a417a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1149308301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1149308301
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.114246564
Short name T820
Test name
Test status
Simulation time 42462105 ps
CPU time 5.01 seconds
Started May 30 01:14:51 PM PDT 24
Finished May 30 01:14:57 PM PDT 24
Peak memory 256920 kb
Host smart-dae9fd7e-6b16-4c71-8a44-537fa634ad91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114246564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.114246564
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2537904869
Short name T732
Test name
Test status
Simulation time 20542752 ps
CPU time 3.97 seconds
Started May 30 01:14:50 PM PDT 24
Finished May 30 01:14:55 PM PDT 24
Peak memory 236864 kb
Host smart-a62c48ec-2982-4652-b06e-a6ebabbf0361
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2537904869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2537904869
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3714948000
Short name T754
Test name
Test status
Simulation time 8395478 ps
CPU time 1.5 seconds
Started May 30 01:14:51 PM PDT 24
Finished May 30 01:14:53 PM PDT 24
Peak memory 236072 kb
Host smart-f8b59034-0b93-47cc-849f-3a651991b3cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3714948000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.3714948000
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.209747055
Short name T724
Test name
Test status
Simulation time 1886971964 ps
CPU time 18.19 seconds
Started May 30 01:14:51 PM PDT 24
Finished May 30 01:15:10 PM PDT 24
Peak memory 245152 kb
Host smart-6729bd39-4d4d-462d-bd11-6961806860fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=209747055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.209747055
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1240204387
Short name T814
Test name
Test status
Simulation time 1703753619 ps
CPU time 86.43 seconds
Started May 30 01:14:50 PM PDT 24
Finished May 30 01:16:17 PM PDT 24
Peak memory 257200 kb
Host smart-004ee993-d00b-4481-95a5-923b83fd0f8d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1240204387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.1240204387
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2587724937
Short name T355
Test name
Test status
Simulation time 6750527620 ps
CPU time 511.58 seconds
Started May 30 01:14:51 PM PDT 24
Finished May 30 01:23:23 PM PDT 24
Peak memory 265428 kb
Host smart-1deba252-1b0b-4e46-8702-c46432b24fb6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587724937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.2587724937
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3221699933
Short name T716
Test name
Test status
Simulation time 1587043312 ps
CPU time 12.6 seconds
Started May 30 01:14:52 PM PDT 24
Finished May 30 01:15:05 PM PDT 24
Peak memory 247848 kb
Host smart-ae87913e-16dd-42bd-b989-514cfa042a88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3221699933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3221699933
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1032436898
Short name T770
Test name
Test status
Simulation time 179897815 ps
CPU time 27.39 seconds
Started May 30 01:14:53 PM PDT 24
Finished May 30 01:15:21 PM PDT 24
Peak memory 237168 kb
Host smart-63fbb02f-90fd-45e7-a565-d71d00718655
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1032436898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1032436898
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3381251467
Short name T777
Test name
Test status
Simulation time 1441945673 ps
CPU time 12.61 seconds
Started May 30 01:14:51 PM PDT 24
Finished May 30 01:15:05 PM PDT 24
Peak memory 248772 kb
Host smart-512eaf41-69d1-475b-934d-50fefa969c83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381251467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.3381251467
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.598516688
Short name T742
Test name
Test status
Simulation time 186891179 ps
CPU time 7.81 seconds
Started May 30 01:14:51 PM PDT 24
Finished May 30 01:15:00 PM PDT 24
Peak memory 236900 kb
Host smart-5ba55388-80ca-429b-9cc9-087a164396ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=598516688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.598516688
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3559280687
Short name T828
Test name
Test status
Simulation time 10165642 ps
CPU time 1.55 seconds
Started May 30 01:14:49 PM PDT 24
Finished May 30 01:14:52 PM PDT 24
Peak memory 237008 kb
Host smart-00457365-2863-4685-b130-18fa7422e9bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3559280687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3559280687
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.548750207
Short name T827
Test name
Test status
Simulation time 5367784162 ps
CPU time 44.33 seconds
Started May 30 01:14:55 PM PDT 24
Finished May 30 01:15:40 PM PDT 24
Peak memory 248776 kb
Host smart-1f8e7f93-59ab-4d51-840d-ec6b12f42097
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=548750207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outs
tanding.548750207
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1648253302
Short name T139
Test name
Test status
Simulation time 1777091218 ps
CPU time 207.88 seconds
Started May 30 01:14:50 PM PDT 24
Finished May 30 01:18:18 PM PDT 24
Peak memory 271224 kb
Host smart-f1110e89-a86b-4b61-8e77-8edc188f440c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1648253302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1648253302
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3793969821
Short name T121
Test name
Test status
Simulation time 17845275188 ps
CPU time 592.59 seconds
Started May 30 01:14:50 PM PDT 24
Finished May 30 01:24:44 PM PDT 24
Peak memory 265452 kb
Host smart-85fb04fa-d020-419b-989c-69b97f0d6636
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793969821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3793969821
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.963286040
Short name T775
Test name
Test status
Simulation time 41207314 ps
CPU time 5.9 seconds
Started May 30 01:14:50 PM PDT 24
Finished May 30 01:14:57 PM PDT 24
Peak memory 248784 kb
Host smart-1bca53ee-28e7-47f8-a9fe-4445ac4529d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=963286040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.963286040
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3508141147
Short name T759
Test name
Test status
Simulation time 493713914 ps
CPU time 12.03 seconds
Started May 30 01:14:57 PM PDT 24
Finished May 30 01:15:10 PM PDT 24
Peak memory 250996 kb
Host smart-2b2cc6b9-0ffa-4831-8238-69480abeef3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508141147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3508141147
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.409189573
Short name T772
Test name
Test status
Simulation time 388594429 ps
CPU time 4.3 seconds
Started May 30 01:14:51 PM PDT 24
Finished May 30 01:14:56 PM PDT 24
Peak memory 236896 kb
Host smart-b3410fda-628c-4996-ae6a-1e9d18590e6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=409189573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.409189573
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2545346768
Short name T721
Test name
Test status
Simulation time 6165399 ps
CPU time 1.36 seconds
Started May 30 01:14:50 PM PDT 24
Finished May 30 01:14:52 PM PDT 24
Peak memory 234996 kb
Host smart-ae85cea8-3cb6-4103-8544-f9d162c06f33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2545346768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2545346768
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1002212767
Short name T178
Test name
Test status
Simulation time 680457264 ps
CPU time 24.22 seconds
Started May 30 01:14:52 PM PDT 24
Finished May 30 01:15:17 PM PDT 24
Peak memory 245116 kb
Host smart-3d091796-e427-4aeb-97a5-d62eb3e06c4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1002212767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1002212767
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1441529953
Short name T152
Test name
Test status
Simulation time 11587875224 ps
CPU time 170.45 seconds
Started May 30 01:14:52 PM PDT 24
Finished May 30 01:17:43 PM PDT 24
Peak memory 257288 kb
Host smart-0642a228-2683-483d-a4e9-8990dfc383e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1441529953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1441529953
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3469445196
Short name T720
Test name
Test status
Simulation time 130760752 ps
CPU time 10.53 seconds
Started May 30 01:14:50 PM PDT 24
Finished May 30 01:15:01 PM PDT 24
Peak memory 248668 kb
Host smart-00e64dd6-7a5f-47c1-95f9-bbc3e515a7d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3469445196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3469445196
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1415059099
Short name T790
Test name
Test status
Simulation time 33108945 ps
CPU time 4.62 seconds
Started May 30 01:14:58 PM PDT 24
Finished May 30 01:15:03 PM PDT 24
Peak memory 241664 kb
Host smart-2f7cc82d-662e-4e84-b6c4-00e349dfd19c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415059099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1415059099
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.4103399249
Short name T805
Test name
Test status
Simulation time 475365595 ps
CPU time 9.46 seconds
Started May 30 01:14:52 PM PDT 24
Finished May 30 01:15:02 PM PDT 24
Peak memory 236872 kb
Host smart-670099d9-106d-4346-88aa-eac87dba5317
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4103399249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.4103399249
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1859258031
Short name T792
Test name
Test status
Simulation time 18317719 ps
CPU time 1.33 seconds
Started May 30 01:14:52 PM PDT 24
Finished May 30 01:14:54 PM PDT 24
Peak memory 236952 kb
Host smart-4b60bf21-04ad-4755-9d86-e71b23b0363c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1859258031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1859258031
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.388265943
Short name T760
Test name
Test status
Simulation time 337052507 ps
CPU time 12.7 seconds
Started May 30 01:14:52 PM PDT 24
Finished May 30 01:15:06 PM PDT 24
Peak memory 245148 kb
Host smart-417e82c3-b8a2-484e-ab8d-c0d2a4f2149a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=388265943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.388265943
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.111179524
Short name T138
Test name
Test status
Simulation time 1681302674 ps
CPU time 118.73 seconds
Started May 30 01:14:50 PM PDT 24
Finished May 30 01:16:49 PM PDT 24
Peak memory 257028 kb
Host smart-caeb57df-390a-4cbf-bffb-c2c22fea88cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=111179524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_error
s.111179524
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1916789027
Short name T122
Test name
Test status
Simulation time 7908956844 ps
CPU time 466.94 seconds
Started May 30 01:14:58 PM PDT 24
Finished May 30 01:22:46 PM PDT 24
Peak memory 265412 kb
Host smart-d0d554c7-e160-487b-bb81-bcf23f98403f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916789027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.1916789027
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3933847033
Short name T811
Test name
Test status
Simulation time 1391160028 ps
CPU time 23.9 seconds
Started May 30 01:14:58 PM PDT 24
Finished May 30 01:15:23 PM PDT 24
Peak memory 248120 kb
Host smart-020fea4a-9b21-4818-bcc6-a54536b1118e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3933847033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3933847033
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3846080064
Short name T739
Test name
Test status
Simulation time 180644108 ps
CPU time 8.81 seconds
Started May 30 01:15:13 PM PDT 24
Finished May 30 01:15:23 PM PDT 24
Peak memory 256460 kb
Host smart-a53b4087-de2d-43fd-b8e2-3859adfa7ea2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846080064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3846080064
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2408871812
Short name T801
Test name
Test status
Simulation time 1004618137 ps
CPU time 10.07 seconds
Started May 30 01:15:15 PM PDT 24
Finished May 30 01:15:26 PM PDT 24
Peak memory 236792 kb
Host smart-ef7ae12d-89c8-403b-96ac-864c54183ae9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2408871812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2408871812
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1811382015
Short name T810
Test name
Test status
Simulation time 8660403 ps
CPU time 1.41 seconds
Started May 30 01:15:15 PM PDT 24
Finished May 30 01:15:17 PM PDT 24
Peak memory 237004 kb
Host smart-30c25161-18be-4f9a-9197-c1885a716b7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1811382015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1811382015
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.4013669891
Short name T769
Test name
Test status
Simulation time 554297538 ps
CPU time 17.58 seconds
Started May 30 01:15:14 PM PDT 24
Finished May 30 01:15:33 PM PDT 24
Peak memory 248720 kb
Host smart-cccb6d5b-7366-4f92-bf19-96f78c40c24f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4013669891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.4013669891
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1262098423
Short name T146
Test name
Test status
Simulation time 3045623848 ps
CPU time 88.01 seconds
Started May 30 01:14:53 PM PDT 24
Finished May 30 01:16:22 PM PDT 24
Peak memory 257240 kb
Host smart-866bcfbe-4864-4709-a4b5-aafb2d67102b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1262098423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1262098423
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1826780218
Short name T356
Test name
Test status
Simulation time 13649337173 ps
CPU time 1036 seconds
Started May 30 01:14:52 PM PDT 24
Finished May 30 01:32:09 PM PDT 24
Peak memory 265440 kb
Host smart-dfdc5188-6972-4650-82ec-e5c3f7336e85
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826780218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.1826780218
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1170934519
Short name T815
Test name
Test status
Simulation time 565171155 ps
CPU time 20.01 seconds
Started May 30 01:14:51 PM PDT 24
Finished May 30 01:15:12 PM PDT 24
Peak memory 248720 kb
Host smart-84714a6a-25c2-4131-aacc-4b7929be266c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1170934519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1170934519
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.2667585536
Short name T95
Test name
Test status
Simulation time 42257238862 ps
CPU time 2450.06 seconds
Started May 30 01:19:27 PM PDT 24
Finished May 30 02:00:18 PM PDT 24
Peak memory 284644 kb
Host smart-7ff4cdc6-475f-43bb-b9a7-7996b0060624
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667585536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2667585536
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1418328920
Short name T226
Test name
Test status
Simulation time 191157207 ps
CPU time 10.52 seconds
Started May 30 01:19:21 PM PDT 24
Finished May 30 01:19:33 PM PDT 24
Peak memory 248776 kb
Host smart-35bc72f9-c851-43b0-afcf-cd6733a8c6ef
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1418328920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1418328920
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.3788406843
Short name T542
Test name
Test status
Simulation time 8525568601 ps
CPU time 124.48 seconds
Started May 30 01:19:19 PM PDT 24
Finished May 30 01:21:25 PM PDT 24
Peak memory 256224 kb
Host smart-9fb8179c-1c75-4fb4-8efd-50c745916542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37884
06843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.3788406843
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.3586571839
Short name T418
Test name
Test status
Simulation time 658514954 ps
CPU time 20.02 seconds
Started May 30 01:19:20 PM PDT 24
Finished May 30 01:19:42 PM PDT 24
Peak memory 254932 kb
Host smart-b094343f-2282-49c8-8123-d703676023db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35865
71839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3586571839
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.3704744035
Short name T291
Test name
Test status
Simulation time 17584492679 ps
CPU time 857.41 seconds
Started May 30 01:19:27 PM PDT 24
Finished May 30 01:33:45 PM PDT 24
Peak memory 270028 kb
Host smart-0b7222cf-b75c-423a-9ef5-d373965967d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704744035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.3704744035
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.129394825
Short name T539
Test name
Test status
Simulation time 12478994168 ps
CPU time 792.14 seconds
Started May 30 01:19:27 PM PDT 24
Finished May 30 01:32:40 PM PDT 24
Peak memory 269324 kb
Host smart-4cc30b43-1ad7-4bc1-872f-ddd8161fb207
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129394825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.129394825
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.481279629
Short name T264
Test name
Test status
Simulation time 1216981849 ps
CPU time 25.95 seconds
Started May 30 01:19:19 PM PDT 24
Finished May 30 01:19:46 PM PDT 24
Peak memory 248768 kb
Host smart-c27f432d-5226-4db6-856e-0b5913c47f41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48127
9629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.481279629
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3754219981
Short name T35
Test name
Test status
Simulation time 159605741 ps
CPU time 17.64 seconds
Started May 30 01:19:19 PM PDT 24
Finished May 30 01:19:38 PM PDT 24
Peak memory 248392 kb
Host smart-4f7a72ff-8fc1-478c-aa15-e77640b01eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37542
19981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3754219981
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3897632034
Short name T34
Test name
Test status
Simulation time 686569098 ps
CPU time 11.83 seconds
Started May 30 01:19:21 PM PDT 24
Finished May 30 01:19:35 PM PDT 24
Peak memory 269416 kb
Host smart-e095ce07-b706-4214-b6ba-49f4bec4f9c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3897632034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3897632034
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.1728336777
Short name T80
Test name
Test status
Simulation time 1548908995 ps
CPU time 30.22 seconds
Started May 30 01:19:21 PM PDT 24
Finished May 30 01:19:53 PM PDT 24
Peak memory 249144 kb
Host smart-ac118f28-2015-4d18-8bc0-dac61de9951c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17283
36777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1728336777
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.241680092
Short name T616
Test name
Test status
Simulation time 277304649 ps
CPU time 11.47 seconds
Started May 30 01:19:18 PM PDT 24
Finished May 30 01:19:31 PM PDT 24
Peak memory 248772 kb
Host smart-4c29ca66-deeb-4362-b59f-e2360a7a4f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24168
0092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.241680092
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.4161204270
Short name T710
Test name
Test status
Simulation time 647994659 ps
CPU time 16.64 seconds
Started May 30 01:19:31 PM PDT 24
Finished May 30 01:19:48 PM PDT 24
Peak memory 240548 kb
Host smart-7d8da4ac-1076-4dba-8084-821261e00229
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4161204270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.4161204270
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.2349672286
Short name T43
Test name
Test status
Simulation time 1899939792 ps
CPU time 81.77 seconds
Started May 30 01:19:19 PM PDT 24
Finished May 30 01:20:42 PM PDT 24
Peak memory 256900 kb
Host smart-f0a49508-ad98-4132-8b79-1344d829d445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23496
72286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2349672286
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3923236781
Short name T41
Test name
Test status
Simulation time 624509481 ps
CPU time 37.07 seconds
Started May 30 01:19:20 PM PDT 24
Finished May 30 01:19:59 PM PDT 24
Peak memory 255904 kb
Host smart-cd5b0ac5-217c-4394-b4d9-308ece179c9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39232
36781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3923236781
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.1704662713
Short name T232
Test name
Test status
Simulation time 13878197619 ps
CPU time 1001.24 seconds
Started May 30 01:19:34 PM PDT 24
Finished May 30 01:36:16 PM PDT 24
Peak memory 283916 kb
Host smart-91ba6e5b-cd2a-4bd9-ba8c-65e7f9440d65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704662713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1704662713
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.2202796231
Short name T570
Test name
Test status
Simulation time 17772895516 ps
CPU time 1605.92 seconds
Started May 30 01:19:32 PM PDT 24
Finished May 30 01:46:20 PM PDT 24
Peak memory 289328 kb
Host smart-2c246448-825e-44fc-b9de-f626a1720ca8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202796231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.2202796231
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.291996796
Short name T40
Test name
Test status
Simulation time 232050516 ps
CPU time 22.08 seconds
Started May 30 01:19:27 PM PDT 24
Finished May 30 01:19:50 PM PDT 24
Peak memory 248740 kb
Host smart-af5ec38c-b48f-4e2f-8ed8-8f1752edd0af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29199
6796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.291996796
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.3780993186
Short name T54
Test name
Test status
Simulation time 2434363847 ps
CPU time 37.28 seconds
Started May 30 01:19:19 PM PDT 24
Finished May 30 01:19:58 PM PDT 24
Peak memory 248256 kb
Host smart-efdbf507-8071-4f62-add1-3222a972b97a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37809
93186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3780993186
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.142211697
Short name T33
Test name
Test status
Simulation time 842455776 ps
CPU time 12.76 seconds
Started May 30 01:19:31 PM PDT 24
Finished May 30 01:19:45 PM PDT 24
Peak memory 269556 kb
Host smart-bcf33b6c-245b-4865-811b-80a05054d220
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=142211697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.142211697
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2855070967
Short name T108
Test name
Test status
Simulation time 782153956 ps
CPU time 22.5 seconds
Started May 30 01:19:35 PM PDT 24
Finished May 30 01:19:59 PM PDT 24
Peak memory 248716 kb
Host smart-b5630fd0-8077-4830-992a-5871ac5b44c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28550
70967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2855070967
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.4238288253
Short name T706
Test name
Test status
Simulation time 3576340270 ps
CPU time 55.93 seconds
Started May 30 01:19:21 PM PDT 24
Finished May 30 01:20:19 PM PDT 24
Peak memory 248808 kb
Host smart-571ac598-7169-4df7-b539-0bea637a1299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42382
88253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.4238288253
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.4221837199
Short name T99
Test name
Test status
Simulation time 182249277709 ps
CPU time 2846.68 seconds
Started May 30 01:19:32 PM PDT 24
Finished May 30 02:07:00 PM PDT 24
Peak memory 289544 kb
Host smart-f9f68c68-8f47-4083-a29c-d5058e85afc9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221837199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.4221837199
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.4057248613
Short name T222
Test name
Test status
Simulation time 32088354 ps
CPU time 3.72 seconds
Started May 30 01:20:13 PM PDT 24
Finished May 30 01:20:18 PM PDT 24
Peak memory 248896 kb
Host smart-7fe28d92-2755-4a9b-8411-751ad4df92c1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4057248613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.4057248613
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.3220802083
Short name T47
Test name
Test status
Simulation time 30115559705 ps
CPU time 900.05 seconds
Started May 30 01:19:58 PM PDT 24
Finished May 30 01:34:59 PM PDT 24
Peak memory 267384 kb
Host smart-6648d4b5-b958-436a-a469-27a8e64ac417
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220802083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3220802083
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2814490412
Short name T460
Test name
Test status
Simulation time 191417590 ps
CPU time 10.38 seconds
Started May 30 01:20:09 PM PDT 24
Finished May 30 01:20:20 PM PDT 24
Peak memory 248752 kb
Host smart-67af40c0-4a57-485d-8bef-b535242e357b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2814490412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2814490412
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2331119084
Short name T46
Test name
Test status
Simulation time 3150670321 ps
CPU time 85.54 seconds
Started May 30 01:19:59 PM PDT 24
Finished May 30 01:21:26 PM PDT 24
Peak memory 256952 kb
Host smart-c297b677-2c78-4be7-9cc5-3ef2465332b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23311
19084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2331119084
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.3990128631
Short name T482
Test name
Test status
Simulation time 4825169608 ps
CPU time 18.68 seconds
Started May 30 01:19:58 PM PDT 24
Finished May 30 01:20:18 PM PDT 24
Peak memory 248884 kb
Host smart-7334ef2e-6b8d-4f03-97e8-34b05904031c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39901
28631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3990128631
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.1402165512
Short name T318
Test name
Test status
Simulation time 153429006247 ps
CPU time 2731.84 seconds
Started May 30 01:19:58 PM PDT 24
Finished May 30 02:05:31 PM PDT 24
Peak memory 289116 kb
Host smart-201f3737-1dbe-42aa-998f-b662c0704219
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402165512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1402165512
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.4102819448
Short name T650
Test name
Test status
Simulation time 22254839042 ps
CPU time 1563.39 seconds
Started May 30 01:19:59 PM PDT 24
Finished May 30 01:46:04 PM PDT 24
Peak memory 272960 kb
Host smart-80bab483-f17f-40ca-bde3-5b374f93884f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102819448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.4102819448
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3124628362
Short name T552
Test name
Test status
Simulation time 1776185365 ps
CPU time 36.87 seconds
Started May 30 01:19:58 PM PDT 24
Finished May 30 01:20:36 PM PDT 24
Peak memory 248780 kb
Host smart-e2d7c62c-b2cb-4c48-8208-0a9024b72b37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31246
28362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3124628362
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.1297928592
Short name T536
Test name
Test status
Simulation time 3762567853 ps
CPU time 51.42 seconds
Started May 30 01:19:59 PM PDT 24
Finished May 30 01:20:52 PM PDT 24
Peak memory 248828 kb
Host smart-a5b42c3d-49b5-4980-bed8-c905654e7874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12979
28592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1297928592
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.108913033
Short name T262
Test name
Test status
Simulation time 614041835 ps
CPU time 46.73 seconds
Started May 30 01:19:58 PM PDT 24
Finished May 30 01:20:46 PM PDT 24
Peak memory 255548 kb
Host smart-a6627ddf-d60a-4f75-aae6-9d26078f1a8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10891
3033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.108913033
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.316680054
Short name T458
Test name
Test status
Simulation time 651305013 ps
CPU time 40.22 seconds
Started May 30 01:19:56 PM PDT 24
Finished May 30 01:20:37 PM PDT 24
Peak memory 255680 kb
Host smart-6bbbcc92-9cc2-438d-b0cd-2281a5af980a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31668
0054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.316680054
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.486096288
Short name T630
Test name
Test status
Simulation time 54321783966 ps
CPU time 1583.03 seconds
Started May 30 01:20:11 PM PDT 24
Finished May 30 01:46:34 PM PDT 24
Peak memory 269320 kb
Host smart-85665ca0-deed-4ff6-8b60-23d5e785e07f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486096288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.486096288
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.3732355845
Short name T385
Test name
Test status
Simulation time 6552926000 ps
CPU time 172.13 seconds
Started May 30 01:20:11 PM PDT 24
Finished May 30 01:23:04 PM PDT 24
Peak memory 257012 kb
Host smart-7bf4e778-2164-4287-baab-076ef594f2dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37323
55845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3732355845
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.3835951379
Short name T436
Test name
Test status
Simulation time 248066361 ps
CPU time 10.16 seconds
Started May 30 01:20:14 PM PDT 24
Finished May 30 01:20:25 PM PDT 24
Peak memory 254696 kb
Host smart-e1361f85-3bfc-401a-b8f3-58d59c85e5d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38359
51379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3835951379
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1958190805
Short name T334
Test name
Test status
Simulation time 28365042158 ps
CPU time 1518.81 seconds
Started May 30 01:20:17 PM PDT 24
Finished May 30 01:45:37 PM PDT 24
Peak memory 265200 kb
Host smart-67e1d955-1887-40d0-ac0c-5bb758b35034
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958190805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1958190805
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.1543925866
Short name T375
Test name
Test status
Simulation time 91264034841 ps
CPU time 1518.87 seconds
Started May 30 01:20:11 PM PDT 24
Finished May 30 01:45:31 PM PDT 24
Peak memory 273456 kb
Host smart-f80b03b0-5d0d-4302-8a6a-60d29710b451
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543925866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1543925866
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1279847073
Short name T360
Test name
Test status
Simulation time 322071351 ps
CPU time 14.4 seconds
Started May 30 01:20:17 PM PDT 24
Finished May 30 01:20:33 PM PDT 24
Peak memory 255976 kb
Host smart-a9408dc0-50eb-4a1f-a391-4987f1f218d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12798
47073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1279847073
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2544621389
Short name T564
Test name
Test status
Simulation time 2515488004 ps
CPU time 37.69 seconds
Started May 30 01:20:13 PM PDT 24
Finished May 30 01:20:51 PM PDT 24
Peak memory 248828 kb
Host smart-9186b439-0ad5-4995-b68c-0272d4b369b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25446
21389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2544621389
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.4104511225
Short name T499
Test name
Test status
Simulation time 16363848 ps
CPU time 2.74 seconds
Started May 30 01:20:16 PM PDT 24
Finished May 30 01:20:20 PM PDT 24
Peak memory 240580 kb
Host smart-e936766f-6429-4e3a-9c4b-31ec6edec21e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41045
11225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.4104511225
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.2186938020
Short name T242
Test name
Test status
Simulation time 123256751796 ps
CPU time 3596.16 seconds
Started May 30 01:20:09 PM PDT 24
Finished May 30 02:20:06 PM PDT 24
Peak memory 289200 kb
Host smart-c433cb8a-d3cf-43f4-944d-f1209383575e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186938020 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.2186938020
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1943640340
Short name T214
Test name
Test status
Simulation time 113767790 ps
CPU time 3.04 seconds
Started May 30 01:20:10 PM PDT 24
Finished May 30 01:20:14 PM PDT 24
Peak memory 248908 kb
Host smart-72169aa5-77fa-4967-9131-243bfef6c8be
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1943640340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1943640340
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3709707629
Short name T56
Test name
Test status
Simulation time 29440847073 ps
CPU time 2044.74 seconds
Started May 30 01:20:14 PM PDT 24
Finished May 30 01:54:20 PM PDT 24
Peak memory 281600 kb
Host smart-b2861d6d-fe75-488f-9843-536f6b8fd272
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709707629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3709707629
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3916193487
Short name T60
Test name
Test status
Simulation time 495536635 ps
CPU time 23.5 seconds
Started May 30 01:20:13 PM PDT 24
Finished May 30 01:20:38 PM PDT 24
Peak memory 248748 kb
Host smart-89b4347e-9ca9-4626-9c36-288e67d6ce6a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3916193487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3916193487
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.1231844796
Short name T395
Test name
Test status
Simulation time 1379227947 ps
CPU time 88.18 seconds
Started May 30 01:20:13 PM PDT 24
Finished May 30 01:21:43 PM PDT 24
Peak memory 256680 kb
Host smart-59231d16-b5aa-4929-97d0-fb9ec6a4b17f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12318
44796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1231844796
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.1339145016
Short name T698
Test name
Test status
Simulation time 174344583 ps
CPU time 12.15 seconds
Started May 30 01:20:10 PM PDT 24
Finished May 30 01:20:23 PM PDT 24
Peak memory 253128 kb
Host smart-0be9b84f-df67-49dc-b03a-96a4ef7d9ed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13391
45016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1339145016
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2585218714
Short name T496
Test name
Test status
Simulation time 23028131722 ps
CPU time 513.98 seconds
Started May 30 01:20:11 PM PDT 24
Finished May 30 01:28:46 PM PDT 24
Peak memory 273368 kb
Host smart-1c04a3fb-7190-4995-8d4e-eccad717744d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585218714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2585218714
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.1742588506
Short name T693
Test name
Test status
Simulation time 14639332819 ps
CPU time 184.76 seconds
Started May 30 01:20:14 PM PDT 24
Finished May 30 01:23:20 PM PDT 24
Peak memory 248156 kb
Host smart-34468fb7-6bad-4334-91f8-e46f3e8e56cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742588506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1742588506
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.687186335
Short name T361
Test name
Test status
Simulation time 102099168 ps
CPU time 11.11 seconds
Started May 30 01:20:10 PM PDT 24
Finished May 30 01:20:22 PM PDT 24
Peak memory 248716 kb
Host smart-9582ef18-166d-4c45-9201-1bac611d9b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68718
6335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.687186335
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1626431799
Short name T610
Test name
Test status
Simulation time 932976543 ps
CPU time 56.75 seconds
Started May 30 01:20:17 PM PDT 24
Finished May 30 01:21:15 PM PDT 24
Peak memory 248756 kb
Host smart-99aed1c3-171b-4172-af92-7429ed70edce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16264
31799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1626431799
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.2324925932
Short name T503
Test name
Test status
Simulation time 48366942 ps
CPU time 4.58 seconds
Started May 30 01:20:11 PM PDT 24
Finished May 30 01:20:17 PM PDT 24
Peak memory 239256 kb
Host smart-7ebe4849-261c-426d-af17-af5a8b2577de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23249
25932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.2324925932
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2141114894
Short name T634
Test name
Test status
Simulation time 1134349279 ps
CPU time 36.8 seconds
Started May 30 01:20:11 PM PDT 24
Finished May 30 01:20:48 PM PDT 24
Peak memory 256176 kb
Host smart-4f32c7da-e35b-4b17-aa1c-722dc20078da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21411
14894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2141114894
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.2811885646
Short name T394
Test name
Test status
Simulation time 3452913575 ps
CPU time 89.58 seconds
Started May 30 01:20:12 PM PDT 24
Finished May 30 01:21:43 PM PDT 24
Peak memory 255556 kb
Host smart-67a70e06-d63b-4d84-8f7f-09a2e0434075
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811885646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.2811885646
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.1387860981
Short name T208
Test name
Test status
Simulation time 43369228 ps
CPU time 3.94 seconds
Started May 30 01:20:15 PM PDT 24
Finished May 30 01:20:20 PM PDT 24
Peak memory 248896 kb
Host smart-79fdcdaa-654c-41f2-befb-ea3c5ada029f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1387860981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.1387860981
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2211300714
Short name T12
Test name
Test status
Simulation time 197820887334 ps
CPU time 1140.86 seconds
Started May 30 01:20:12 PM PDT 24
Finished May 30 01:39:14 PM PDT 24
Peak memory 289024 kb
Host smart-fca71e77-934c-4b17-aefc-057bc012b54d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211300714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2211300714
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1249846726
Short name T419
Test name
Test status
Simulation time 735343376 ps
CPU time 11.39 seconds
Started May 30 01:20:10 PM PDT 24
Finished May 30 01:20:22 PM PDT 24
Peak memory 248680 kb
Host smart-d0e61652-5ef4-4e28-b3f6-34dd69a4eeed
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1249846726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1249846726
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3441925520
Short name T280
Test name
Test status
Simulation time 7105770073 ps
CPU time 131.67 seconds
Started May 30 01:20:11 PM PDT 24
Finished May 30 01:22:24 PM PDT 24
Peak memory 250308 kb
Host smart-2e32685b-df07-4b0a-a51a-ae81d80a1fd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34419
25520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3441925520
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.785199215
Short name T700
Test name
Test status
Simulation time 2233581475 ps
CPU time 16.61 seconds
Started May 30 01:20:12 PM PDT 24
Finished May 30 01:20:29 PM PDT 24
Peak memory 248712 kb
Host smart-fe6adff1-2a88-48ca-8dba-baea6767ff02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78519
9215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.785199215
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2998139657
Short name T324
Test name
Test status
Simulation time 191234697128 ps
CPU time 2740.32 seconds
Started May 30 01:20:15 PM PDT 24
Finished May 30 02:05:57 PM PDT 24
Peak memory 281620 kb
Host smart-f22ece5b-b3d4-469c-8331-9ebe500035ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998139657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2998139657
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.4259774434
Short name T390
Test name
Test status
Simulation time 1793433804 ps
CPU time 38.46 seconds
Started May 30 01:20:14 PM PDT 24
Finished May 30 01:20:54 PM PDT 24
Peak memory 256688 kb
Host smart-33e40321-852f-42a8-8635-8b7c2a3d99b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42597
74434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.4259774434
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.1444765646
Short name T579
Test name
Test status
Simulation time 755070904 ps
CPU time 12.85 seconds
Started May 30 01:20:11 PM PDT 24
Finished May 30 01:20:25 PM PDT 24
Peak memory 252000 kb
Host smart-87ce5acb-1186-40e3-880b-139a6126dd81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14447
65646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1444765646
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3542642440
Short name T481
Test name
Test status
Simulation time 2794568033 ps
CPU time 39.15 seconds
Started May 30 01:20:13 PM PDT 24
Finished May 30 01:20:53 PM PDT 24
Peak memory 255596 kb
Host smart-f68c3774-e8c1-4741-8621-720a76dba2e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35426
42440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3542642440
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1322661401
Short name T546
Test name
Test status
Simulation time 119946545 ps
CPU time 7.97 seconds
Started May 30 01:20:13 PM PDT 24
Finished May 30 01:20:22 PM PDT 24
Peak memory 248768 kb
Host smart-c6b92034-9aab-4427-ac6f-18ec48be0bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13226
61401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1322661401
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3972959076
Short name T651
Test name
Test status
Simulation time 64312116013 ps
CPU time 3019.58 seconds
Started May 30 01:20:11 PM PDT 24
Finished May 30 02:10:32 PM PDT 24
Peak memory 289020 kb
Host smart-a03bcc73-f3c7-42a1-9441-020ea192de4d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972959076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3972959076
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.133400684
Short name T92
Test name
Test status
Simulation time 7705361379 ps
CPU time 795.12 seconds
Started May 30 01:20:15 PM PDT 24
Finished May 30 01:33:31 PM PDT 24
Peak memory 283132 kb
Host smart-d5f7ac98-f407-4432-8c1b-09746bed4406
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133400684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.133400684
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.3689197247
Short name T495
Test name
Test status
Simulation time 4160761248 ps
CPU time 81.41 seconds
Started May 30 01:20:14 PM PDT 24
Finished May 30 01:21:36 PM PDT 24
Peak memory 248804 kb
Host smart-ee7f9827-f3c6-4280-9b63-200e81115923
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3689197247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3689197247
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.754947663
Short name T414
Test name
Test status
Simulation time 1504103268 ps
CPU time 156.81 seconds
Started May 30 01:20:13 PM PDT 24
Finished May 30 01:22:51 PM PDT 24
Peak memory 249988 kb
Host smart-a2fbaa65-dd2f-40a4-a573-887ba5f86ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75494
7663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.754947663
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.1785394550
Short name T67
Test name
Test status
Simulation time 451844769 ps
CPU time 32.72 seconds
Started May 30 01:20:11 PM PDT 24
Finished May 30 01:20:45 PM PDT 24
Peak memory 254904 kb
Host smart-580f35f7-f776-49e8-81a7-e66194cf440b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17853
94550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1785394550
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.461007999
Short name T407
Test name
Test status
Simulation time 38584925886 ps
CPU time 1082.19 seconds
Started May 30 01:20:18 PM PDT 24
Finished May 30 01:38:22 PM PDT 24
Peak memory 288648 kb
Host smart-a403d0f8-f029-4227-9bd7-478aab159630
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461007999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.461007999
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.2168628983
Short name T622
Test name
Test status
Simulation time 21325062940 ps
CPU time 247.58 seconds
Started May 30 01:20:13 PM PDT 24
Finished May 30 01:24:21 PM PDT 24
Peak memory 248020 kb
Host smart-2cd5a4ed-6731-4543-baab-b2e0625f2ea2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168628983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.2168628983
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.942129774
Short name T455
Test name
Test status
Simulation time 335503591 ps
CPU time 4.86 seconds
Started May 30 01:20:13 PM PDT 24
Finished May 30 01:20:19 PM PDT 24
Peak memory 239116 kb
Host smart-dffb478e-8baf-4ba9-94fe-886d57c6a1e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94212
9774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.942129774
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.2761939787
Short name T20
Test name
Test status
Simulation time 171719544 ps
CPU time 21.94 seconds
Started May 30 01:20:15 PM PDT 24
Finished May 30 01:20:38 PM PDT 24
Peak memory 247652 kb
Host smart-75123bc4-0456-46bc-8f6a-3b12ccf096a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27619
39787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2761939787
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.529398810
Short name T490
Test name
Test status
Simulation time 155724612 ps
CPU time 4.1 seconds
Started May 30 01:20:13 PM PDT 24
Finished May 30 01:20:18 PM PDT 24
Peak memory 240528 kb
Host smart-249610f3-d2e2-4a1a-982b-0bf70dc60fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52939
8810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.529398810
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.811212023
Short name T583
Test name
Test status
Simulation time 4333047899 ps
CPU time 367.86 seconds
Started May 30 01:20:16 PM PDT 24
Finished May 30 01:26:25 PM PDT 24
Peak memory 266180 kb
Host smart-429e2f7f-e0b1-4a65-bfb2-18f276182a02
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811212023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_han
dler_stress_all.811212023
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3321670670
Short name T219
Test name
Test status
Simulation time 470253882 ps
CPU time 3.36 seconds
Started May 30 01:20:21 PM PDT 24
Finished May 30 01:20:25 PM PDT 24
Peak memory 248932 kb
Host smart-5ef66071-e3c6-4a0f-805f-9d63e24b9001
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3321670670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3321670670
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3078108326
Short name T664
Test name
Test status
Simulation time 42560703025 ps
CPU time 2015.93 seconds
Started May 30 01:20:16 PM PDT 24
Finished May 30 01:53:53 PM PDT 24
Peak memory 270504 kb
Host smart-1f04b420-660b-4cc1-ba9c-cd00103de380
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078108326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3078108326
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.194044830
Short name T678
Test name
Test status
Simulation time 579226168 ps
CPU time 15.67 seconds
Started May 30 01:20:19 PM PDT 24
Finished May 30 01:20:36 PM PDT 24
Peak memory 248796 kb
Host smart-1f4db988-ed84-42fc-bd51-3eb3019975d3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=194044830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.194044830
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.134053251
Short name T281
Test name
Test status
Simulation time 18685251572 ps
CPU time 124.46 seconds
Started May 30 01:20:14 PM PDT 24
Finished May 30 01:22:20 PM PDT 24
Peak memory 257020 kb
Host smart-14bf5a23-88f8-46a0-9362-e91c5cec39f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13405
3251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.134053251
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1761876903
Short name T420
Test name
Test status
Simulation time 1324296093 ps
CPU time 32.39 seconds
Started May 30 01:20:21 PM PDT 24
Finished May 30 01:20:54 PM PDT 24
Peak memory 255964 kb
Host smart-0f97b3c9-6b35-4677-8493-e67208d414e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17618
76903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1761876903
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3052776717
Short name T337
Test name
Test status
Simulation time 193492305769 ps
CPU time 1714.03 seconds
Started May 30 01:20:18 PM PDT 24
Finished May 30 01:48:53 PM PDT 24
Peak memory 268288 kb
Host smart-1b19d56c-f7a0-471f-8203-bb7a60ff3052
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052776717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3052776717
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2052080029
Short name T61
Test name
Test status
Simulation time 23368190021 ps
CPU time 1356.96 seconds
Started May 30 01:20:13 PM PDT 24
Finished May 30 01:42:52 PM PDT 24
Peak memory 269608 kb
Host smart-d5387b75-9d92-4b4f-82bf-1a915c13b92e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052080029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2052080029
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.963536510
Short name T692
Test name
Test status
Simulation time 7959677777 ps
CPU time 198.7 seconds
Started May 30 01:20:13 PM PDT 24
Finished May 30 01:23:33 PM PDT 24
Peak memory 254900 kb
Host smart-2308972c-0c01-4441-9d99-70bdb2b98d27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963536510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.963536510
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.167748153
Short name T500
Test name
Test status
Simulation time 310286728 ps
CPU time 21.83 seconds
Started May 30 01:20:14 PM PDT 24
Finished May 30 01:20:37 PM PDT 24
Peak memory 248208 kb
Host smart-4e54bdb5-b514-47c7-a2da-709635a330fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16774
8153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.167748153
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.2256283141
Short name T389
Test name
Test status
Simulation time 1399409130 ps
CPU time 18.83 seconds
Started May 30 01:20:15 PM PDT 24
Finished May 30 01:20:35 PM PDT 24
Peak memory 253940 kb
Host smart-78e4f386-97b1-4396-9dcb-8156752d2bd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22562
83141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2256283141
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.3595457614
Short name T472
Test name
Test status
Simulation time 128639075 ps
CPU time 14.19 seconds
Started May 30 01:20:15 PM PDT 24
Finished May 30 01:20:30 PM PDT 24
Peak memory 255632 kb
Host smart-db3fe3bf-184e-4627-8254-9541fa157cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35954
57614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3595457614
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.211221216
Short name T623
Test name
Test status
Simulation time 162941940 ps
CPU time 15.11 seconds
Started May 30 01:20:11 PM PDT 24
Finished May 30 01:20:27 PM PDT 24
Peak memory 255880 kb
Host smart-ffe92bf4-5b1b-40fb-a2c4-ac4ff314220f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21122
1216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.211221216
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2801589894
Short name T639
Test name
Test status
Simulation time 557702060813 ps
CPU time 3894.1 seconds
Started May 30 01:20:18 PM PDT 24
Finished May 30 02:25:14 PM PDT 24
Peak memory 289204 kb
Host smart-da81ddac-fd6a-402b-a617-14b835366d48
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801589894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2801589894
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3082046652
Short name T181
Test name
Test status
Simulation time 89154519877 ps
CPU time 2220.35 seconds
Started May 30 01:20:18 PM PDT 24
Finished May 30 01:57:19 PM PDT 24
Peak memory 305836 kb
Host smart-a6a49531-8625-41de-963f-a5295de48f1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082046652 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3082046652
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3465803186
Short name T217
Test name
Test status
Simulation time 129535350 ps
CPU time 3.34 seconds
Started May 30 01:20:28 PM PDT 24
Finished May 30 01:20:32 PM PDT 24
Peak memory 248912 kb
Host smart-4f52d842-1b91-430a-9565-bfc473d21c79
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3465803186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3465803186
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.886068453
Short name T641
Test name
Test status
Simulation time 14554146477 ps
CPU time 816.2 seconds
Started May 30 01:20:16 PM PDT 24
Finished May 30 01:33:54 PM PDT 24
Peak memory 273344 kb
Host smart-5bd8bf7e-7688-43ff-bb0d-d4f348be78c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886068453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.886068453
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.989572632
Short name T627
Test name
Test status
Simulation time 510878444 ps
CPU time 13.67 seconds
Started May 30 01:20:18 PM PDT 24
Finished May 30 01:20:33 PM PDT 24
Peak memory 240572 kb
Host smart-8c40c938-07c2-4f65-b19d-cddba298111d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=989572632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.989572632
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.264552146
Short name T514
Test name
Test status
Simulation time 1511554817 ps
CPU time 134.89 seconds
Started May 30 01:20:26 PM PDT 24
Finished May 30 01:22:42 PM PDT 24
Peak memory 256064 kb
Host smart-f9fcff47-7d65-45f8-8fa6-ffbec49b83f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26455
2146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.264552146
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.1454052769
Short name T646
Test name
Test status
Simulation time 225331619 ps
CPU time 17.3 seconds
Started May 30 01:20:28 PM PDT 24
Finished May 30 01:20:46 PM PDT 24
Peak memory 248720 kb
Host smart-d2d1d877-4bdc-4933-a677-1075c949f568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14540
52769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1454052769
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.654278155
Short name T331
Test name
Test status
Simulation time 19852796151 ps
CPU time 1192.44 seconds
Started May 30 01:20:26 PM PDT 24
Finished May 30 01:40:19 PM PDT 24
Peak memory 265256 kb
Host smart-17612392-883d-47d6-8ac2-84a8f836e65e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654278155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.654278155
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2021160518
Short name T289
Test name
Test status
Simulation time 52906097616 ps
CPU time 3012.89 seconds
Started May 30 01:20:26 PM PDT 24
Finished May 30 02:10:40 PM PDT 24
Peak memory 289196 kb
Host smart-88681862-b997-4ae2-85d8-09a8b5fe2bea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021160518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2021160518
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3708568270
Short name T4
Test name
Test status
Simulation time 15128309116 ps
CPU time 157.12 seconds
Started May 30 01:20:17 PM PDT 24
Finished May 30 01:22:55 PM PDT 24
Peak memory 248264 kb
Host smart-f7165bd6-55b1-4fa0-a493-044fe0a858d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708568270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3708568270
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.3686518931
Short name T368
Test name
Test status
Simulation time 519881006 ps
CPU time 9.58 seconds
Started May 30 01:20:21 PM PDT 24
Finished May 30 01:20:32 PM PDT 24
Peak memory 248780 kb
Host smart-4f376d3e-866f-404d-bcb4-a18b282f6f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36865
18931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.3686518931
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.546967022
Short name T587
Test name
Test status
Simulation time 798034083 ps
CPU time 58.72 seconds
Started May 30 01:20:16 PM PDT 24
Finished May 30 01:21:16 PM PDT 24
Peak memory 254960 kb
Host smart-e44c372a-ffc2-44d3-b6a4-b60fb13bc855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54696
7022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.546967022
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3622665952
Short name T422
Test name
Test status
Simulation time 1474356720 ps
CPU time 27.07 seconds
Started May 30 01:20:26 PM PDT 24
Finished May 30 01:20:54 PM PDT 24
Peak memory 254152 kb
Host smart-948a6314-0079-4901-9293-814a0bdaf236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36226
65952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3622665952
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.4088142411
Short name T489
Test name
Test status
Simulation time 604856247 ps
CPU time 32.25 seconds
Started May 30 01:20:26 PM PDT 24
Finished May 30 01:20:59 PM PDT 24
Peak memory 256120 kb
Host smart-c37cd122-840b-43cb-9b60-ebceacd6a723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40881
42411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.4088142411
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.3587472515
Short name T673
Test name
Test status
Simulation time 102064245941 ps
CPU time 7412.78 seconds
Started May 30 01:20:19 PM PDT 24
Finished May 30 03:23:54 PM PDT 24
Peak memory 355064 kb
Host smart-9e284337-77da-4875-8c51-c73ad2d8561e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587472515 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.3587472515
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.2086262623
Short name T206
Test name
Test status
Simulation time 20045634 ps
CPU time 2.79 seconds
Started May 30 01:20:12 PM PDT 24
Finished May 30 01:20:16 PM PDT 24
Peak memory 248936 kb
Host smart-7f12a90c-96e5-4e43-b052-6befdf37bf4a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2086262623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2086262623
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.2727099755
Short name T578
Test name
Test status
Simulation time 19552357260 ps
CPU time 1684.27 seconds
Started May 30 01:20:19 PM PDT 24
Finished May 30 01:48:25 PM PDT 24
Peak memory 289388 kb
Host smart-c61e3d21-04ce-46fc-ba54-7eaf88f141f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727099755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2727099755
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1459864283
Short name T540
Test name
Test status
Simulation time 750806903 ps
CPU time 10.87 seconds
Started May 30 01:20:10 PM PDT 24
Finished May 30 01:20:21 PM PDT 24
Peak memory 248748 kb
Host smart-0fd81133-5a4c-402e-b1e9-ccd3c67f3a1c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1459864283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1459864283
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1503466654
Short name T247
Test name
Test status
Simulation time 8029269823 ps
CPU time 212.48 seconds
Started May 30 01:20:13 PM PDT 24
Finished May 30 01:23:46 PM PDT 24
Peak memory 257016 kb
Host smart-d36e4ec6-0d85-4304-a713-ad7da7c449f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15034
66654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1503466654
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2473923092
Short name T383
Test name
Test status
Simulation time 480200253 ps
CPU time 11.38 seconds
Started May 30 01:20:11 PM PDT 24
Finished May 30 01:20:23 PM PDT 24
Peak memory 248836 kb
Host smart-98311f43-f4fa-42e7-85b1-587cdb9b1a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24739
23092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2473923092
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2147388173
Short name T691
Test name
Test status
Simulation time 58424017292 ps
CPU time 1267.13 seconds
Started May 30 01:20:12 PM PDT 24
Finished May 30 01:41:20 PM PDT 24
Peak memory 287092 kb
Host smart-b4c681bd-6322-425c-896f-569741064ce8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147388173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2147388173
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.1743902492
Short name T663
Test name
Test status
Simulation time 58664712245 ps
CPU time 3535.19 seconds
Started May 30 01:20:14 PM PDT 24
Finished May 30 02:19:11 PM PDT 24
Peak memory 289384 kb
Host smart-e7d817c9-2fb9-4c1e-a474-f188d6c167fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743902492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1743902492
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1069756409
Short name T666
Test name
Test status
Simulation time 34391098660 ps
CPU time 354.17 seconds
Started May 30 01:20:15 PM PDT 24
Finished May 30 01:26:10 PM PDT 24
Peak memory 254860 kb
Host smart-e688a870-81d2-4feb-bc07-a7f1a92cf9b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069756409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1069756409
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.233223666
Short name T403
Test name
Test status
Simulation time 31462045 ps
CPU time 3.97 seconds
Started May 30 01:20:17 PM PDT 24
Finished May 30 01:20:22 PM PDT 24
Peak memory 240576 kb
Host smart-a00e9b2f-80ad-41e6-bcac-1569a297dd4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23322
3666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.233223666
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.4244953401
Short name T708
Test name
Test status
Simulation time 1368239742 ps
CPU time 12.95 seconds
Started May 30 01:20:13 PM PDT 24
Finished May 30 01:20:27 PM PDT 24
Peak memory 252984 kb
Host smart-744a47bc-066e-4ab7-86bf-a3e09e1082b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42449
53401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.4244953401
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1986267051
Short name T74
Test name
Test status
Simulation time 606538693 ps
CPU time 18.29 seconds
Started May 30 01:20:13 PM PDT 24
Finished May 30 01:20:33 PM PDT 24
Peak memory 255920 kb
Host smart-a8fb2503-a7c0-4216-a028-28a04ed4df51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19862
67051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1986267051
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.2211151035
Short name T530
Test name
Test status
Simulation time 717891178 ps
CPU time 41.28 seconds
Started May 30 01:20:17 PM PDT 24
Finished May 30 01:21:00 PM PDT 24
Peak memory 255972 kb
Host smart-bc973ff9-fc20-4493-b8c9-52e566a39176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22111
51035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2211151035
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.414181915
Short name T107
Test name
Test status
Simulation time 70961535413 ps
CPU time 1700.19 seconds
Started May 30 01:20:15 PM PDT 24
Finished May 30 01:48:36 PM PDT 24
Peak memory 289784 kb
Host smart-76d26704-5b8b-48ef-a713-c1ca96157611
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414181915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.414181915
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2841467815
Short name T221
Test name
Test status
Simulation time 75172408 ps
CPU time 3.41 seconds
Started May 30 01:20:25 PM PDT 24
Finished May 30 01:20:29 PM PDT 24
Peak memory 248928 kb
Host smart-40f4c6b3-b614-4210-a951-549728a2c775
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2841467815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2841467815
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.686899755
Short name T527
Test name
Test status
Simulation time 177541711865 ps
CPU time 1833.15 seconds
Started May 30 01:20:16 PM PDT 24
Finished May 30 01:50:50 PM PDT 24
Peak memory 272460 kb
Host smart-b90db889-8185-43fa-95d0-fd16987233ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686899755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.686899755
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1574691425
Short name T423
Test name
Test status
Simulation time 631693351 ps
CPU time 27.34 seconds
Started May 30 01:20:15 PM PDT 24
Finished May 30 01:20:44 PM PDT 24
Peak memory 248756 kb
Host smart-b1a6fe82-d641-4808-88be-a41f758fd000
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1574691425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1574691425
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3104073745
Short name T531
Test name
Test status
Simulation time 2932113688 ps
CPU time 57.42 seconds
Started May 30 01:20:15 PM PDT 24
Finished May 30 01:21:14 PM PDT 24
Peak memory 256788 kb
Host smart-95a2f71b-0c50-494a-b881-160df54e31be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31040
73745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3104073745
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.3875188299
Short name T556
Test name
Test status
Simulation time 2095208163 ps
CPU time 34.63 seconds
Started May 30 01:20:15 PM PDT 24
Finished May 30 01:20:51 PM PDT 24
Peak memory 255888 kb
Host smart-aebd8979-e41c-49fc-836d-0aa5416912da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38751
88299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3875188299
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2769800028
Short name T498
Test name
Test status
Simulation time 61052346426 ps
CPU time 1124.1 seconds
Started May 30 01:20:14 PM PDT 24
Finished May 30 01:38:59 PM PDT 24
Peak memory 271700 kb
Host smart-72e4b0ad-6092-4611-ba16-5ef90118099b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769800028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2769800028
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.3512161248
Short name T494
Test name
Test status
Simulation time 5617650030 ps
CPU time 42.23 seconds
Started May 30 01:20:20 PM PDT 24
Finished May 30 01:21:03 PM PDT 24
Peak memory 248776 kb
Host smart-163ef768-6ef0-470c-8c91-64f37a1e8056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35121
61248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3512161248
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1511634621
Short name T101
Test name
Test status
Simulation time 487753628 ps
CPU time 33.93 seconds
Started May 30 01:20:18 PM PDT 24
Finished May 30 01:20:53 PM PDT 24
Peak memory 255988 kb
Host smart-eab46d4c-2495-4f6e-a10c-7cdef180de87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15116
34621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1511634621
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2713608224
Short name T57
Test name
Test status
Simulation time 11172375401 ps
CPU time 43.62 seconds
Started May 30 01:20:15 PM PDT 24
Finished May 30 01:21:00 PM PDT 24
Peak memory 248772 kb
Host smart-4ed54a22-da03-4046-8ed0-85da27e496f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27136
08224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2713608224
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.567206174
Short name T680
Test name
Test status
Simulation time 145174834 ps
CPU time 7.52 seconds
Started May 30 01:20:15 PM PDT 24
Finished May 30 01:20:24 PM PDT 24
Peak memory 248796 kb
Host smart-c325699d-c42a-4d44-99c1-57263a0205e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56720
6174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.567206174
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.1720134353
Short name T163
Test name
Test status
Simulation time 94064312422 ps
CPU time 2948.23 seconds
Started May 30 01:20:34 PM PDT 24
Finished May 30 02:09:44 PM PDT 24
Peak memory 322672 kb
Host smart-82b44ff6-5b08-4a90-a84d-3a1098d48eb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720134353 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.1720134353
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.337961518
Short name T212
Test name
Test status
Simulation time 30959448 ps
CPU time 3.53 seconds
Started May 30 01:20:24 PM PDT 24
Finished May 30 01:20:29 PM PDT 24
Peak memory 248916 kb
Host smart-1e00a86c-64c4-4a60-93ce-20f264a90ca5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=337961518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.337961518
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2284458637
Short name T467
Test name
Test status
Simulation time 123676144097 ps
CPU time 2005.41 seconds
Started May 30 01:20:37 PM PDT 24
Finished May 30 01:54:04 PM PDT 24
Peak memory 287072 kb
Host smart-03aafb77-b593-4bd6-8722-97aefc9333b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284458637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2284458637
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3139752582
Short name T457
Test name
Test status
Simulation time 942181298 ps
CPU time 11.05 seconds
Started May 30 01:20:27 PM PDT 24
Finished May 30 01:20:39 PM PDT 24
Peak memory 248728 kb
Host smart-804fa145-af3e-4214-b150-df24d82050eb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3139752582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3139752582
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1462610977
Short name T94
Test name
Test status
Simulation time 12231563438 ps
CPU time 190.73 seconds
Started May 30 01:20:37 PM PDT 24
Finished May 30 01:23:49 PM PDT 24
Peak memory 256916 kb
Host smart-63bb5036-602c-4ebe-9fbc-920548123f8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14626
10977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1462610977
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3874282760
Short name T624
Test name
Test status
Simulation time 1355578309 ps
CPU time 37.47 seconds
Started May 30 01:20:35 PM PDT 24
Finished May 30 01:21:13 PM PDT 24
Peak memory 248780 kb
Host smart-528c265b-6f14-4d5a-b728-aa20cd5929d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38742
82760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3874282760
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.965491586
Short name T502
Test name
Test status
Simulation time 102411736401 ps
CPU time 1606.22 seconds
Started May 30 01:20:23 PM PDT 24
Finished May 30 01:47:10 PM PDT 24
Peak memory 288636 kb
Host smart-8ba5dc5b-36d4-4ca6-a4f9-156f8c9f8d53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965491586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.965491586
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.150887269
Short name T321
Test name
Test status
Simulation time 220650259270 ps
CPU time 472.86 seconds
Started May 30 01:20:22 PM PDT 24
Finished May 30 01:28:16 PM PDT 24
Peak memory 247876 kb
Host smart-ae82e22c-800b-41cf-ad2f-74cfaaa8fdaf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150887269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.150887269
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.428882982
Short name T505
Test name
Test status
Simulation time 32601792 ps
CPU time 3.65 seconds
Started May 30 01:20:34 PM PDT 24
Finished May 30 01:20:39 PM PDT 24
Peak memory 240580 kb
Host smart-5725f741-4833-40eb-b81a-e68c00dd2dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42888
2982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.428882982
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.1150693152
Short name T432
Test name
Test status
Simulation time 290418396 ps
CPU time 18.5 seconds
Started May 30 01:20:26 PM PDT 24
Finished May 30 01:20:45 PM PDT 24
Peak memory 255148 kb
Host smart-0a2d3a97-35d0-413f-b84e-15a957d4e764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11506
93152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.1150693152
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.60987019
Short name T571
Test name
Test status
Simulation time 1293825326 ps
CPU time 27.7 seconds
Started May 30 01:20:39 PM PDT 24
Finished May 30 01:21:08 PM PDT 24
Peak memory 248732 kb
Host smart-12cc58f4-3910-4b0d-9f3e-bcfc82035a00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60987
019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.60987019
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.1489292741
Short name T596
Test name
Test status
Simulation time 1041582320 ps
CPU time 16.35 seconds
Started May 30 01:20:36 PM PDT 24
Finished May 30 01:20:53 PM PDT 24
Peak memory 248776 kb
Host smart-07735781-5e7f-4d9e-9a16-a089d361fef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14892
92741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1489292741
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3466495708
Short name T39
Test name
Test status
Simulation time 6909181446 ps
CPU time 285.17 seconds
Started May 30 01:20:25 PM PDT 24
Finished May 30 01:25:11 PM PDT 24
Peak memory 256988 kb
Host smart-ee6a8208-a441-48bb-ae30-cb1fa3829b19
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466495708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3466495708
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.3547209155
Short name T209
Test name
Test status
Simulation time 518817480 ps
CPU time 3.61 seconds
Started May 30 01:19:30 PM PDT 24
Finished May 30 01:19:35 PM PDT 24
Peak memory 248908 kb
Host smart-4988db0b-78dd-4ccc-821f-455c560d235d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3547209155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3547209155
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1739572004
Short name T590
Test name
Test status
Simulation time 33394247525 ps
CPU time 1934.35 seconds
Started May 30 01:19:33 PM PDT 24
Finished May 30 01:51:49 PM PDT 24
Peak memory 273372 kb
Host smart-36da7be5-77bb-4845-b7c8-dc5a4a62d13d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739572004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1739572004
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3436728550
Short name T605
Test name
Test status
Simulation time 587885383 ps
CPU time 25.23 seconds
Started May 30 01:19:32 PM PDT 24
Finished May 30 01:19:59 PM PDT 24
Peak memory 240576 kb
Host smart-66c89016-80c2-4ac1-af40-a60431930893
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3436728550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3436728550
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1075618140
Short name T114
Test name
Test status
Simulation time 497263590 ps
CPU time 32.02 seconds
Started May 30 01:19:34 PM PDT 24
Finished May 30 01:20:07 PM PDT 24
Peak memory 255940 kb
Host smart-87a8ae22-91da-49aa-8cbb-af95731effb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10756
18140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1075618140
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.529489238
Short name T534
Test name
Test status
Simulation time 2576759024 ps
CPU time 45.66 seconds
Started May 30 01:19:32 PM PDT 24
Finished May 30 01:20:19 PM PDT 24
Peak memory 255380 kb
Host smart-e08b2516-b589-4119-9d29-f19a5fc7bdde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52948
9238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.529489238
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1465339049
Short name T224
Test name
Test status
Simulation time 7115877218 ps
CPU time 809.58 seconds
Started May 30 01:19:33 PM PDT 24
Finished May 30 01:33:04 PM PDT 24
Peak memory 266284 kb
Host smart-e4bae4e2-cf7d-4915-ba4f-be88797183d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465339049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1465339049
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1653026811
Short name T609
Test name
Test status
Simulation time 7204680258 ps
CPU time 716.51 seconds
Started May 30 01:19:31 PM PDT 24
Finished May 30 01:31:29 PM PDT 24
Peak memory 273376 kb
Host smart-58d79de2-6dc8-4b74-ac5d-7a36e73e4cb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653026811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1653026811
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.4271431877
Short name T316
Test name
Test status
Simulation time 6252317818 ps
CPU time 129.6 seconds
Started May 30 01:19:33 PM PDT 24
Finished May 30 01:21:44 PM PDT 24
Peak memory 253364 kb
Host smart-a63f0615-05c9-401d-a541-a94976212174
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271431877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.4271431877
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.3487531167
Short name T442
Test name
Test status
Simulation time 4950606020 ps
CPU time 70.31 seconds
Started May 30 01:19:31 PM PDT 24
Finished May 30 01:20:43 PM PDT 24
Peak memory 256932 kb
Host smart-ef338c5b-22c4-4c68-9872-01a0b3fe4b83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34875
31167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3487531167
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1716573822
Short name T297
Test name
Test status
Simulation time 527516751 ps
CPU time 17.97 seconds
Started May 30 01:19:32 PM PDT 24
Finished May 30 01:19:52 PM PDT 24
Peak memory 255892 kb
Host smart-3b606543-806e-4b70-a2bd-e243d8b56860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17165
73822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1716573822
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1222221997
Short name T470
Test name
Test status
Simulation time 849950028 ps
CPU time 14.54 seconds
Started May 30 01:19:31 PM PDT 24
Finished May 30 01:19:47 PM PDT 24
Peak memory 248724 kb
Host smart-88f808a6-224d-457f-9a47-4d9b75aeb187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12222
21997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1222221997
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.200887990
Short name T541
Test name
Test status
Simulation time 21062556227 ps
CPU time 198.56 seconds
Started May 30 01:20:27 PM PDT 24
Finished May 30 01:23:46 PM PDT 24
Peak memory 256952 kb
Host smart-48255585-44bf-4228-ab88-6780db0361aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20088
7990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.200887990
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3117585296
Short name T69
Test name
Test status
Simulation time 827252610 ps
CPU time 22.27 seconds
Started May 30 01:20:30 PM PDT 24
Finished May 30 01:20:53 PM PDT 24
Peak memory 254956 kb
Host smart-c958c94e-41a7-4dc7-97e1-7eb544071cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31175
85296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3117585296
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.3194634627
Short name T292
Test name
Test status
Simulation time 22146588763 ps
CPU time 1151.05 seconds
Started May 30 01:20:29 PM PDT 24
Finished May 30 01:39:41 PM PDT 24
Peak memory 271664 kb
Host smart-dc663639-1e28-486f-9452-c16d637732ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194634627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.3194634627
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.1752824979
Short name T480
Test name
Test status
Simulation time 10253621900 ps
CPU time 999.5 seconds
Started May 30 01:20:26 PM PDT 24
Finished May 30 01:37:07 PM PDT 24
Peak memory 288732 kb
Host smart-c76145ec-5405-485a-b36d-1b2232105860
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752824979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.1752824979
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2122227827
Short name T654
Test name
Test status
Simulation time 20630222718 ps
CPU time 204.24 seconds
Started May 30 01:20:30 PM PDT 24
Finished May 30 01:23:55 PM PDT 24
Peak memory 255004 kb
Host smart-ca8fe7dd-edb4-4090-9fef-9f8dc32e0bd5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122227827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2122227827
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.4002502756
Short name T619
Test name
Test status
Simulation time 6552623851 ps
CPU time 46.9 seconds
Started May 30 01:20:25 PM PDT 24
Finished May 30 01:21:12 PM PDT 24
Peak memory 248828 kb
Host smart-e4512db3-f032-4d56-8472-e0ba22a2a01e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40025
02756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.4002502756
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.3332573965
Short name T526
Test name
Test status
Simulation time 1536600271 ps
CPU time 32.78 seconds
Started May 30 01:20:37 PM PDT 24
Finished May 30 01:21:12 PM PDT 24
Peak memory 248736 kb
Host smart-a69edeae-b538-4e13-b861-fb3d7d4683b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33325
73965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3332573965
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1083644937
Short name T474
Test name
Test status
Simulation time 1342908284 ps
CPU time 33.94 seconds
Started May 30 01:20:36 PM PDT 24
Finished May 30 01:21:11 PM PDT 24
Peak memory 248796 kb
Host smart-f6a56f01-9104-4d4e-b51e-d9a737624ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10836
44937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1083644937
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1262816990
Short name T685
Test name
Test status
Simulation time 3588100089 ps
CPU time 58.96 seconds
Started May 30 01:20:27 PM PDT 24
Finished May 30 01:21:27 PM PDT 24
Peak memory 256388 kb
Host smart-a17ca3b1-ff31-4061-993f-2d344086c9c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12628
16990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1262816990
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2962103700
Short name T607
Test name
Test status
Simulation time 1299644606 ps
CPU time 52.18 seconds
Started May 30 01:20:23 PM PDT 24
Finished May 30 01:21:16 PM PDT 24
Peak memory 256392 kb
Host smart-4fcdf749-856f-4485-886c-b4e21f58fe8c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962103700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2962103700
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.1617689743
Short name T19
Test name
Test status
Simulation time 10500826391 ps
CPU time 279.25 seconds
Started May 30 01:20:23 PM PDT 24
Finished May 30 01:25:03 PM PDT 24
Peak memory 250988 kb
Host smart-30573f68-a112-423e-a57a-a5ecb36477d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16176
89743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1617689743
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.497125549
Short name T608
Test name
Test status
Simulation time 610370545 ps
CPU time 11.52 seconds
Started May 30 01:20:33 PM PDT 24
Finished May 30 01:20:45 PM PDT 24
Peak memory 254696 kb
Host smart-12e955d8-0857-45b1-91ba-af72af51c76a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49712
5549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.497125549
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.1498675340
Short name T461
Test name
Test status
Simulation time 30532748862 ps
CPU time 1981.51 seconds
Started May 30 01:20:26 PM PDT 24
Finished May 30 01:53:28 PM PDT 24
Peak memory 283440 kb
Host smart-680a0059-e4ef-4fb9-b3fd-1131b890e429
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498675340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.1498675340
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3650921625
Short name T189
Test name
Test status
Simulation time 7264603336 ps
CPU time 118.15 seconds
Started May 30 01:20:30 PM PDT 24
Finished May 30 01:22:29 PM PDT 24
Peak memory 248228 kb
Host smart-55a39bd1-2ca1-4813-81b1-bda66885da4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650921625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3650921625
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.669483608
Short name T233
Test name
Test status
Simulation time 702414724 ps
CPU time 45.82 seconds
Started May 30 01:20:25 PM PDT 24
Finished May 30 01:21:12 PM PDT 24
Peak memory 248776 kb
Host smart-1b64047e-09a0-4b00-b009-4955697d168a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66948
3608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.669483608
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3219560309
Short name T528
Test name
Test status
Simulation time 662498714 ps
CPU time 16.58 seconds
Started May 30 01:20:24 PM PDT 24
Finished May 30 01:20:41 PM PDT 24
Peak memory 248756 kb
Host smart-d5d17270-1a64-4a8c-9554-7498ed7e1cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32195
60309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3219560309
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1059412651
Short name T270
Test name
Test status
Simulation time 297957330 ps
CPU time 35.51 seconds
Started May 30 01:20:39 PM PDT 24
Finished May 30 01:21:16 PM PDT 24
Peak memory 256452 kb
Host smart-3835400f-0c35-4a19-a496-3288d743eac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10594
12651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1059412651
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2071429143
Short name T576
Test name
Test status
Simulation time 1782631146 ps
CPU time 24.16 seconds
Started May 30 01:20:35 PM PDT 24
Finished May 30 01:21:00 PM PDT 24
Peak memory 256928 kb
Host smart-c1885059-ad3f-4a4c-a1d7-d3a2caf87ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20714
29143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2071429143
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1408350768
Short name T55
Test name
Test status
Simulation time 72009269700 ps
CPU time 4237.81 seconds
Started May 30 01:20:26 PM PDT 24
Finished May 30 02:31:05 PM PDT 24
Peak memory 297880 kb
Host smart-d6288f21-0ca6-4831-9bdc-411fe4ef2cd7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408350768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1408350768
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.4169593214
Short name T87
Test name
Test status
Simulation time 1259256137408 ps
CPU time 8450.58 seconds
Started May 30 01:20:27 PM PDT 24
Finished May 30 03:41:20 PM PDT 24
Peak memory 371372 kb
Host smart-62e2f590-15e1-411b-9d54-7e56cab7c4e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169593214 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.4169593214
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1168643590
Short name T652
Test name
Test status
Simulation time 33691265927 ps
CPU time 2087.31 seconds
Started May 30 01:20:28 PM PDT 24
Finished May 30 01:55:16 PM PDT 24
Peak memory 289708 kb
Host smart-e9891dcd-6bb0-4e82-ad53-bcd1b80a2808
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168643590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1168643590
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.1129049752
Short name T683
Test name
Test status
Simulation time 1843594330 ps
CPU time 131.78 seconds
Started May 30 01:20:36 PM PDT 24
Finished May 30 01:22:50 PM PDT 24
Peak memory 256876 kb
Host smart-40f67cb6-4829-44ff-9cff-ccafd56e91f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11290
49752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1129049752
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.1524071128
Short name T711
Test name
Test status
Simulation time 755153680 ps
CPU time 24.68 seconds
Started May 30 01:20:39 PM PDT 24
Finished May 30 01:21:05 PM PDT 24
Peak memory 255540 kb
Host smart-455c16c8-0fe7-4351-91a5-a7cddcc57be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15240
71128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.1524071128
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.4144611260
Short name T106
Test name
Test status
Simulation time 165776002176 ps
CPU time 2457.98 seconds
Started May 30 01:20:38 PM PDT 24
Finished May 30 02:01:38 PM PDT 24
Peak memory 289108 kb
Host smart-c7d918b8-c4f4-4112-86de-cb6ba17732f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144611260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.4144611260
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3689064633
Short name T197
Test name
Test status
Simulation time 32480215198 ps
CPU time 270.25 seconds
Started May 30 01:20:40 PM PDT 24
Finished May 30 01:25:11 PM PDT 24
Peak memory 254792 kb
Host smart-01030a93-2cef-4f39-855c-029772dd0024
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689064633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3689064633
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.1244561631
Short name T555
Test name
Test status
Simulation time 66737933 ps
CPU time 5.47 seconds
Started May 30 01:20:27 PM PDT 24
Finished May 30 01:20:33 PM PDT 24
Peak memory 248732 kb
Host smart-90a97877-d192-426a-91a9-52ea6412d0f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12445
61631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1244561631
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.342217133
Short name T72
Test name
Test status
Simulation time 352224938 ps
CPU time 32.7 seconds
Started May 30 01:20:36 PM PDT 24
Finished May 30 01:21:09 PM PDT 24
Peak memory 248776 kb
Host smart-fcff4a34-5007-474e-990b-a42a8920599c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34221
7133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.342217133
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1172372649
Short name T187
Test name
Test status
Simulation time 4341467431 ps
CPU time 58.09 seconds
Started May 30 01:20:36 PM PDT 24
Finished May 30 01:21:35 PM PDT 24
Peak memory 256340 kb
Host smart-5efc4fd1-8641-4d2a-b437-bb9ce5520d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11723
72649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1172372649
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.677503288
Short name T618
Test name
Test status
Simulation time 401167874 ps
CPU time 34.78 seconds
Started May 30 01:20:36 PM PDT 24
Finished May 30 01:21:12 PM PDT 24
Peak memory 248760 kb
Host smart-182d7b46-5d59-463a-b14c-08a17e7a7cbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67750
3288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.677503288
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.2020855289
Short name T100
Test name
Test status
Simulation time 251655943207 ps
CPU time 2465.52 seconds
Started May 30 01:20:36 PM PDT 24
Finished May 30 02:01:43 PM PDT 24
Peak memory 289380 kb
Host smart-4b3e6fd6-6896-4c48-ae47-071ce9a9389e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020855289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.2020855289
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.3328899794
Short name T295
Test name
Test status
Simulation time 14506637267 ps
CPU time 1320.31 seconds
Started May 30 01:20:39 PM PDT 24
Finished May 30 01:42:41 PM PDT 24
Peak memory 288312 kb
Host smart-e94d4629-0b22-4ccb-a675-666fa0cd1774
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328899794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.3328899794
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.2813592612
Short name T476
Test name
Test status
Simulation time 2280204112 ps
CPU time 136.64 seconds
Started May 30 01:20:38 PM PDT 24
Finished May 30 01:22:56 PM PDT 24
Peak memory 256936 kb
Host smart-73dc845c-4385-4b94-afa3-963e3a2460cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28135
92612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2813592612
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.4186887021
Short name T387
Test name
Test status
Simulation time 244419646 ps
CPU time 15.47 seconds
Started May 30 01:20:37 PM PDT 24
Finished May 30 01:20:54 PM PDT 24
Peak memory 248948 kb
Host smart-3a29d4e8-a880-4403-b21a-6ad9100656e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41868
87021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.4186887021
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3239596051
Short name T329
Test name
Test status
Simulation time 64445773533 ps
CPU time 1374.08 seconds
Started May 30 01:20:38 PM PDT 24
Finished May 30 01:43:34 PM PDT 24
Peak memory 284456 kb
Host smart-036d71d0-43c1-4230-916b-5a103e341c0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239596051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3239596051
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2836601362
Short name T509
Test name
Test status
Simulation time 151360681188 ps
CPU time 1476.68 seconds
Started May 30 01:20:39 PM PDT 24
Finished May 30 01:45:17 PM PDT 24
Peak memory 288816 kb
Host smart-df55b203-e703-4297-9614-5212738a3a3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836601362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2836601362
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3611299586
Short name T452
Test name
Test status
Simulation time 5242268409 ps
CPU time 110.78 seconds
Started May 30 01:20:44 PM PDT 24
Finished May 30 01:22:35 PM PDT 24
Peak memory 248268 kb
Host smart-f539475c-b601-4627-be8a-595eab9a2384
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611299586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3611299586
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.2680309511
Short name T369
Test name
Test status
Simulation time 3258529964 ps
CPU time 19.69 seconds
Started May 30 01:20:38 PM PDT 24
Finished May 30 01:21:00 PM PDT 24
Peak memory 248812 kb
Host smart-3e7af052-8b8a-446e-90f1-afbb96593d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26803
09511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2680309511
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.114935450
Short name T273
Test name
Test status
Simulation time 7343790295 ps
CPU time 45.85 seconds
Started May 30 01:20:40 PM PDT 24
Finished May 30 01:21:27 PM PDT 24
Peak memory 248832 kb
Host smart-292b8950-e0fa-406b-ada1-ac4c3876e25a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11493
5450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.114935450
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2921147025
Short name T62
Test name
Test status
Simulation time 149993797 ps
CPU time 17.41 seconds
Started May 30 01:20:38 PM PDT 24
Finished May 30 01:20:57 PM PDT 24
Peak memory 255804 kb
Host smart-5dc0c61b-228f-4809-b6c9-bed33af427a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29211
47025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2921147025
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.2066859463
Short name T441
Test name
Test status
Simulation time 396641908 ps
CPU time 14.62 seconds
Started May 30 01:20:39 PM PDT 24
Finished May 30 01:20:55 PM PDT 24
Peak memory 254148 kb
Host smart-b094c500-5375-4835-80ac-e24334b233b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20668
59463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2066859463
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1146618236
Short name T267
Test name
Test status
Simulation time 65384575149 ps
CPU time 2434.62 seconds
Started May 30 01:20:38 PM PDT 24
Finished May 30 02:01:15 PM PDT 24
Peak memory 289008 kb
Host smart-a435b306-2d94-4694-8e75-62114bc6ea08
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146618236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1146618236
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1327659411
Short name T674
Test name
Test status
Simulation time 26525787799 ps
CPU time 1294.92 seconds
Started May 30 01:20:43 PM PDT 24
Finished May 30 01:42:19 PM PDT 24
Peak memory 267340 kb
Host smart-a140e543-643d-4a94-921e-f56aa3b2e366
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327659411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1327659411
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.91641973
Short name T521
Test name
Test status
Simulation time 1390192804 ps
CPU time 117.94 seconds
Started May 30 01:20:39 PM PDT 24
Finished May 30 01:22:38 PM PDT 24
Peak memory 249748 kb
Host smart-639b2a60-7196-4345-a9c7-2aa2aaa73853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91641
973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.91641973
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1768148483
Short name T409
Test name
Test status
Simulation time 965453279 ps
CPU time 62.58 seconds
Started May 30 01:20:39 PM PDT 24
Finished May 30 01:21:43 PM PDT 24
Peak memory 255576 kb
Host smart-8b3d2832-b666-4144-a4cb-08fdf3c75a8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17681
48483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1768148483
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.4251551839
Short name T429
Test name
Test status
Simulation time 14681342025 ps
CPU time 1471.06 seconds
Started May 30 01:20:38 PM PDT 24
Finished May 30 01:45:11 PM PDT 24
Peak memory 289468 kb
Host smart-c43fb79f-0ab9-47d5-b231-321cb2084d4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251551839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.4251551839
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2440887988
Short name T89
Test name
Test status
Simulation time 28211217870 ps
CPU time 656.26 seconds
Started May 30 01:20:38 PM PDT 24
Finished May 30 01:31:36 PM PDT 24
Peak memory 273096 kb
Host smart-5a2d5758-8677-40ab-a4c1-633ac1533b9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440887988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2440887988
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3024701311
Short name T37
Test name
Test status
Simulation time 20714799221 ps
CPU time 253.43 seconds
Started May 30 01:20:39 PM PDT 24
Finished May 30 01:24:54 PM PDT 24
Peak memory 248240 kb
Host smart-5513ebef-be13-49fd-ac5e-f4fcadc2e43b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024701311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3024701311
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.2111196788
Short name T416
Test name
Test status
Simulation time 1438862372 ps
CPU time 48.12 seconds
Started May 30 01:20:37 PM PDT 24
Finished May 30 01:21:26 PM PDT 24
Peak memory 248812 kb
Host smart-ef879f42-bc2a-4eea-9dc8-78f70d6f6533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21111
96788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2111196788
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2765893931
Short name T456
Test name
Test status
Simulation time 1007058240 ps
CPU time 27.67 seconds
Started May 30 01:20:39 PM PDT 24
Finished May 30 01:21:08 PM PDT 24
Peak memory 255816 kb
Host smart-400316c7-63fd-4446-9623-6709495536e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27658
93931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2765893931
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1845308435
Short name T560
Test name
Test status
Simulation time 482328197 ps
CPU time 9.26 seconds
Started May 30 01:20:39 PM PDT 24
Finished May 30 01:20:50 PM PDT 24
Peak memory 252036 kb
Host smart-3a1027e1-ac2a-472f-9744-281c64bb6575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18453
08435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1845308435
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.2225604319
Short name T381
Test name
Test status
Simulation time 615577539 ps
CPU time 40.99 seconds
Started May 30 01:20:37 PM PDT 24
Finished May 30 01:21:20 PM PDT 24
Peak memory 248880 kb
Host smart-26bcf57e-41d2-422a-9840-d6f4118a5b72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22256
04319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2225604319
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1204673275
Short name T53
Test name
Test status
Simulation time 14459007578 ps
CPU time 219.96 seconds
Started May 30 01:20:39 PM PDT 24
Finished May 30 01:24:20 PM PDT 24
Peak memory 257020 kb
Host smart-ba323398-a1f0-4c50-8ad0-9933456e5a5b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204673275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1204673275
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.1714825030
Short name T486
Test name
Test status
Simulation time 28590425286 ps
CPU time 1630.79 seconds
Started May 30 01:20:48 PM PDT 24
Finished May 30 01:48:00 PM PDT 24
Peak memory 272992 kb
Host smart-146a5e47-5926-4fe4-a678-2763a1883a5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714825030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1714825030
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3002678040
Short name T603
Test name
Test status
Simulation time 257193746 ps
CPU time 9.99 seconds
Started May 30 01:20:51 PM PDT 24
Finished May 30 01:21:02 PM PDT 24
Peak memory 254360 kb
Host smart-b9a900a7-2335-4496-9153-6826473d5887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30026
78040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3002678040
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2417954601
Short name T254
Test name
Test status
Simulation time 307320834 ps
CPU time 33.56 seconds
Started May 30 01:20:51 PM PDT 24
Finished May 30 01:21:26 PM PDT 24
Peak memory 255908 kb
Host smart-549d0afb-5504-41ef-92f4-c0fca222ad03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24179
54601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2417954601
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3532210959
Short name T611
Test name
Test status
Simulation time 11035214761 ps
CPU time 921.76 seconds
Started May 30 01:20:52 PM PDT 24
Finished May 30 01:36:15 PM PDT 24
Peak memory 272572 kb
Host smart-7301dfa3-a4c2-4ffe-8175-51ebce2de866
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532210959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3532210959
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.2090580080
Short name T697
Test name
Test status
Simulation time 117400695519 ps
CPU time 1984.51 seconds
Started May 30 01:20:58 PM PDT 24
Finished May 30 01:54:03 PM PDT 24
Peak memory 281176 kb
Host smart-14e69edf-eca8-48fe-b26b-5542dee52539
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090580080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2090580080
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3333509256
Short name T319
Test name
Test status
Simulation time 24235305471 ps
CPU time 253.23 seconds
Started May 30 01:20:51 PM PDT 24
Finished May 30 01:25:05 PM PDT 24
Peak memory 248192 kb
Host smart-3c900495-7aa4-42d7-9a94-962a5b59e868
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333509256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3333509256
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1570787432
Short name T50
Test name
Test status
Simulation time 783112452 ps
CPU time 23.89 seconds
Started May 30 01:20:52 PM PDT 24
Finished May 30 01:21:17 PM PDT 24
Peak memory 249020 kb
Host smart-fa566bc1-d985-4db1-a528-c22496f6fa96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15707
87432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1570787432
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.625531099
Short name T109
Test name
Test status
Simulation time 675039444 ps
CPU time 33.47 seconds
Started May 30 01:20:49 PM PDT 24
Finished May 30 01:21:23 PM PDT 24
Peak memory 248888 kb
Host smart-4d1e8f29-c4e0-4255-ad0d-9ff9cf13468e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62553
1099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.625531099
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.2047199481
Short name T592
Test name
Test status
Simulation time 86448491 ps
CPU time 3.91 seconds
Started May 30 01:20:59 PM PDT 24
Finished May 30 01:21:03 PM PDT 24
Peak memory 239224 kb
Host smart-8c671750-c2b2-4739-ae6f-906992de314f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20471
99481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2047199481
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3137931948
Short name T682
Test name
Test status
Simulation time 257377445 ps
CPU time 26.86 seconds
Started May 30 01:20:40 PM PDT 24
Finished May 30 01:21:08 PM PDT 24
Peak memory 255988 kb
Host smart-486c0a2d-d493-4019-be39-1d08ac82d5dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31379
31948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3137931948
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.258504564
Short name T485
Test name
Test status
Simulation time 1533585404 ps
CPU time 114.7 seconds
Started May 30 01:20:52 PM PDT 24
Finished May 30 01:22:48 PM PDT 24
Peak memory 256956 kb
Host smart-2a11264e-7957-4b2d-9a0c-bf51f6b74263
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258504564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.258504564
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.49767837
Short name T444
Test name
Test status
Simulation time 19281716341 ps
CPU time 1033.51 seconds
Started May 30 01:20:55 PM PDT 24
Finished May 30 01:38:09 PM PDT 24
Peak memory 265484 kb
Host smart-ac2267ab-3d34-45cf-9418-769b3d3fc0a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49767837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.49767837
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.267763335
Short name T401
Test name
Test status
Simulation time 1543354159 ps
CPU time 93.21 seconds
Started May 30 01:20:50 PM PDT 24
Finished May 30 01:22:24 PM PDT 24
Peak memory 250016 kb
Host smart-a6d88e49-954c-4ec5-a763-e9f2a1ab0add
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26776
3335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.267763335
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.877612814
Short name T567
Test name
Test status
Simulation time 612140934 ps
CPU time 14.32 seconds
Started May 30 01:20:49 PM PDT 24
Finished May 30 01:21:04 PM PDT 24
Peak memory 248768 kb
Host smart-a42dd137-f419-47a6-a6fa-9ecfa3474c90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87761
2814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.877612814
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1442533847
Short name T330
Test name
Test status
Simulation time 378826869100 ps
CPU time 2720.49 seconds
Started May 30 01:20:59 PM PDT 24
Finished May 30 02:06:20 PM PDT 24
Peak memory 288904 kb
Host smart-bfe1ecc6-7b6d-464c-b6b0-e21cbd007278
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442533847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1442533847
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.1619471699
Short name T294
Test name
Test status
Simulation time 5759677939 ps
CPU time 124.67 seconds
Started May 30 01:20:48 PM PDT 24
Finished May 30 01:22:53 PM PDT 24
Peak memory 248368 kb
Host smart-1efc2814-651a-4961-bd00-03ab9d0d1406
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619471699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.1619471699
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.262446057
Short name T575
Test name
Test status
Simulation time 103509212 ps
CPU time 12.78 seconds
Started May 30 01:20:50 PM PDT 24
Finished May 30 01:21:03 PM PDT 24
Peak memory 248720 kb
Host smart-d032d73e-fd75-441c-a6e3-f29259f8b9e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26244
6057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.262446057
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2152856691
Short name T377
Test name
Test status
Simulation time 261012517 ps
CPU time 24.88 seconds
Started May 30 01:20:49 PM PDT 24
Finished May 30 01:21:14 PM PDT 24
Peak memory 247436 kb
Host smart-d9799fac-3a53-4bb5-a4fd-55ad4d317a42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21528
56691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2152856691
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.2452360610
Short name T252
Test name
Test status
Simulation time 1829658262 ps
CPU time 27.67 seconds
Started May 30 01:20:49 PM PDT 24
Finished May 30 01:21:17 PM PDT 24
Peak memory 254780 kb
Host smart-9c665f03-b19d-4128-9beb-b0d7a5d6df13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24523
60610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2452360610
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1702384657
Short name T679
Test name
Test status
Simulation time 138425389 ps
CPU time 5 seconds
Started May 30 01:20:52 PM PDT 24
Finished May 30 01:20:58 PM PDT 24
Peak memory 240552 kb
Host smart-1e133cd1-2b27-404b-9c60-79ccec8be208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17023
84657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1702384657
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2247292233
Short name T628
Test name
Test status
Simulation time 17737505064 ps
CPU time 1943.42 seconds
Started May 30 01:20:51 PM PDT 24
Finished May 30 01:53:16 PM PDT 24
Peak memory 305496 kb
Host smart-7b835c4a-0120-4eb8-8756-f6723f00dc79
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247292233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2247292233
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.1357318450
Short name T446
Test name
Test status
Simulation time 31229411935 ps
CPU time 1944.17 seconds
Started May 30 01:20:49 PM PDT 24
Finished May 30 01:53:14 PM PDT 24
Peak memory 273104 kb
Host smart-f719f2ee-f498-4d69-a47b-f178c3ffb493
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357318450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.1357318450
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.2650676750
Short name T638
Test name
Test status
Simulation time 2399075758 ps
CPU time 41.45 seconds
Started May 30 01:20:50 PM PDT 24
Finished May 30 01:21:32 PM PDT 24
Peak memory 255912 kb
Host smart-0c80d5c1-b66b-4c2b-b2c5-63b9b1903f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26506
76750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.2650676750
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1558360909
Short name T529
Test name
Test status
Simulation time 779426537 ps
CPU time 39.67 seconds
Started May 30 01:20:48 PM PDT 24
Finished May 30 01:21:29 PM PDT 24
Peak memory 255396 kb
Host smart-eea8a717-7388-425f-b15f-0d3ae343ab22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15583
60909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1558360909
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.2209899437
Short name T305
Test name
Test status
Simulation time 67732470109 ps
CPU time 1795.37 seconds
Started May 30 01:20:51 PM PDT 24
Finished May 30 01:50:47 PM PDT 24
Peak memory 289284 kb
Host smart-6e0dfe26-eeb4-4f94-ba51-5fd8bde6377c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209899437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2209899437
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.2312984062
Short name T66
Test name
Test status
Simulation time 144265855385 ps
CPU time 2418.23 seconds
Started May 30 01:20:57 PM PDT 24
Finished May 30 02:01:17 PM PDT 24
Peak memory 288264 kb
Host smart-bafe83a1-8007-40e1-bc27-30be0ff8ea78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312984062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.2312984062
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1079098249
Short name T65
Test name
Test status
Simulation time 39385103054 ps
CPU time 348.87 seconds
Started May 30 01:20:50 PM PDT 24
Finished May 30 01:26:40 PM PDT 24
Peak memory 247964 kb
Host smart-db3e69d8-51c2-4d1a-ba5d-901546e40cc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079098249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1079098249
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3536389849
Short name T581
Test name
Test status
Simulation time 344386087 ps
CPU time 27.56 seconds
Started May 30 01:20:57 PM PDT 24
Finished May 30 01:21:26 PM PDT 24
Peak memory 248748 kb
Host smart-b9d429d6-813b-46c2-8b33-5d93d006906c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35363
89849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3536389849
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.263081583
Short name T604
Test name
Test status
Simulation time 3950034483 ps
CPU time 49.05 seconds
Started May 30 01:20:50 PM PDT 24
Finished May 30 01:21:40 PM PDT 24
Peak memory 255624 kb
Host smart-3f041aab-0cc8-4b53-9d6c-714ebe72b42c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26308
1583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.263081583
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.405441331
Short name T554
Test name
Test status
Simulation time 37417522 ps
CPU time 6.15 seconds
Started May 30 01:20:57 PM PDT 24
Finished May 30 01:21:04 PM PDT 24
Peak memory 239224 kb
Host smart-19e77d2e-e188-4e6e-b568-5af7dadfe7d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40544
1331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.405441331
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1375052836
Short name T625
Test name
Test status
Simulation time 829036262 ps
CPU time 17.28 seconds
Started May 30 01:20:55 PM PDT 24
Finished May 30 01:21:12 PM PDT 24
Peak memory 248772 kb
Host smart-035a766f-a5d1-4bf5-a28b-64afeab388eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13750
52836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1375052836
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.1400222351
Short name T676
Test name
Test status
Simulation time 27626193457 ps
CPU time 2953.34 seconds
Started May 30 01:20:52 PM PDT 24
Finished May 30 02:10:07 PM PDT 24
Peak memory 321472 kb
Host smart-87b23f62-6d7b-434b-84ae-23b1e8289d2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400222351 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.1400222351
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2361560864
Short name T705
Test name
Test status
Simulation time 23327366090 ps
CPU time 1622.01 seconds
Started May 30 01:21:05 PM PDT 24
Finished May 30 01:48:09 PM PDT 24
Peak memory 273384 kb
Host smart-158f618a-ed66-44c5-a170-ea5fe3dac163
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361560864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2361560864
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2789573367
Short name T557
Test name
Test status
Simulation time 100202184 ps
CPU time 14.13 seconds
Started May 30 01:20:50 PM PDT 24
Finished May 30 01:21:05 PM PDT 24
Peak memory 255556 kb
Host smart-b66c9bf0-ddf0-4def-9a91-c54c6cd6f6e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27895
73367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2789573367
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.3907998147
Short name T450
Test name
Test status
Simulation time 1430140736 ps
CPU time 32.53 seconds
Started May 30 01:20:49 PM PDT 24
Finished May 30 01:21:22 PM PDT 24
Peak memory 255732 kb
Host smart-326e0788-490d-4da8-a6dc-0ceb3cba3039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39079
98147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3907998147
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.4215970350
Short name T565
Test name
Test status
Simulation time 31889604780 ps
CPU time 1767.21 seconds
Started May 30 01:21:05 PM PDT 24
Finished May 30 01:50:34 PM PDT 24
Peak memory 272656 kb
Host smart-52220d18-087d-4653-b375-8b9657ec7755
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215970350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.4215970350
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2429660987
Short name T643
Test name
Test status
Simulation time 10363530607 ps
CPU time 970.19 seconds
Started May 30 01:21:06 PM PDT 24
Finished May 30 01:37:18 PM PDT 24
Peak memory 273124 kb
Host smart-5f6e505f-fe3d-4448-85fd-6674d0238c88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429660987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2429660987
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.3284829779
Short name T302
Test name
Test status
Simulation time 8292740249 ps
CPU time 254.31 seconds
Started May 30 01:21:05 PM PDT 24
Finished May 30 01:25:20 PM PDT 24
Peak memory 248008 kb
Host smart-19a5a4d2-efe6-43e2-9b0b-602e5eca0531
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284829779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3284829779
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.3398272998
Short name T645
Test name
Test status
Simulation time 16623108762 ps
CPU time 65.98 seconds
Started May 30 01:20:52 PM PDT 24
Finished May 30 01:21:59 PM PDT 24
Peak memory 256192 kb
Host smart-34dd3d44-017b-4701-bb7b-8102db2c9f28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33982
72998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.3398272998
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.75906740
Short name T548
Test name
Test status
Simulation time 411494486 ps
CPU time 20.61 seconds
Started May 30 01:20:52 PM PDT 24
Finished May 30 01:21:14 PM PDT 24
Peak memory 255900 kb
Host smart-5dcf4ad8-af6c-4c92-aa59-fac549db9f61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75906
740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.75906740
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.835273454
Short name T551
Test name
Test status
Simulation time 2011672768 ps
CPU time 26.49 seconds
Started May 30 01:21:05 PM PDT 24
Finished May 30 01:21:33 PM PDT 24
Peak memory 247456 kb
Host smart-2fb7e572-8204-49e9-a5e1-7ba44a612ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83527
3454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.835273454
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.4244503482
Short name T379
Test name
Test status
Simulation time 1102581658 ps
CPU time 19.21 seconds
Started May 30 01:20:51 PM PDT 24
Finished May 30 01:21:11 PM PDT 24
Peak memory 248724 kb
Host smart-1277c7b3-290f-4a64-8410-033a75efa301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42445
03482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.4244503482
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.1702276872
Short name T586
Test name
Test status
Simulation time 25143540115 ps
CPU time 1980.04 seconds
Started May 30 01:21:06 PM PDT 24
Finished May 30 01:54:07 PM PDT 24
Peak memory 273352 kb
Host smart-5bc4cea3-5ef0-4fc1-868c-70d299dfacc1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702276872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.1702276872
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.1899478963
Short name T3
Test name
Test status
Simulation time 9478989929 ps
CPU time 41.53 seconds
Started May 30 01:21:05 PM PDT 24
Finished May 30 01:21:47 PM PDT 24
Peak memory 256136 kb
Host smart-3776633d-1389-441f-8bf8-e78307910ad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18994
78963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1899478963
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.1358472633
Short name T568
Test name
Test status
Simulation time 484130372 ps
CPU time 23.17 seconds
Started May 30 01:21:04 PM PDT 24
Finished May 30 01:21:28 PM PDT 24
Peak memory 256328 kb
Host smart-99417188-f47a-4b49-9968-495345e548e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13584
72633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.1358472633
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.690569088
Short name T612
Test name
Test status
Simulation time 14333988363 ps
CPU time 1504.52 seconds
Started May 30 01:21:03 PM PDT 24
Finished May 30 01:46:08 PM PDT 24
Peak memory 289132 kb
Host smart-3e119836-a6f1-41a5-b849-d5391678b5a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690569088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.690569088
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3734445926
Short name T98
Test name
Test status
Simulation time 58577315833 ps
CPU time 2861.84 seconds
Started May 30 01:21:04 PM PDT 24
Finished May 30 02:08:48 PM PDT 24
Peak memory 281504 kb
Host smart-ac73d2af-0bc8-468f-a8b9-40afb4258b06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734445926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3734445926
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.2567757854
Short name T315
Test name
Test status
Simulation time 112794291524 ps
CPU time 309.29 seconds
Started May 30 01:21:05 PM PDT 24
Finished May 30 01:26:16 PM PDT 24
Peak memory 254536 kb
Host smart-1faaec63-338e-4a40-a2c1-08c52c6501af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567757854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.2567757854
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.4131059923
Short name T431
Test name
Test status
Simulation time 252432976 ps
CPU time 9.21 seconds
Started May 30 01:21:05 PM PDT 24
Finished May 30 01:21:15 PM PDT 24
Peak memory 254124 kb
Host smart-d76f348c-d5af-4e6b-92a2-4872f0faf3cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41310
59923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.4131059923
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2613138275
Short name T359
Test name
Test status
Simulation time 2328872420 ps
CPU time 68.12 seconds
Started May 30 01:21:05 PM PDT 24
Finished May 30 01:22:15 PM PDT 24
Peak memory 255568 kb
Host smart-0ce65d4d-b71d-43ce-a42e-6bae1bc4d8ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26131
38275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2613138275
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.766681314
Short name T2
Test name
Test status
Simulation time 203405382 ps
CPU time 4.58 seconds
Started May 30 01:21:06 PM PDT 24
Finished May 30 01:21:12 PM PDT 24
Peak memory 240548 kb
Host smart-cbfd971d-f2f1-4fa3-899a-f34e274d4f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76668
1314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.766681314
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.3431324851
Short name T492
Test name
Test status
Simulation time 900095267 ps
CPU time 16.24 seconds
Started May 30 01:21:04 PM PDT 24
Finished May 30 01:21:21 PM PDT 24
Peak memory 252840 kb
Host smart-2cf66005-e812-4485-9e62-267a5a9840c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34313
24851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.3431324851
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1497537924
Short name T223
Test name
Test status
Simulation time 164626238 ps
CPU time 2.51 seconds
Started May 30 01:19:32 PM PDT 24
Finished May 30 01:19:36 PM PDT 24
Peak memory 248896 kb
Host smart-6b2a40ed-93f2-4c6b-8f4e-cce315740f58
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1497537924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1497537924
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.4088613398
Short name T90
Test name
Test status
Simulation time 60566925045 ps
CPU time 1780.12 seconds
Started May 30 01:19:32 PM PDT 24
Finished May 30 01:49:14 PM PDT 24
Peak memory 285316 kb
Host smart-e638dc71-c592-49f9-831c-dc9378d0ffad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088613398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.4088613398
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1968436836
Short name T545
Test name
Test status
Simulation time 4217183133 ps
CPU time 46.21 seconds
Started May 30 01:19:37 PM PDT 24
Finished May 30 01:20:23 PM PDT 24
Peak memory 240648 kb
Host smart-7e56ece2-8f45-46db-a8bf-e5dd81eec897
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1968436836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1968436836
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.2431904677
Short name T668
Test name
Test status
Simulation time 10626770713 ps
CPU time 168.06 seconds
Started May 30 01:19:30 PM PDT 24
Finished May 30 01:22:19 PM PDT 24
Peak memory 250400 kb
Host smart-0a0b648c-cb7c-4bf1-8d41-20692041e075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24319
04677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2431904677
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2197728908
Short name T532
Test name
Test status
Simulation time 13556845095 ps
CPU time 71.43 seconds
Started May 30 01:19:33 PM PDT 24
Finished May 30 01:20:46 PM PDT 24
Peak memory 248820 kb
Host smart-68c2ef10-4b73-4757-8430-c3bc026283c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21977
28908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2197728908
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3814038449
Short name T606
Test name
Test status
Simulation time 159460992164 ps
CPU time 2186 seconds
Started May 30 01:19:32 PM PDT 24
Finished May 30 01:56:00 PM PDT 24
Peak memory 282008 kb
Host smart-b2c9de3f-dd40-47e4-bcf6-9d283b087b5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814038449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3814038449
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.3873516648
Short name T391
Test name
Test status
Simulation time 52875817024 ps
CPU time 1112.4 seconds
Started May 30 01:19:34 PM PDT 24
Finished May 30 01:38:08 PM PDT 24
Peak memory 281580 kb
Host smart-0c8c70d5-8818-4e02-9f2f-a58302bd19e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873516648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.3873516648
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.1932247504
Short name T689
Test name
Test status
Simulation time 5595580772 ps
CPU time 223.97 seconds
Started May 30 01:19:31 PM PDT 24
Finished May 30 01:23:16 PM PDT 24
Peak memory 248240 kb
Host smart-3b667c02-257a-41bb-9610-5ed5342c69d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932247504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1932247504
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1560088176
Short name T276
Test name
Test status
Simulation time 3789979934 ps
CPU time 48 seconds
Started May 30 01:19:36 PM PDT 24
Finished May 30 01:20:25 PM PDT 24
Peak memory 248760 kb
Host smart-996466b0-3f14-43d3-b702-7eaf5cd8619a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15600
88176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1560088176
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1983226030
Short name T85
Test name
Test status
Simulation time 430381305 ps
CPU time 11.32 seconds
Started May 30 01:19:32 PM PDT 24
Finished May 30 01:19:45 PM PDT 24
Peak memory 247328 kb
Host smart-6037ae18-7f3b-4f93-81d4-20e82fd84420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19832
26030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1983226030
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.2493799780
Short name T11
Test name
Test status
Simulation time 775410178 ps
CPU time 12.09 seconds
Started May 30 01:19:31 PM PDT 24
Finished May 30 01:19:45 PM PDT 24
Peak memory 270292 kb
Host smart-e5bd7c48-1c16-42a1-abff-51047c45182a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2493799780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.2493799780
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1091027247
Short name T296
Test name
Test status
Simulation time 241688451 ps
CPU time 26.77 seconds
Started May 30 01:19:31 PM PDT 24
Finished May 30 01:19:59 PM PDT 24
Peak memory 247416 kb
Host smart-9f5dd58e-5786-4185-8252-b2e00a2729f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10910
27247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1091027247
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2838296577
Short name T478
Test name
Test status
Simulation time 436831169 ps
CPU time 13.52 seconds
Started May 30 01:19:30 PM PDT 24
Finished May 30 01:19:45 PM PDT 24
Peak memory 248772 kb
Host smart-6e22def3-1b75-4616-a903-a202d8712333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28382
96577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2838296577
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.3912835376
Short name T64
Test name
Test status
Simulation time 68033789921 ps
CPU time 2834.04 seconds
Started May 30 01:19:32 PM PDT 24
Finished May 30 02:06:47 PM PDT 24
Peak memory 289844 kb
Host smart-6f3fbf56-a327-49c1-8fd9-494eb42ea48a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912835376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.3912835376
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.1866510844
Short name T684
Test name
Test status
Simulation time 37216377404 ps
CPU time 3549.52 seconds
Started May 30 01:19:31 PM PDT 24
Finished May 30 02:18:42 PM PDT 24
Peak memory 322308 kb
Host smart-e8bc1b00-aae0-4278-9b86-acf556cd51ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866510844 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.1866510844
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.783845464
Short name T670
Test name
Test status
Simulation time 65764027860 ps
CPU time 2127.56 seconds
Started May 30 01:21:04 PM PDT 24
Finished May 30 01:56:32 PM PDT 24
Peak memory 281608 kb
Host smart-c6230d2c-c6b4-412c-8653-12e02fc9c592
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783845464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.783845464
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1792357933
Short name T515
Test name
Test status
Simulation time 11045683454 ps
CPU time 251.47 seconds
Started May 30 01:21:05 PM PDT 24
Finished May 30 01:25:17 PM PDT 24
Peak memory 256708 kb
Host smart-81e1aa46-9eb6-40cf-a7d2-777d956b4e73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17923
57933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1792357933
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.2245021870
Short name T229
Test name
Test status
Simulation time 770237427 ps
CPU time 41.24 seconds
Started May 30 01:21:05 PM PDT 24
Finished May 30 01:21:47 PM PDT 24
Peak memory 254908 kb
Host smart-0348cbf5-779d-4508-8e77-44f0f4e67b9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22450
21870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2245021870
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.999870570
Short name T343
Test name
Test status
Simulation time 60358663602 ps
CPU time 1722.67 seconds
Started May 30 01:21:04 PM PDT 24
Finished May 30 01:49:48 PM PDT 24
Peak memory 273492 kb
Host smart-91699add-5c71-4721-8d06-87b78b74f673
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999870570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.999870570
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.514378866
Short name T415
Test name
Test status
Simulation time 66467332395 ps
CPU time 1435.74 seconds
Started May 30 01:21:04 PM PDT 24
Finished May 30 01:45:01 PM PDT 24
Peak memory 289732 kb
Host smart-617c5271-f0c9-4754-915a-bc4e2caeb290
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514378866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.514378866
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.3368791578
Short name T301
Test name
Test status
Simulation time 9934665679 ps
CPU time 93.61 seconds
Started May 30 01:21:06 PM PDT 24
Finished May 30 01:22:41 PM PDT 24
Peak memory 248208 kb
Host smart-c79f0259-e599-46bd-9956-6013a34eb05f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368791578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3368791578
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.1449477961
Short name T364
Test name
Test status
Simulation time 2992998463 ps
CPU time 27.56 seconds
Started May 30 01:21:04 PM PDT 24
Finished May 30 01:21:33 PM PDT 24
Peak memory 248816 kb
Host smart-7360f7d5-c6ca-42d8-82ae-1d595ccf86f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14494
77961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1449477961
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2670929314
Short name T513
Test name
Test status
Simulation time 36991815 ps
CPU time 3.1 seconds
Started May 30 01:21:04 PM PDT 24
Finished May 30 01:21:08 PM PDT 24
Peak memory 239236 kb
Host smart-4fb22611-d97a-4899-b42b-df1a14179605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26709
29314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2670929314
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.1001965669
Short name T259
Test name
Test status
Simulation time 541449279 ps
CPU time 20.5 seconds
Started May 30 01:21:06 PM PDT 24
Finished May 30 01:21:28 PM PDT 24
Peak memory 248748 kb
Host smart-0db46387-f52f-446b-b256-67a234b83671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10019
65669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.1001965669
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2533568755
Short name T28
Test name
Test status
Simulation time 446229360 ps
CPU time 32.1 seconds
Started May 30 01:21:05 PM PDT 24
Finished May 30 01:21:39 PM PDT 24
Peak memory 248712 kb
Host smart-8177edec-7e1d-4768-a73d-f9380ac74499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25335
68755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2533568755
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.1375798103
Short name T632
Test name
Test status
Simulation time 85135115679 ps
CPU time 1840.78 seconds
Started May 30 01:21:06 PM PDT 24
Finished May 30 01:51:48 PM PDT 24
Peak memory 305156 kb
Host smart-a45d23ba-7e62-48e8-ad44-92214aa808ac
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375798103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1375798103
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.1535140156
Short name T463
Test name
Test status
Simulation time 38143972457 ps
CPU time 1855.75 seconds
Started May 30 01:21:05 PM PDT 24
Finished May 30 01:52:01 PM PDT 24
Peak memory 305668 kb
Host smart-65db5c01-a086-4c00-9b6b-74ff810362dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535140156 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.1535140156
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2741873667
Short name T293
Test name
Test status
Simulation time 22341294332 ps
CPU time 1320.43 seconds
Started May 30 01:21:05 PM PDT 24
Finished May 30 01:43:07 PM PDT 24
Peak memory 273372 kb
Host smart-5d02c324-6ac5-4d2c-89a1-cc63650f671e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741873667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2741873667
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.1719776264
Short name T497
Test name
Test status
Simulation time 1071743729 ps
CPU time 115.43 seconds
Started May 30 01:21:07 PM PDT 24
Finished May 30 01:23:03 PM PDT 24
Peak memory 250216 kb
Host smart-e20f9deb-5dd4-4fe5-a319-bb72b2415b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17197
76264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.1719776264
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.3103471880
Short name T520
Test name
Test status
Simulation time 198991297 ps
CPU time 12.32 seconds
Started May 30 01:21:06 PM PDT 24
Finished May 30 01:21:20 PM PDT 24
Peak memory 252808 kb
Host smart-4ec910b3-61b5-40e0-ad8a-56d75b978fa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31034
71880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3103471880
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.2694116744
Short name T5
Test name
Test status
Simulation time 94577717239 ps
CPU time 1772.33 seconds
Started May 30 01:21:06 PM PDT 24
Finished May 30 01:50:40 PM PDT 24
Peak memory 266268 kb
Host smart-9c32970a-cbd8-441e-835e-797c63fa7489
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694116744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.2694116744
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2689428904
Short name T384
Test name
Test status
Simulation time 52968180861 ps
CPU time 1271.26 seconds
Started May 30 01:21:07 PM PDT 24
Finished May 30 01:42:19 PM PDT 24
Peak memory 288396 kb
Host smart-c82e638f-62a5-4189-a974-c10b2c626607
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689428904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2689428904
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1569798933
Short name T320
Test name
Test status
Simulation time 10965501752 ps
CPU time 279.76 seconds
Started May 30 01:21:04 PM PDT 24
Finished May 30 01:25:45 PM PDT 24
Peak memory 248224 kb
Host smart-80a0f316-f395-43fd-bfb2-90f9612a87d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569798933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1569798933
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3596301851
Short name T31
Test name
Test status
Simulation time 691849768 ps
CPU time 43.27 seconds
Started May 30 01:21:07 PM PDT 24
Finished May 30 01:21:51 PM PDT 24
Peak memory 248752 kb
Host smart-299311b8-5a65-4926-a08b-6fa95b7bb810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35963
01851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3596301851
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.425925416
Short name T103
Test name
Test status
Simulation time 2775675036 ps
CPU time 38.27 seconds
Started May 30 01:21:06 PM PDT 24
Finished May 30 01:21:46 PM PDT 24
Peak memory 248944 kb
Host smart-85c1e494-2a3e-48e1-b5a8-ae41963c098d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42592
5416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.425925416
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.922330541
Short name T701
Test name
Test status
Simulation time 108976436 ps
CPU time 7.54 seconds
Started May 30 01:21:05 PM PDT 24
Finished May 30 01:21:14 PM PDT 24
Peak memory 251368 kb
Host smart-620065c8-8412-493e-b246-d711b73dab51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92233
0541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.922330541
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1108290833
Short name T376
Test name
Test status
Simulation time 617877419 ps
CPU time 15.44 seconds
Started May 30 01:21:07 PM PDT 24
Finished May 30 01:21:23 PM PDT 24
Peak memory 256908 kb
Host smart-c96b5847-c968-4cd7-9a8a-ac83a503c1a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11082
90833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1108290833
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2612282959
Short name T250
Test name
Test status
Simulation time 3194427004 ps
CPU time 273.81 seconds
Started May 30 01:21:06 PM PDT 24
Finished May 30 01:25:41 PM PDT 24
Peak memory 257012 kb
Host smart-d7e2ca5d-699c-495f-9461-d0556a1a2566
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612282959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2612282959
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.2651964977
Short name T180
Test name
Test status
Simulation time 318238965336 ps
CPU time 5966.78 seconds
Started May 30 01:21:07 PM PDT 24
Finished May 30 03:00:35 PM PDT 24
Peak memory 371320 kb
Host smart-5e3c1839-71a9-4b38-84f2-468bf1616f07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651964977 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.2651964977
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.1698495681
Short name T468
Test name
Test status
Simulation time 42971321688 ps
CPU time 2634.49 seconds
Started May 30 01:21:18 PM PDT 24
Finished May 30 02:05:14 PM PDT 24
Peak memory 281656 kb
Host smart-ebe7bbd1-9464-403f-9b54-84c12ca9bb8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698495681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.1698495681
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1772953534
Short name T227
Test name
Test status
Simulation time 9344690963 ps
CPU time 174.86 seconds
Started May 30 01:21:17 PM PDT 24
Finished May 30 01:24:13 PM PDT 24
Peak memory 250948 kb
Host smart-06c649e0-9e22-499d-81f1-e70525129e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17729
53534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1772953534
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2785474033
Short name T709
Test name
Test status
Simulation time 163812463 ps
CPU time 10.11 seconds
Started May 30 01:21:06 PM PDT 24
Finished May 30 01:21:17 PM PDT 24
Peak memory 248972 kb
Host smart-5060d61d-d83c-4dc8-81fe-eebc7a36a697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27854
74033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2785474033
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.181783980
Short name T340
Test name
Test status
Simulation time 39201050928 ps
CPU time 1463.17 seconds
Started May 30 01:21:21 PM PDT 24
Finished May 30 01:45:46 PM PDT 24
Peak memory 270652 kb
Host smart-aa09dbd8-8ccc-4135-bebd-50733893334c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181783980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.181783980
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.4189364989
Short name T640
Test name
Test status
Simulation time 30947640150 ps
CPU time 1822.78 seconds
Started May 30 01:21:18 PM PDT 24
Finished May 30 01:51:42 PM PDT 24
Peak memory 289244 kb
Host smart-23d26a59-3b69-44aa-bfa5-b29f78ede4d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189364989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.4189364989
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.1904650063
Short name T8
Test name
Test status
Simulation time 68546081631 ps
CPU time 389.23 seconds
Started May 30 01:21:18 PM PDT 24
Finished May 30 01:27:48 PM PDT 24
Peak memory 254316 kb
Host smart-09258826-0a84-4f63-b0c6-79ca7f9cca88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904650063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1904650063
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.2152434819
Short name T275
Test name
Test status
Simulation time 2798767937 ps
CPU time 41.02 seconds
Started May 30 01:21:04 PM PDT 24
Finished May 30 01:21:45 PM PDT 24
Peak memory 256188 kb
Host smart-a8c7b85a-b4de-4248-b756-5413558f464d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21524
34819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2152434819
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2038798993
Short name T404
Test name
Test status
Simulation time 339798041 ps
CPU time 37.83 seconds
Started May 30 01:21:06 PM PDT 24
Finished May 30 01:21:45 PM PDT 24
Peak memory 248696 kb
Host smart-cee3c0e5-4225-4fbd-a6cc-fd19398fdcf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20387
98993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2038798993
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.522478388
Short name T602
Test name
Test status
Simulation time 87339570 ps
CPU time 6.04 seconds
Started May 30 01:21:21 PM PDT 24
Finished May 30 01:21:28 PM PDT 24
Peak memory 248756 kb
Host smart-16220560-e91a-4d34-a69c-733a6b98f9ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52247
8388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.522478388
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1434034083
Short name T525
Test name
Test status
Simulation time 676510670 ps
CPU time 14.27 seconds
Started May 30 01:21:06 PM PDT 24
Finished May 30 01:21:22 PM PDT 24
Peak memory 248752 kb
Host smart-4005fe09-12b5-41d3-b191-eff8effdb25d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14340
34083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1434034083
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1684893454
Short name T694
Test name
Test status
Simulation time 322245715288 ps
CPU time 3225.92 seconds
Started May 30 01:21:18 PM PDT 24
Finished May 30 02:15:05 PM PDT 24
Peak memory 288944 kb
Host smart-e906c3b2-cba2-4789-9334-6c3e658a72b8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684893454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1684893454
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.1442280558
Short name T648
Test name
Test status
Simulation time 69463737242 ps
CPU time 2056.23 seconds
Started May 30 01:21:18 PM PDT 24
Finished May 30 01:55:35 PM PDT 24
Peak memory 285288 kb
Host smart-87501a13-84ef-4a1f-aef2-d7c0fa82d0c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442280558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.1442280558
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.412885402
Short name T510
Test name
Test status
Simulation time 7799808462 ps
CPU time 183.12 seconds
Started May 30 01:21:21 PM PDT 24
Finished May 30 01:24:25 PM PDT 24
Peak memory 256932 kb
Host smart-083b227c-5332-4016-a4ab-9426b8179a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41288
5402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.412885402
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3607628439
Short name T77
Test name
Test status
Simulation time 1307503483 ps
CPU time 51.41 seconds
Started May 30 01:21:18 PM PDT 24
Finished May 30 01:22:10 PM PDT 24
Peak memory 249160 kb
Host smart-8cca374e-1f76-4c89-82aa-6dfae7a456c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36076
28439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3607628439
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3830174030
Short name T328
Test name
Test status
Simulation time 239175843940 ps
CPU time 1475.04 seconds
Started May 30 01:21:20 PM PDT 24
Finished May 30 01:45:56 PM PDT 24
Peak memory 288944 kb
Host smart-c1bb7cd6-e78b-4889-9eda-3cf0469ab522
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830174030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3830174030
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.189883006
Short name T408
Test name
Test status
Simulation time 46342296296 ps
CPU time 2459.36 seconds
Started May 30 01:21:18 PM PDT 24
Finished May 30 02:02:18 PM PDT 24
Peak memory 283984 kb
Host smart-dcdaa126-1086-47f2-a8a5-131e856502cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189883006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.189883006
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3727574243
Short name T314
Test name
Test status
Simulation time 16003690498 ps
CPU time 357.07 seconds
Started May 30 01:21:19 PM PDT 24
Finished May 30 01:27:17 PM PDT 24
Peak memory 248116 kb
Host smart-1a3ad5d0-2356-4c83-a8d4-84771ee5041a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727574243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3727574243
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.3915639160
Short name T659
Test name
Test status
Simulation time 1574601873 ps
CPU time 24.89 seconds
Started May 30 01:21:18 PM PDT 24
Finished May 30 01:21:44 PM PDT 24
Peak memory 248724 kb
Host smart-9e5cc630-6ab0-4bf7-ace1-9d8c9eb3d2ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39156
39160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.3915639160
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.2929912626
Short name T198
Test name
Test status
Simulation time 307637172 ps
CPU time 20.18 seconds
Started May 30 01:21:19 PM PDT 24
Finished May 30 01:21:40 PM PDT 24
Peak memory 247440 kb
Host smart-2942f072-80bb-40fd-9c0b-61cdf7820df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29299
12626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2929912626
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3931723704
Short name T188
Test name
Test status
Simulation time 247549613 ps
CPU time 6.97 seconds
Started May 30 01:21:19 PM PDT 24
Finished May 30 01:21:27 PM PDT 24
Peak memory 252032 kb
Host smart-5a52ca6c-314c-435c-904f-6f2797f1becb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39317
23704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3931723704
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2007297131
Short name T675
Test name
Test status
Simulation time 567000742 ps
CPU time 16.91 seconds
Started May 30 01:21:18 PM PDT 24
Finished May 30 01:21:36 PM PDT 24
Peak memory 255912 kb
Host smart-b891235b-24c4-45c4-9cdf-8bda530491a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20072
97131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2007297131
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.4079135394
Short name T642
Test name
Test status
Simulation time 30338269997 ps
CPU time 2197.8 seconds
Started May 30 01:21:21 PM PDT 24
Finished May 30 01:58:00 PM PDT 24
Peak memory 289908 kb
Host smart-c7b81190-5112-4aa0-917d-612fa1d37168
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079135394 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.4079135394
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1504225608
Short name T110
Test name
Test status
Simulation time 37850860354 ps
CPU time 2487.13 seconds
Started May 30 01:21:19 PM PDT 24
Finished May 30 02:02:48 PM PDT 24
Peak memory 282408 kb
Host smart-a7beda7f-61d1-4ae9-89f5-b6838b454bb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504225608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1504225608
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.21905611
Short name T228
Test name
Test status
Simulation time 3367018493 ps
CPU time 60.27 seconds
Started May 30 01:21:19 PM PDT 24
Finished May 30 01:22:20 PM PDT 24
Peak memory 255664 kb
Host smart-bef201a9-1412-4b44-805a-1dca27f2de57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21905
611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.21905611
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.4287851752
Short name T661
Test name
Test status
Simulation time 331662340 ps
CPU time 40.21 seconds
Started May 30 01:21:27 PM PDT 24
Finished May 30 01:22:08 PM PDT 24
Peak memory 255832 kb
Host smart-ed5e1ace-cd80-4780-b456-06af1eb30d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42878
51752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.4287851752
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1180706712
Short name T449
Test name
Test status
Simulation time 123143358892 ps
CPU time 1816.43 seconds
Started May 30 01:21:27 PM PDT 24
Finished May 30 01:51:45 PM PDT 24
Peak memory 273396 kb
Host smart-d5d457c4-493f-4a2c-9888-e3b1564dbbfe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180706712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1180706712
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3927979727
Short name T506
Test name
Test status
Simulation time 12402842843 ps
CPU time 258.15 seconds
Started May 30 01:21:21 PM PDT 24
Finished May 30 01:25:40 PM PDT 24
Peak memory 248340 kb
Host smart-8c4af707-c975-479f-95d7-ddd90d12e16c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927979727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3927979727
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.3199266571
Short name T417
Test name
Test status
Simulation time 172081624 ps
CPU time 14.33 seconds
Started May 30 01:21:21 PM PDT 24
Finished May 30 01:21:37 PM PDT 24
Peak memory 248864 kb
Host smart-13ee6369-a266-4b1e-9cb1-b5eddffa74cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31992
66571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3199266571
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.432183433
Short name T105
Test name
Test status
Simulation time 2315344782 ps
CPU time 35.69 seconds
Started May 30 01:21:20 PM PDT 24
Finished May 30 01:21:56 PM PDT 24
Peak memory 248788 kb
Host smart-9bfedaee-cf79-4118-aebe-11bf6dffc6c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43218
3433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.432183433
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.3265649094
Short name T454
Test name
Test status
Simulation time 652703086 ps
CPU time 44.13 seconds
Started May 30 01:21:19 PM PDT 24
Finished May 30 01:22:04 PM PDT 24
Peak memory 248760 kb
Host smart-1eea93c0-155b-4d3c-a3cb-1d508992fd96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32656
49094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3265649094
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.4127045392
Short name T535
Test name
Test status
Simulation time 64837719527 ps
CPU time 3899.67 seconds
Started May 30 01:21:27 PM PDT 24
Finished May 30 02:26:28 PM PDT 24
Peak memory 289688 kb
Host smart-ee9a66f3-8f7a-4f24-acd2-89ff2f168469
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127045392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.4127045392
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.4083191757
Short name T253
Test name
Test status
Simulation time 21290895053 ps
CPU time 2490.64 seconds
Started May 30 01:21:20 PM PDT 24
Finished May 30 02:02:52 PM PDT 24
Peak memory 322668 kb
Host smart-673636f3-8444-4b49-8dfd-95ae4ff6e363
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083191757 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.4083191757
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.950140062
Short name T279
Test name
Test status
Simulation time 67552841619 ps
CPU time 2079.59 seconds
Started May 30 01:21:23 PM PDT 24
Finished May 30 01:56:04 PM PDT 24
Peak memory 283804 kb
Host smart-a3e4f56d-4bc6-4e6c-9c6b-17b4f454de2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950140062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.950140062
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.658812013
Short name T392
Test name
Test status
Simulation time 510645006 ps
CPU time 9.8 seconds
Started May 30 01:21:21 PM PDT 24
Finished May 30 01:21:31 PM PDT 24
Peak memory 253624 kb
Host smart-8d8969de-eea7-4249-804b-deef098ae478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65881
2013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.658812013
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3378107423
Short name T644
Test name
Test status
Simulation time 1763473937 ps
CPU time 28.07 seconds
Started May 30 01:21:24 PM PDT 24
Finished May 30 01:21:53 PM PDT 24
Peak memory 255956 kb
Host smart-329cba1f-b2fd-4ff2-a3d6-05ae726a7390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33781
07423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3378107423
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2595831117
Short name T201
Test name
Test status
Simulation time 21299868841 ps
CPU time 1914.8 seconds
Started May 30 01:21:24 PM PDT 24
Finished May 30 01:53:20 PM PDT 24
Peak memory 289384 kb
Host smart-3be295e8-e011-4850-81b6-34a5d4b390a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595831117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2595831117
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.2935868174
Short name T475
Test name
Test status
Simulation time 110513824494 ps
CPU time 745.95 seconds
Started May 30 01:21:24 PM PDT 24
Finished May 30 01:33:51 PM PDT 24
Peak memory 273248 kb
Host smart-17d10c70-66e0-44ba-90d9-76362296df2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935868174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2935868174
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1463139701
Short name T202
Test name
Test status
Simulation time 43694319072 ps
CPU time 462.47 seconds
Started May 30 01:21:24 PM PDT 24
Finished May 30 01:29:07 PM PDT 24
Peak memory 248128 kb
Host smart-e4fc85f1-90af-4fba-9592-c4f11ce03bfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463139701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1463139701
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3265822981
Short name T614
Test name
Test status
Simulation time 1868496208 ps
CPU time 30.23 seconds
Started May 30 01:21:20 PM PDT 24
Finished May 30 01:21:52 PM PDT 24
Peak memory 255920 kb
Host smart-0dcae645-0c12-41a6-8cb0-e9d779d3448b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32658
22981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3265822981
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.3459539300
Short name T501
Test name
Test status
Simulation time 1042954839 ps
CPU time 24.97 seconds
Started May 30 01:21:20 PM PDT 24
Finished May 30 01:21:46 PM PDT 24
Peak memory 248752 kb
Host smart-b2b0cc1e-156e-4724-93b4-07ff6ddafdfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34595
39300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.3459539300
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.4180612264
Short name T38
Test name
Test status
Simulation time 393153729 ps
CPU time 23.69 seconds
Started May 30 01:21:20 PM PDT 24
Finished May 30 01:21:45 PM PDT 24
Peak memory 254916 kb
Host smart-51a15675-8a5a-4c92-ba43-1f5a2f763d9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41806
12264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.4180612264
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.336768459
Short name T388
Test name
Test status
Simulation time 2201288481 ps
CPU time 30.13 seconds
Started May 30 01:21:24 PM PDT 24
Finished May 30 01:21:55 PM PDT 24
Peak memory 248824 kb
Host smart-52f4edca-db4d-42e3-a939-50541260f8d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33676
8459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.336768459
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2733576936
Short name T93
Test name
Test status
Simulation time 57844850513 ps
CPU time 3145.25 seconds
Started May 30 01:21:18 PM PDT 24
Finished May 30 02:13:45 PM PDT 24
Peak memory 289216 kb
Host smart-2e4902e0-804d-43d5-87bb-f168ba4e4e2a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733576936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2733576936
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.1428178595
Short name T591
Test name
Test status
Simulation time 57991259775 ps
CPU time 2593.31 seconds
Started May 30 01:21:29 PM PDT 24
Finished May 30 02:04:43 PM PDT 24
Peak memory 289192 kb
Host smart-5bd59e82-289d-4ea7-997f-ac69f8262e9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428178595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.1428178595
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.739792534
Short name T246
Test name
Test status
Simulation time 16046009885 ps
CPU time 96.75 seconds
Started May 30 01:21:31 PM PDT 24
Finished May 30 01:23:08 PM PDT 24
Peak memory 249920 kb
Host smart-8721b179-a493-4d84-a884-972a9700da3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73979
2534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.739792534
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.216566742
Short name T393
Test name
Test status
Simulation time 564113318 ps
CPU time 11.12 seconds
Started May 30 01:21:19 PM PDT 24
Finished May 30 01:21:31 PM PDT 24
Peak memory 248848 kb
Host smart-e04d6f3a-edad-46b9-a01a-4eebfcfe4db8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21656
6742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.216566742
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3206953081
Short name T341
Test name
Test status
Simulation time 172603289381 ps
CPU time 2138.37 seconds
Started May 30 01:21:31 PM PDT 24
Finished May 30 01:57:11 PM PDT 24
Peak memory 281652 kb
Host smart-32290620-d6fa-41ca-a65b-4a8447d2555f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206953081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3206953081
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.653169660
Short name T484
Test name
Test status
Simulation time 21408134664 ps
CPU time 1428.75 seconds
Started May 30 01:21:31 PM PDT 24
Finished May 30 01:45:21 PM PDT 24
Peak memory 273208 kb
Host smart-06e3d372-855d-4e04-b0f4-d8cc62d66e16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653169660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.653169660
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.2205907379
Short name T308
Test name
Test status
Simulation time 7898725925 ps
CPU time 288.72 seconds
Started May 30 01:21:33 PM PDT 24
Finished May 30 01:26:22 PM PDT 24
Peak memory 247216 kb
Host smart-63045272-2e51-4a11-8ce5-ad8b746cb183
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205907379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2205907379
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.3300890622
Short name T588
Test name
Test status
Simulation time 596501533 ps
CPU time 30.53 seconds
Started May 30 01:21:19 PM PDT 24
Finished May 30 01:21:50 PM PDT 24
Peak memory 248756 kb
Host smart-f8877b27-82ba-41e7-bcc2-e83a9cb22726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33008
90622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.3300890622
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.4200890414
Short name T538
Test name
Test status
Simulation time 818706039 ps
CPU time 26.63 seconds
Started May 30 01:21:17 PM PDT 24
Finished May 30 01:21:45 PM PDT 24
Peak memory 254784 kb
Host smart-52eea5d7-39d0-49cd-b2e7-111c35096b4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42008
90414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.4200890414
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.2736454126
Short name T199
Test name
Test status
Simulation time 1333477917 ps
CPU time 22.02 seconds
Started May 30 01:21:33 PM PDT 24
Finished May 30 01:21:55 PM PDT 24
Peak memory 256036 kb
Host smart-5075bf5f-6f57-41d3-8ecf-697500a2dad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27364
54126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2736454126
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.3022629978
Short name T451
Test name
Test status
Simulation time 229335354 ps
CPU time 16.36 seconds
Started May 30 01:21:18 PM PDT 24
Finished May 30 01:21:36 PM PDT 24
Peak memory 248756 kb
Host smart-998aef43-3f86-4b6f-987d-6e6076ab3344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30226
29978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3022629978
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.3196962109
Short name T647
Test name
Test status
Simulation time 14798138920 ps
CPU time 242.64 seconds
Started May 30 01:21:32 PM PDT 24
Finished May 30 01:25:36 PM PDT 24
Peak memory 257000 kb
Host smart-36ef8832-e339-4a84-aa45-390ae7b54f95
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196962109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.3196962109
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.340502244
Short name T473
Test name
Test status
Simulation time 52152496107 ps
CPU time 1433.68 seconds
Started May 30 01:21:31 PM PDT 24
Finished May 30 01:45:26 PM PDT 24
Peak memory 289416 kb
Host smart-a0a92586-67d0-4b42-b58c-4f63377ba29b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340502244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.340502244
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1280084892
Short name T703
Test name
Test status
Simulation time 17005322656 ps
CPU time 109.47 seconds
Started May 30 01:21:33 PM PDT 24
Finished May 30 01:23:24 PM PDT 24
Peak memory 257008 kb
Host smart-8856aed0-37b9-4b7d-8c3d-d9b915ef7be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12800
84892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1280084892
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1813603469
Short name T75
Test name
Test status
Simulation time 298050776 ps
CPU time 18.31 seconds
Started May 30 01:21:33 PM PDT 24
Finished May 30 01:21:52 PM PDT 24
Peak memory 255992 kb
Host smart-988ec8c4-0bec-4d96-b8d6-ab5c869ab758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18136
03469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1813603469
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.3281268971
Short name T287
Test name
Test status
Simulation time 170904344234 ps
CPU time 2064.01 seconds
Started May 30 01:21:31 PM PDT 24
Finished May 30 01:55:56 PM PDT 24
Peak memory 288588 kb
Host smart-7e60a2b1-a448-4772-be6e-97aa37c1577c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281268971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3281268971
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.178897243
Short name T662
Test name
Test status
Simulation time 54878670619 ps
CPU time 1835.07 seconds
Started May 30 01:21:31 PM PDT 24
Finished May 30 01:52:07 PM PDT 24
Peak memory 281540 kb
Host smart-65ae7beb-c3e5-4d5a-9fca-eec0103c5929
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178897243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.178897243
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.3597897066
Short name T553
Test name
Test status
Simulation time 727607921 ps
CPU time 22.01 seconds
Started May 30 01:21:31 PM PDT 24
Finished May 30 01:21:54 PM PDT 24
Peak memory 248760 kb
Host smart-1cf8b113-f93d-458e-b2a8-bdac9ae3bb71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35978
97066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3597897066
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.773089231
Short name T462
Test name
Test status
Simulation time 361431387 ps
CPU time 37.85 seconds
Started May 30 01:21:31 PM PDT 24
Finished May 30 01:22:10 PM PDT 24
Peak memory 255608 kb
Host smart-75cc5664-9c0a-46b0-8a7b-c6093d0460cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77308
9231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.773089231
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.2325735723
Short name T491
Test name
Test status
Simulation time 597886314 ps
CPU time 20.96 seconds
Started May 30 01:21:31 PM PDT 24
Finished May 30 01:21:53 PM PDT 24
Peak memory 255412 kb
Host smart-c12b9499-9241-417d-a4d8-1a359cf5d931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23257
35723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.2325735723
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.2580173561
Short name T631
Test name
Test status
Simulation time 204542589 ps
CPU time 19.21 seconds
Started May 30 01:21:30 PM PDT 24
Finished May 30 01:21:50 PM PDT 24
Peak memory 256940 kb
Host smart-955b3161-b6f6-4dc4-be6e-162a3c667965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25801
73561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2580173561
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.4228078130
Short name T241
Test name
Test status
Simulation time 71733932810 ps
CPU time 4864.23 seconds
Started May 30 01:21:30 PM PDT 24
Finished May 30 02:42:36 PM PDT 24
Peak memory 305288 kb
Host smart-42d0ee8d-5cd0-4c08-a29e-270f9f72f202
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228078130 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.4228078130
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.190350981
Short name T459
Test name
Test status
Simulation time 27707799458 ps
CPU time 873.59 seconds
Started May 30 01:21:32 PM PDT 24
Finished May 30 01:36:07 PM PDT 24
Peak memory 273208 kb
Host smart-50ed5042-f823-4267-80b1-b3136b43559b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190350981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.190350981
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.1052963998
Short name T443
Test name
Test status
Simulation time 16874015763 ps
CPU time 248.02 seconds
Started May 30 01:21:30 PM PDT 24
Finished May 30 01:25:39 PM PDT 24
Peak memory 256964 kb
Host smart-c4de1584-3b36-4415-a28e-3b8f5682a679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10529
63998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1052963998
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.4070915427
Short name T82
Test name
Test status
Simulation time 233090281 ps
CPU time 9.46 seconds
Started May 30 01:21:32 PM PDT 24
Finished May 30 01:21:42 PM PDT 24
Peak memory 251132 kb
Host smart-ab7cd323-99f8-4336-b6ce-7a3ac6b490b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40709
15427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.4070915427
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.2861384990
Short name T6
Test name
Test status
Simulation time 10066084651 ps
CPU time 924.07 seconds
Started May 30 01:21:34 PM PDT 24
Finished May 30 01:36:58 PM PDT 24
Peak memory 271832 kb
Host smart-0ff16a3f-ebe6-4189-82be-765e07d0f1c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861384990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2861384990
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.246963252
Short name T447
Test name
Test status
Simulation time 8782899141 ps
CPU time 642.29 seconds
Started May 30 01:21:31 PM PDT 24
Finished May 30 01:32:14 PM PDT 24
Peak memory 265172 kb
Host smart-44239480-e57f-4a1c-a9a6-596917dbbeaf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246963252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.246963252
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3862356879
Short name T317
Test name
Test status
Simulation time 19215641817 ps
CPU time 203.01 seconds
Started May 30 01:21:29 PM PDT 24
Finished May 30 01:24:53 PM PDT 24
Peak memory 247196 kb
Host smart-69b538e5-29d7-4d72-8a80-a6060d1c2276
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862356879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3862356879
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.984880935
Short name T439
Test name
Test status
Simulation time 51324234 ps
CPU time 6.08 seconds
Started May 30 01:21:32 PM PDT 24
Finished May 30 01:21:39 PM PDT 24
Peak memory 248716 kb
Host smart-370e177f-61c3-4b53-8cb5-4d6cbc906262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98488
0935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.984880935
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.1118779805
Short name T255
Test name
Test status
Simulation time 2514926453 ps
CPU time 29.76 seconds
Started May 30 01:21:30 PM PDT 24
Finished May 30 01:22:01 PM PDT 24
Peak memory 256220 kb
Host smart-a95ef529-78f1-4616-b469-c7a1897ad8e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11187
79805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1118779805
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3896883948
Short name T584
Test name
Test status
Simulation time 51890046 ps
CPU time 7.01 seconds
Started May 30 01:21:33 PM PDT 24
Finished May 30 01:21:41 PM PDT 24
Peak memory 248688 kb
Host smart-acd08244-da4a-4ae2-be77-f66912321418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38968
83948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3896883948
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3053225642
Short name T577
Test name
Test status
Simulation time 731294110 ps
CPU time 30.65 seconds
Started May 30 01:21:30 PM PDT 24
Finished May 30 01:22:01 PM PDT 24
Peak memory 248772 kb
Host smart-40eb8697-03bf-4207-90ba-4f1fd1f10a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30532
25642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3053225642
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.360841766
Short name T537
Test name
Test status
Simulation time 69347454203 ps
CPU time 2150.04 seconds
Started May 30 01:21:31 PM PDT 24
Finished May 30 01:57:23 PM PDT 24
Peak memory 281552 kb
Host smart-dcd57a70-d0be-4c38-8ceb-80e14626e551
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360841766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.360841766
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.1701338908
Short name T599
Test name
Test status
Simulation time 14713765160 ps
CPU time 882.55 seconds
Started May 30 01:21:32 PM PDT 24
Finished May 30 01:36:15 PM PDT 24
Peak memory 289872 kb
Host smart-50ac30b9-399b-481a-9caa-1f9a400d9f72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701338908 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.1701338908
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.4133848895
Short name T400
Test name
Test status
Simulation time 34059285118 ps
CPU time 893.85 seconds
Started May 30 01:21:47 PM PDT 24
Finished May 30 01:36:42 PM PDT 24
Peak memory 273140 kb
Host smart-99f5af64-7e2e-4519-9d5c-c95bd90b8675
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133848895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.4133848895
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2622157338
Short name T511
Test name
Test status
Simulation time 3040253971 ps
CPU time 115 seconds
Started May 30 01:21:45 PM PDT 24
Finished May 30 01:23:40 PM PDT 24
Peak memory 249916 kb
Host smart-a53cb1e5-bee0-456d-b578-f5b9b2b1b54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26221
57338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2622157338
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.2547559067
Short name T17
Test name
Test status
Simulation time 351860260 ps
CPU time 21.66 seconds
Started May 30 01:21:46 PM PDT 24
Finished May 30 01:22:09 PM PDT 24
Peak memory 255652 kb
Host smart-c1f4e9fe-32bd-475d-8460-c804967ab3c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25475
59067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.2547559067
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2014722585
Short name T300
Test name
Test status
Simulation time 33162773791 ps
CPU time 1490.71 seconds
Started May 30 01:21:46 PM PDT 24
Finished May 30 01:46:38 PM PDT 24
Peak memory 283540 kb
Host smart-208fe3e9-e4db-4f5c-b503-d80240eb1e4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014722585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2014722585
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.3240658298
Short name T613
Test name
Test status
Simulation time 190200323857 ps
CPU time 2783.85 seconds
Started May 30 01:21:45 PM PDT 24
Finished May 30 02:08:10 PM PDT 24
Peak memory 281584 kb
Host smart-9716e618-d58e-4d7d-adc3-8983c50e8005
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240658298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3240658298
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.989943757
Short name T412
Test name
Test status
Simulation time 49883454907 ps
CPU time 167.34 seconds
Started May 30 01:21:47 PM PDT 24
Finished May 30 01:24:35 PM PDT 24
Peak memory 256332 kb
Host smart-05344a7d-8287-431e-81f0-b9205d76239d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989943757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.989943757
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.3113206685
Short name T426
Test name
Test status
Simulation time 4006170324 ps
CPU time 30.06 seconds
Started May 30 01:21:32 PM PDT 24
Finished May 30 01:22:03 PM PDT 24
Peak memory 248812 kb
Host smart-6e8ce7f3-a041-45ed-99f9-10a06ae0c060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31132
06685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.3113206685
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.3185077579
Short name T508
Test name
Test status
Simulation time 335140220 ps
CPU time 10.85 seconds
Started May 30 01:21:45 PM PDT 24
Finished May 30 01:21:57 PM PDT 24
Peak memory 248896 kb
Host smart-38d2e576-41c0-4a4c-8617-27013023a85d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31850
77579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.3185077579
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.88828172
Short name T573
Test name
Test status
Simulation time 1451543685 ps
CPU time 15.26 seconds
Started May 30 01:21:49 PM PDT 24
Finished May 30 01:22:05 PM PDT 24
Peak memory 254160 kb
Host smart-a3b13420-3bf6-451b-8094-c2f409a53b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88828
172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.88828172
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.1652349507
Short name T373
Test name
Test status
Simulation time 213300662 ps
CPU time 16.51 seconds
Started May 30 01:21:32 PM PDT 24
Finished May 30 01:21:50 PM PDT 24
Peak memory 255964 kb
Host smart-ae2b9a03-a294-4e8e-a203-71b3eca542e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16523
49507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.1652349507
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.4064680907
Short name T629
Test name
Test status
Simulation time 37124114936 ps
CPU time 1764.86 seconds
Started May 30 01:21:47 PM PDT 24
Finished May 30 01:51:13 PM PDT 24
Peak memory 305176 kb
Host smart-da2a6101-e2ec-4fd1-b690-413dce9fa5c5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064680907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.4064680907
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.3259179809
Short name T215
Test name
Test status
Simulation time 13866585 ps
CPU time 2.34 seconds
Started May 30 01:19:32 PM PDT 24
Finished May 30 01:19:35 PM PDT 24
Peak memory 248876 kb
Host smart-c0c3ab4b-13e5-4b81-98cc-55241497753f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3259179809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3259179809
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.1885595962
Short name T13
Test name
Test status
Simulation time 37207504857 ps
CPU time 2536.96 seconds
Started May 30 01:19:33 PM PDT 24
Finished May 30 02:01:52 PM PDT 24
Peak memory 289756 kb
Host smart-cbb4f17e-5da6-4e78-844b-1fc9fd2d7f22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885595962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1885595962
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.330366532
Short name T507
Test name
Test status
Simulation time 740041865 ps
CPU time 25.71 seconds
Started May 30 01:19:33 PM PDT 24
Finished May 30 01:20:00 PM PDT 24
Peak memory 248796 kb
Host smart-d3f9ab83-7d8a-40ee-a977-81fadcf7121b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=330366532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.330366532
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.968864734
Short name T593
Test name
Test status
Simulation time 1848139482 ps
CPU time 89.46 seconds
Started May 30 01:19:36 PM PDT 24
Finished May 30 01:21:06 PM PDT 24
Peak memory 256444 kb
Host smart-014170e0-9c39-4f05-afbf-75afac7d2ecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96886
4734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.968864734
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1047887531
Short name T563
Test name
Test status
Simulation time 4153276769 ps
CPU time 67.02 seconds
Started May 30 01:19:33 PM PDT 24
Finished May 30 01:20:41 PM PDT 24
Peak memory 256212 kb
Host smart-f1218318-4df5-42c2-9562-92a329e8968f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10478
87531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1047887531
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.232976933
Short name T336
Test name
Test status
Simulation time 24298436193 ps
CPU time 1437.12 seconds
Started May 30 01:19:36 PM PDT 24
Finished May 30 01:43:34 PM PDT 24
Peak memory 273384 kb
Host smart-071020ca-154e-4402-a49d-b42fdbff6fa6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232976933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.232976933
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.996480172
Short name T483
Test name
Test status
Simulation time 69244307919 ps
CPU time 1507.8 seconds
Started May 30 01:19:32 PM PDT 24
Finished May 30 01:44:42 PM PDT 24
Peak memory 273416 kb
Host smart-b1530233-e5dc-4be3-a637-80189a29c840
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996480172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.996480172
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.1580517571
Short name T304
Test name
Test status
Simulation time 98630447605 ps
CPU time 338.48 seconds
Started May 30 01:19:34 PM PDT 24
Finished May 30 01:25:13 PM PDT 24
Peak memory 248816 kb
Host smart-e90bc74d-4776-40c9-89ce-d85bd61fb062
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580517571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.1580517571
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1795250804
Short name T363
Test name
Test status
Simulation time 1029241869 ps
CPU time 33.22 seconds
Started May 30 01:19:34 PM PDT 24
Finished May 30 01:20:08 PM PDT 24
Peak memory 248760 kb
Host smart-cb0b9d48-4f25-46ef-aa5c-b47ecddf5934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17952
50804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1795250804
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1495338364
Short name T44
Test name
Test status
Simulation time 800754845 ps
CPU time 40.58 seconds
Started May 30 01:19:34 PM PDT 24
Finished May 30 01:20:15 PM PDT 24
Peak memory 248588 kb
Host smart-e5c33f88-6c8f-4cb6-b4d2-390af4881d4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14953
38364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1495338364
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.3636045177
Short name T10
Test name
Test status
Simulation time 504394504 ps
CPU time 23.68 seconds
Started May 30 01:19:37 PM PDT 24
Finished May 30 01:20:02 PM PDT 24
Peak memory 268780 kb
Host smart-6e834737-8b88-4598-b2b8-0a359fa9b4f4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3636045177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3636045177
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.1545338158
Short name T471
Test name
Test status
Simulation time 406367874 ps
CPU time 38.07 seconds
Started May 30 01:19:36 PM PDT 24
Finished May 30 01:20:15 PM PDT 24
Peak memory 255840 kb
Host smart-385e77f8-cb74-4fc2-abfe-7955a87da9f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15453
38158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.1545338158
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3543223865
Short name T465
Test name
Test status
Simulation time 1651313139 ps
CPU time 22.96 seconds
Started May 30 01:19:34 PM PDT 24
Finished May 30 01:19:59 PM PDT 24
Peak memory 248756 kb
Host smart-cc4adc76-db67-497b-977a-11336ffbfceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35432
23865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3543223865
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3806239686
Short name T430
Test name
Test status
Simulation time 271906006522 ps
CPU time 1738.02 seconds
Started May 30 01:19:35 PM PDT 24
Finished May 30 01:48:35 PM PDT 24
Peak memory 285404 kb
Host smart-31ad6afa-b020-4e4c-89da-b01235de6551
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806239686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3806239686
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.547912835
Short name T524
Test name
Test status
Simulation time 3075762733 ps
CPU time 155.85 seconds
Started May 30 01:21:44 PM PDT 24
Finished May 30 01:24:20 PM PDT 24
Peak memory 256948 kb
Host smart-d998f936-154b-4bcd-a632-124c56bcb90e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54791
2835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.547912835
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.3611694037
Short name T372
Test name
Test status
Simulation time 902979786 ps
CPU time 29.06 seconds
Started May 30 01:21:43 PM PDT 24
Finished May 30 01:22:13 PM PDT 24
Peak memory 248764 kb
Host smart-e7f220ec-7848-426b-994e-e191a98a6098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36116
94037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3611694037
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2014845518
Short name T344
Test name
Test status
Simulation time 27490247406 ps
CPU time 1522.75 seconds
Started May 30 01:21:45 PM PDT 24
Finished May 30 01:47:09 PM PDT 24
Peak memory 272324 kb
Host smart-19e4152d-84ae-4746-9f8e-ef4a0421e09b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014845518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2014845518
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.769951452
Short name T438
Test name
Test status
Simulation time 35542208145 ps
CPU time 2308.29 seconds
Started May 30 01:21:46 PM PDT 24
Finished May 30 02:00:15 PM PDT 24
Peak memory 289300 kb
Host smart-6b92fe7d-23fa-4c15-bfab-01865e5a8e3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769951452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.769951452
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2464835299
Short name T274
Test name
Test status
Simulation time 35005208814 ps
CPU time 346.72 seconds
Started May 30 01:21:49 PM PDT 24
Finished May 30 01:27:36 PM PDT 24
Peak memory 255064 kb
Host smart-8354a7dc-fa80-43be-9f61-ce5f2a00f8e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464835299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2464835299
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.2614479058
Short name T681
Test name
Test status
Simulation time 490434211 ps
CPU time 8.43 seconds
Started May 30 01:21:53 PM PDT 24
Finished May 30 01:22:02 PM PDT 24
Peak memory 248764 kb
Host smart-bebd7756-63ba-418f-a3ce-76f6d7be99d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26144
79058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.2614479058
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3287079530
Short name T42
Test name
Test status
Simulation time 4895005290 ps
CPU time 47.49 seconds
Started May 30 01:21:49 PM PDT 24
Finished May 30 01:22:37 PM PDT 24
Peak memory 255944 kb
Host smart-4c2078c5-06f1-4ec4-838d-d6b949cc3a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32870
79530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3287079530
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.4214732260
Short name T378
Test name
Test status
Simulation time 1078975736 ps
CPU time 14.04 seconds
Started May 30 01:21:46 PM PDT 24
Finished May 30 01:22:01 PM PDT 24
Peak memory 254952 kb
Host smart-c92a5cf8-c5ad-4aea-9d91-b5678ff7cd6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42147
32260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.4214732260
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1841977178
Short name T413
Test name
Test status
Simulation time 1224945140 ps
CPU time 36.32 seconds
Started May 30 01:21:47 PM PDT 24
Finished May 30 01:22:24 PM PDT 24
Peak memory 248764 kb
Host smart-d663495b-da9a-49ea-9769-c7c898976dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18419
77178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1841977178
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.1273487933
Short name T402
Test name
Test status
Simulation time 54609174746 ps
CPU time 1236.54 seconds
Started May 30 01:21:43 PM PDT 24
Finished May 30 01:42:21 PM PDT 24
Peak memory 281528 kb
Host smart-8138fd4e-f445-40f7-aacb-299928f266fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273487933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1273487933
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2471411100
Short name T323
Test name
Test status
Simulation time 4045986532 ps
CPU time 223.03 seconds
Started May 30 01:21:47 PM PDT 24
Finished May 30 01:25:31 PM PDT 24
Peak memory 257000 kb
Host smart-87fba099-1b27-49f5-bf62-211169d8370a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24714
11100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2471411100
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.52150529
Short name T617
Test name
Test status
Simulation time 2340042596 ps
CPU time 77.08 seconds
Started May 30 01:21:45 PM PDT 24
Finished May 30 01:23:03 PM PDT 24
Peak memory 248772 kb
Host smart-cf881911-fc53-491b-bd3a-6a566230e2b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52150
529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.52150529
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.254531157
Short name T326
Test name
Test status
Simulation time 298072826579 ps
CPU time 1988.14 seconds
Started May 30 01:21:44 PM PDT 24
Finished May 30 01:54:53 PM PDT 24
Peak memory 272436 kb
Host smart-67b81ffa-0adf-452e-bc05-dce9a2cacbb1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254531157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.254531157
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2332234688
Short name T597
Test name
Test status
Simulation time 26207842737 ps
CPU time 1430.4 seconds
Started May 30 01:21:43 PM PDT 24
Finished May 30 01:45:35 PM PDT 24
Peak memory 269492 kb
Host smart-d1dd03db-2b31-49fc-a2ac-cba2da469809
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332234688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2332234688
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2659284985
Short name T313
Test name
Test status
Simulation time 18267438497 ps
CPU time 186.76 seconds
Started May 30 01:21:45 PM PDT 24
Finished May 30 01:24:53 PM PDT 24
Peak memory 248248 kb
Host smart-f6cc03c0-b896-4914-b68c-c0544001fd7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659284985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2659284985
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.2458609856
Short name T637
Test name
Test status
Simulation time 363950077 ps
CPU time 30.06 seconds
Started May 30 01:21:45 PM PDT 24
Finished May 30 01:22:16 PM PDT 24
Peak memory 248808 kb
Host smart-9164ed3b-5a1e-4d49-957d-1f484efd5436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24586
09856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.2458609856
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.464959793
Short name T636
Test name
Test status
Simulation time 2936341275 ps
CPU time 24.74 seconds
Started May 30 01:21:46 PM PDT 24
Finished May 30 01:22:12 PM PDT 24
Peak memory 255540 kb
Host smart-380cd071-2be2-40d9-82bf-96adf3e6c719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46495
9793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.464959793
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.3866329499
Short name T655
Test name
Test status
Simulation time 415893551 ps
CPU time 12.27 seconds
Started May 30 01:21:46 PM PDT 24
Finished May 30 01:21:59 PM PDT 24
Peak memory 254724 kb
Host smart-6f748e85-3dcc-46f9-80e3-9afe810df780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38663
29499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3866329499
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.3031168898
Short name T382
Test name
Test status
Simulation time 1795279368 ps
CPU time 30.86 seconds
Started May 30 01:21:54 PM PDT 24
Finished May 30 01:22:26 PM PDT 24
Peak memory 255948 kb
Host smart-687ff0fe-b140-4bd3-af20-1088b7fafc98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30311
68898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3031168898
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.2301596444
Short name T266
Test name
Test status
Simulation time 37429545107 ps
CPU time 2185.49 seconds
Started May 30 01:21:47 PM PDT 24
Finished May 30 01:58:14 PM PDT 24
Peak memory 305700 kb
Host smart-42a3548f-26ce-496b-b42f-400face49607
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301596444 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.2301596444
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.2680350919
Short name T544
Test name
Test status
Simulation time 186639251884 ps
CPU time 2463 seconds
Started May 30 01:21:59 PM PDT 24
Finished May 30 02:03:03 PM PDT 24
Peak memory 288908 kb
Host smart-13a0daf4-59d4-4deb-be3d-8ccad6ab17a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680350919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.2680350919
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.2658647220
Short name T286
Test name
Test status
Simulation time 1778720520 ps
CPU time 116.49 seconds
Started May 30 01:21:47 PM PDT 24
Finished May 30 01:23:44 PM PDT 24
Peak memory 256428 kb
Host smart-cd77b0e3-d4de-4031-9670-7a3f8882a1ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26586
47220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2658647220
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.58576535
Short name T234
Test name
Test status
Simulation time 115524825 ps
CPU time 3.72 seconds
Started May 30 01:21:45 PM PDT 24
Finished May 30 01:21:50 PM PDT 24
Peak memory 240576 kb
Host smart-5e30011e-3700-4dfa-8649-f5bba9a5c7a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58576
535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.58576535
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1545588469
Short name T550
Test name
Test status
Simulation time 42676294335 ps
CPU time 1651.85 seconds
Started May 30 01:21:59 PM PDT 24
Finished May 30 01:49:32 PM PDT 24
Peak memory 281596 kb
Host smart-afc12820-3f22-484a-a9c8-29e190c3baf9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545588469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1545588469
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.3145243074
Short name T96
Test name
Test status
Simulation time 46770998446 ps
CPU time 2601.54 seconds
Started May 30 01:22:00 PM PDT 24
Finished May 30 02:05:23 PM PDT 24
Peak memory 289540 kb
Host smart-bc8bb34f-332f-4796-a6ec-5fd3536a072f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145243074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3145243074
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2131277572
Short name T307
Test name
Test status
Simulation time 13003512659 ps
CPU time 509.42 seconds
Started May 30 01:22:03 PM PDT 24
Finished May 30 01:30:33 PM PDT 24
Peak memory 248008 kb
Host smart-20a6efa5-f124-466b-9af9-7aa8ca5e6222
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131277572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2131277572
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3623533435
Short name T523
Test name
Test status
Simulation time 316756683 ps
CPU time 11.17 seconds
Started May 30 01:21:46 PM PDT 24
Finished May 30 01:21:58 PM PDT 24
Peak memory 248764 kb
Host smart-957117fd-4827-45de-a8d9-caab2dc0ec1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36235
33435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3623533435
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2232978196
Short name T434
Test name
Test status
Simulation time 1145999360 ps
CPU time 18.42 seconds
Started May 30 01:21:46 PM PDT 24
Finished May 30 01:22:05 PM PDT 24
Peak memory 248648 kb
Host smart-14505cd4-8083-4a8d-8ba2-e6c5bb56721b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22329
78196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2232978196
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2075717263
Short name T284
Test name
Test status
Simulation time 260344242 ps
CPU time 16.25 seconds
Started May 30 01:21:47 PM PDT 24
Finished May 30 01:22:04 PM PDT 24
Peak memory 255236 kb
Host smart-e212a872-3588-4db2-8532-1b6ed2aad7d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20757
17263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2075717263
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.127453997
Short name T665
Test name
Test status
Simulation time 2197283823 ps
CPU time 11.87 seconds
Started May 30 01:21:45 PM PDT 24
Finished May 30 01:21:58 PM PDT 24
Peak memory 248952 kb
Host smart-c262b925-7833-47f3-a419-23b2d4eccca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12745
3997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.127453997
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.3985854816
Short name T256
Test name
Test status
Simulation time 17027716841 ps
CPU time 2021 seconds
Started May 30 01:22:01 PM PDT 24
Finished May 30 01:55:43 PM PDT 24
Peak memory 305764 kb
Host smart-f7288d2a-c737-4f2d-b69d-bc71d5a7da7d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985854816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.3985854816
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.3172390662
Short name T696
Test name
Test status
Simulation time 37051464076 ps
CPU time 2439.31 seconds
Started May 30 01:22:02 PM PDT 24
Finished May 30 02:02:42 PM PDT 24
Peak memory 289780 kb
Host smart-ea75986a-91c5-468a-a3cd-1a797d93fbda
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172390662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.3172390662
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.559484183
Short name T522
Test name
Test status
Simulation time 1092472316 ps
CPU time 96.99 seconds
Started May 30 01:22:02 PM PDT 24
Finished May 30 01:23:40 PM PDT 24
Peak memory 256864 kb
Host smart-e08b34b5-c87b-453f-b9a3-eaed80f9a91a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55948
4183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.559484183
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.778768537
Short name T398
Test name
Test status
Simulation time 773076126 ps
CPU time 46.11 seconds
Started May 30 01:21:59 PM PDT 24
Finished May 30 01:22:46 PM PDT 24
Peak memory 255808 kb
Host smart-7445c239-22e6-4e8a-8812-9c4dacbdb288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77876
8537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.778768537
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.665216781
Short name T649
Test name
Test status
Simulation time 59139422553 ps
CPU time 676.14 seconds
Started May 30 01:22:02 PM PDT 24
Finished May 30 01:33:19 PM PDT 24
Peak memory 265244 kb
Host smart-7bd319f3-9af6-4b5c-aa68-4e7350970532
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665216781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.665216781
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3138389666
Short name T580
Test name
Test status
Simulation time 14473334168 ps
CPU time 1123.23 seconds
Started May 30 01:21:59 PM PDT 24
Finished May 30 01:40:43 PM PDT 24
Peak memory 281560 kb
Host smart-26c6128c-4e39-452c-a1f8-1a201a19448a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138389666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3138389666
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.1236316595
Short name T487
Test name
Test status
Simulation time 703355140 ps
CPU time 20.56 seconds
Started May 30 01:22:00 PM PDT 24
Finished May 30 01:22:21 PM PDT 24
Peak memory 248776 kb
Host smart-56958995-5b2a-4da6-8ecf-f9d5fd9d752c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12363
16595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.1236316595
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2245805809
Short name T615
Test name
Test status
Simulation time 127971326 ps
CPU time 15.73 seconds
Started May 30 01:22:00 PM PDT 24
Finished May 30 01:22:16 PM PDT 24
Peak memory 248752 kb
Host smart-ffa22b10-4461-4904-94b6-a61e13e90553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22458
05809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2245805809
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1129156598
Short name T81
Test name
Test status
Simulation time 824378845 ps
CPU time 27.03 seconds
Started May 30 01:22:02 PM PDT 24
Finished May 30 01:22:29 PM PDT 24
Peak memory 248772 kb
Host smart-a6000b8a-9171-4e0a-9237-4ddb94212c0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11291
56598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1129156598
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2501162130
Short name T561
Test name
Test status
Simulation time 907449831 ps
CPU time 22.58 seconds
Started May 30 01:22:00 PM PDT 24
Finished May 30 01:22:24 PM PDT 24
Peak memory 248796 kb
Host smart-7d933f71-fda8-479f-aac1-7f9beb6148be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25011
62130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2501162130
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1779820368
Short name T660
Test name
Test status
Simulation time 201575307765 ps
CPU time 2655.33 seconds
Started May 30 01:22:00 PM PDT 24
Finished May 30 02:06:17 PM PDT 24
Peak memory 286732 kb
Host smart-9800b19d-bed0-426c-b891-5a4bcc1cfea3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779820368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1779820368
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.3440806526
Short name T182
Test name
Test status
Simulation time 179629316549 ps
CPU time 2085.86 seconds
Started May 30 01:21:59 PM PDT 24
Finished May 30 01:56:46 PM PDT 24
Peak memory 281912 kb
Host smart-d2a3ad7d-ef64-4e4c-84f4-1a745fab4f21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440806526 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.3440806526
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.993380376
Short name T380
Test name
Test status
Simulation time 73788355392 ps
CPU time 1211.39 seconds
Started May 30 01:22:02 PM PDT 24
Finished May 30 01:42:14 PM PDT 24
Peak memory 266232 kb
Host smart-fd15057e-243c-4703-9315-3f3a5ba29825
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993380376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.993380376
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3407626540
Short name T658
Test name
Test status
Simulation time 14908360609 ps
CPU time 254.82 seconds
Started May 30 01:22:00 PM PDT 24
Finished May 30 01:26:15 PM PDT 24
Peak memory 250984 kb
Host smart-de1a638c-5fc0-460d-8aa5-9060a642e450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34076
26540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3407626540
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.286312446
Short name T18
Test name
Test status
Simulation time 1330525902 ps
CPU time 16.94 seconds
Started May 30 01:22:00 PM PDT 24
Finished May 30 01:22:18 PM PDT 24
Peak memory 248724 kb
Host smart-3cfdf46d-5812-4fe3-aa16-357f7f57a3ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28631
2446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.286312446
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.2143307221
Short name T562
Test name
Test status
Simulation time 24566176577 ps
CPU time 1644.68 seconds
Started May 30 01:22:02 PM PDT 24
Finished May 30 01:49:27 PM PDT 24
Peak memory 273424 kb
Host smart-c01c00b4-ea50-401b-a3ee-a431febb78d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143307221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2143307221
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3396728265
Short name T585
Test name
Test status
Simulation time 93093998 ps
CPU time 10.14 seconds
Started May 30 01:21:59 PM PDT 24
Finished May 30 01:22:09 PM PDT 24
Peak memory 248776 kb
Host smart-dd618840-376a-4a45-ae87-0c5ee1196005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33967
28265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3396728265
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1615340739
Short name T437
Test name
Test status
Simulation time 563408775 ps
CPU time 31.49 seconds
Started May 30 01:22:01 PM PDT 24
Finished May 30 01:22:34 PM PDT 24
Peak memory 255776 kb
Host smart-ce629503-12a4-4bcd-8f56-7d0d393130ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16153
40739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1615340739
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.4136852059
Short name T263
Test name
Test status
Simulation time 329427419 ps
CPU time 12.04 seconds
Started May 30 01:22:00 PM PDT 24
Finished May 30 01:22:12 PM PDT 24
Peak memory 255696 kb
Host smart-409a5f10-6b4a-4ee9-964c-eb4b27d66977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41368
52059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.4136852059
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2120869300
Short name T533
Test name
Test status
Simulation time 702592254 ps
CPU time 39.86 seconds
Started May 30 01:22:00 PM PDT 24
Finished May 30 01:22:40 PM PDT 24
Peak memory 248752 kb
Host smart-2cfaa032-f6fa-486d-a2a2-24179b2e82ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21208
69300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2120869300
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1216664455
Short name T27
Test name
Test status
Simulation time 74893390625 ps
CPU time 1446.99 seconds
Started May 30 01:22:05 PM PDT 24
Finished May 30 01:46:13 PM PDT 24
Peak memory 289740 kb
Host smart-633df8ac-8f42-4848-85af-613dd629621b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216664455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1216664455
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.2944205453
Short name T183
Test name
Test status
Simulation time 230231357402 ps
CPU time 4719.64 seconds
Started May 30 01:22:01 PM PDT 24
Finished May 30 02:40:42 PM PDT 24
Peak memory 348344 kb
Host smart-8d0faec8-0d9a-41e2-9b0f-3029ab5d2f40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944205453 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.2944205453
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3200101352
Short name T488
Test name
Test status
Simulation time 84870296739 ps
CPU time 1386.38 seconds
Started May 30 01:22:01 PM PDT 24
Finished May 30 01:45:09 PM PDT 24
Peak memory 273324 kb
Host smart-9d1d3280-8934-414c-911a-72c3836a5f14
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200101352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3200101352
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3500995035
Short name T656
Test name
Test status
Simulation time 12595127392 ps
CPU time 158.08 seconds
Started May 30 01:22:03 PM PDT 24
Finished May 30 01:24:42 PM PDT 24
Peak memory 249832 kb
Host smart-0f9562b9-c314-4d38-b1a5-1df7d2cae5dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35009
95035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3500995035
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3435480636
Short name T669
Test name
Test status
Simulation time 1422954679 ps
CPU time 36.15 seconds
Started May 30 01:22:03 PM PDT 24
Finished May 30 01:22:40 PM PDT 24
Peak memory 248780 kb
Host smart-acf73e4b-5b63-420b-a94c-505f3553a295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34354
80636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3435480636
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.886799181
Short name T427
Test name
Test status
Simulation time 172849996664 ps
CPU time 2272.71 seconds
Started May 30 01:22:23 PM PDT 24
Finished May 30 02:00:16 PM PDT 24
Peak memory 282080 kb
Host smart-d39540da-a2c3-4697-8fce-d7c9be1b06ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886799181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.886799181
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.452792017
Short name T433
Test name
Test status
Simulation time 4408915531 ps
CPU time 179.78 seconds
Started May 30 01:22:00 PM PDT 24
Finished May 30 01:25:01 PM PDT 24
Peak memory 247192 kb
Host smart-7d34d9f4-46c4-464a-a81f-065b4460ebe9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452792017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.452792017
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.4187484249
Short name T366
Test name
Test status
Simulation time 329153708 ps
CPU time 32.95 seconds
Started May 30 01:22:00 PM PDT 24
Finished May 30 01:22:34 PM PDT 24
Peak memory 248776 kb
Host smart-96e1f8dd-88eb-4f0a-9647-88a7c4ae427d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41874
84249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.4187484249
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3947447698
Short name T111
Test name
Test status
Simulation time 1237379074 ps
CPU time 32.72 seconds
Started May 30 01:21:59 PM PDT 24
Finished May 30 01:22:33 PM PDT 24
Peak memory 248876 kb
Host smart-01535e9f-85c3-4d0a-b2ad-dbffb1d09389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39474
47698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3947447698
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.125380753
Short name T48
Test name
Test status
Simulation time 2011978241 ps
CPU time 12.58 seconds
Started May 30 01:22:01 PM PDT 24
Finished May 30 01:22:14 PM PDT 24
Peak memory 247316 kb
Host smart-7bfb01f7-bb7f-46ed-9291-db26e3133185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12538
0753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.125380753
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2526416859
Short name T445
Test name
Test status
Simulation time 1572538353 ps
CPU time 29.87 seconds
Started May 30 01:22:04 PM PDT 24
Finished May 30 01:22:35 PM PDT 24
Peak memory 248732 kb
Host smart-4b51d1eb-061a-4750-a5e5-45928599352b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25264
16859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2526416859
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2585161635
Short name T549
Test name
Test status
Simulation time 6526933592 ps
CPU time 103 seconds
Started May 30 01:22:23 PM PDT 24
Finished May 30 01:24:07 PM PDT 24
Peak memory 256956 kb
Host smart-b8648134-9dc3-49d2-9ba8-9824b3e53284
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585161635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2585161635
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.293557845
Short name T411
Test name
Test status
Simulation time 87218475442 ps
CPU time 1229.93 seconds
Started May 30 01:22:22 PM PDT 24
Finished May 30 01:42:53 PM PDT 24
Peak memory 273344 kb
Host smart-04c91d75-7106-49f7-85cf-e9275f804b9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293557845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.293557845
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.3082151007
Short name T367
Test name
Test status
Simulation time 868818223 ps
CPU time 31.33 seconds
Started May 30 01:22:14 PM PDT 24
Finished May 30 01:22:47 PM PDT 24
Peak memory 256068 kb
Host smart-1e439184-d2fc-4dd1-8606-7eeaf45340d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30821
51007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3082151007
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1711897118
Short name T365
Test name
Test status
Simulation time 730014519 ps
CPU time 20.05 seconds
Started May 30 01:22:23 PM PDT 24
Finished May 30 01:22:44 PM PDT 24
Peak memory 255956 kb
Host smart-2df45eb1-6ec2-4857-87aa-7324dc31d513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17118
97118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1711897118
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.3463763995
Short name T543
Test name
Test status
Simulation time 38419098368 ps
CPU time 804.64 seconds
Started May 30 01:22:23 PM PDT 24
Finished May 30 01:35:49 PM PDT 24
Peak memory 265216 kb
Host smart-5de07a8a-4023-4c6a-95a1-61ec2c0621a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463763995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3463763995
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.3514571123
Short name T621
Test name
Test status
Simulation time 108473634914 ps
CPU time 3357.02 seconds
Started May 30 01:22:23 PM PDT 24
Finished May 30 02:18:21 PM PDT 24
Peak memory 289848 kb
Host smart-cd886771-5af4-4392-b72a-162799730887
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514571123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3514571123
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.661032611
Short name T200
Test name
Test status
Simulation time 8130392714 ps
CPU time 195.29 seconds
Started May 30 01:22:23 PM PDT 24
Finished May 30 01:25:39 PM PDT 24
Peak memory 248264 kb
Host smart-e8c2e4d5-b4de-43d2-a2e5-51e881437907
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661032611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.661032611
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.2232663554
Short name T405
Test name
Test status
Simulation time 3107249537 ps
CPU time 28.74 seconds
Started May 30 01:22:23 PM PDT 24
Finished May 30 01:22:52 PM PDT 24
Peak memory 255016 kb
Host smart-ef0d9ada-6ca4-4c50-8824-54e8eeeeaf74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22326
63554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.2232663554
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.2672918546
Short name T45
Test name
Test status
Simulation time 846328646 ps
CPU time 61.26 seconds
Started May 30 01:22:24 PM PDT 24
Finished May 30 01:23:26 PM PDT 24
Peak memory 247372 kb
Host smart-ad832d2d-9b84-429f-9c23-fab304deea16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26729
18546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2672918546
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3287309659
Short name T512
Test name
Test status
Simulation time 142192767 ps
CPU time 23.5 seconds
Started May 30 01:22:24 PM PDT 24
Finished May 30 01:22:48 PM PDT 24
Peak memory 254680 kb
Host smart-4a34ec27-b216-4127-9c5f-69b512bf3a89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32873
09659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3287309659
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.3968686095
Short name T370
Test name
Test status
Simulation time 920158371 ps
CPU time 17.23 seconds
Started May 30 01:22:21 PM PDT 24
Finished May 30 01:22:39 PM PDT 24
Peak memory 248764 kb
Host smart-5a089c7a-ab5b-44ae-a736-f75ce0836db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39686
86095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3968686095
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1514852527
Short name T425
Test name
Test status
Simulation time 69325763416 ps
CPU time 1621.23 seconds
Started May 30 01:22:23 PM PDT 24
Finished May 30 01:49:25 PM PDT 24
Peak memory 288856 kb
Host smart-721e5690-0275-440b-8e62-142d70f2ea42
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514852527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1514852527
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1309284010
Short name T421
Test name
Test status
Simulation time 24495098268 ps
CPU time 1444.96 seconds
Started May 30 01:22:22 PM PDT 24
Finished May 30 01:46:28 PM PDT 24
Peak memory 272736 kb
Host smart-0c301a7a-55ef-43e3-88f3-5225b356a371
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309284010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1309284010
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3063446353
Short name T635
Test name
Test status
Simulation time 1384766620 ps
CPU time 45.3 seconds
Started May 30 01:22:22 PM PDT 24
Finished May 30 01:23:08 PM PDT 24
Peak memory 248856 kb
Host smart-dcee8983-4bc8-479a-8055-7cec6814bffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30634
46353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3063446353
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3151473711
Short name T582
Test name
Test status
Simulation time 1787869339 ps
CPU time 52.19 seconds
Started May 30 01:22:23 PM PDT 24
Finished May 30 01:23:16 PM PDT 24
Peak memory 248760 kb
Host smart-477a1f79-337d-4e49-80e3-de9b4fd99161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31514
73711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3151473711
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3130069831
Short name T339
Test name
Test status
Simulation time 163417110024 ps
CPU time 2225.23 seconds
Started May 30 01:22:23 PM PDT 24
Finished May 30 01:59:30 PM PDT 24
Peak memory 273464 kb
Host smart-b4b7fe26-1541-4018-b288-bbf83aab1f34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130069831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3130069831
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.2587244757
Short name T371
Test name
Test status
Simulation time 9623496724 ps
CPU time 1128.22 seconds
Started May 30 01:22:23 PM PDT 24
Finished May 30 01:41:13 PM PDT 24
Peak memory 269628 kb
Host smart-da5411ff-9c58-404a-84b8-ed87685f63df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587244757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2587244757
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2322400092
Short name T239
Test name
Test status
Simulation time 4945366568 ps
CPU time 210.93 seconds
Started May 30 01:22:24 PM PDT 24
Finished May 30 01:25:56 PM PDT 24
Peak memory 248224 kb
Host smart-68ac2b4b-a2d4-41f2-9279-218cd832c0b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322400092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2322400092
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.654570589
Short name T469
Test name
Test status
Simulation time 517140342 ps
CPU time 17.67 seconds
Started May 30 01:22:23 PM PDT 24
Finished May 30 01:22:41 PM PDT 24
Peak memory 248828 kb
Host smart-82fa6d51-0252-44e9-ab6e-7d047891ce98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65457
0589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.654570589
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1976127873
Short name T453
Test name
Test status
Simulation time 7888380715 ps
CPU time 50.61 seconds
Started May 30 01:22:22 PM PDT 24
Finished May 30 01:23:13 PM PDT 24
Peak memory 247700 kb
Host smart-65c375d3-27f7-4c7d-bfa4-07b924aca749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19761
27873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1976127873
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.605167811
Short name T572
Test name
Test status
Simulation time 531848334 ps
CPU time 18.32 seconds
Started May 30 01:22:22 PM PDT 24
Finished May 30 01:22:41 PM PDT 24
Peak memory 248792 kb
Host smart-594f0931-3567-4fd9-8776-e601f267d283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60516
7811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.605167811
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.743621399
Short name T704
Test name
Test status
Simulation time 125882204 ps
CPU time 6.07 seconds
Started May 30 01:22:23 PM PDT 24
Finished May 30 01:22:30 PM PDT 24
Peak memory 240572 kb
Host smart-d22683ef-73be-4cce-8e48-3831ad84a69d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74362
1399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.743621399
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2139599481
Short name T249
Test name
Test status
Simulation time 13083911208 ps
CPU time 338.57 seconds
Started May 30 01:22:24 PM PDT 24
Finished May 30 01:28:03 PM PDT 24
Peak memory 257080 kb
Host smart-a7948777-f01f-41a7-a34f-e32209dfbfb7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139599481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2139599481
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3354207813
Short name T397
Test name
Test status
Simulation time 53984800203 ps
CPU time 1534.74 seconds
Started May 30 01:22:34 PM PDT 24
Finished May 30 01:48:09 PM PDT 24
Peak memory 289348 kb
Host smart-5a3740e8-d58f-4d2b-b198-75491ed8a8ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354207813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3354207813
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.631165359
Short name T186
Test name
Test status
Simulation time 4357600553 ps
CPU time 131.35 seconds
Started May 30 01:22:35 PM PDT 24
Finished May 30 01:24:47 PM PDT 24
Peak memory 248848 kb
Host smart-9ae7c77d-5af6-418a-b39e-34ccf7e358b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63116
5359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.631165359
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2044309456
Short name T78
Test name
Test status
Simulation time 1650722228 ps
CPU time 30.72 seconds
Started May 30 01:22:24 PM PDT 24
Finished May 30 01:22:56 PM PDT 24
Peak memory 248780 kb
Host smart-0f573b24-f7e9-4285-aaab-c1b0eaf57ecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20443
09456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2044309456
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.3505547141
Short name T271
Test name
Test status
Simulation time 111582190807 ps
CPU time 1709.02 seconds
Started May 30 01:22:34 PM PDT 24
Finished May 30 01:51:04 PM PDT 24
Peak memory 289272 kb
Host smart-0bf1deab-cf80-4d29-aed2-bc10685dd10f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505547141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.3505547141
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2166147276
Short name T464
Test name
Test status
Simulation time 31922964196 ps
CPU time 363.32 seconds
Started May 30 01:22:34 PM PDT 24
Finished May 30 01:28:38 PM PDT 24
Peak memory 248272 kb
Host smart-66ee16dd-68b9-42fd-9a76-c6ed71d59b48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166147276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2166147276
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3369044157
Short name T374
Test name
Test status
Simulation time 1369604457 ps
CPU time 21.14 seconds
Started May 30 01:22:25 PM PDT 24
Finished May 30 01:22:46 PM PDT 24
Peak memory 248760 kb
Host smart-4a43e755-8574-40df-8621-61365b3643ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33690
44157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3369044157
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.1598618953
Short name T86
Test name
Test status
Simulation time 830050260 ps
CPU time 49.07 seconds
Started May 30 01:22:26 PM PDT 24
Finished May 30 01:23:16 PM PDT 24
Peak memory 248748 kb
Host smart-7a941ae4-7f2c-473e-801b-9be41567edec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15986
18953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1598618953
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.894488915
Short name T671
Test name
Test status
Simulation time 546762335 ps
CPU time 36.64 seconds
Started May 30 01:22:37 PM PDT 24
Finished May 30 01:23:15 PM PDT 24
Peak memory 255964 kb
Host smart-174f5b87-5129-4da9-9f91-bf5a7db1bfb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89448
8915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.894488915
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.1352924223
Short name T589
Test name
Test status
Simulation time 2887894498 ps
CPU time 55.22 seconds
Started May 30 01:22:23 PM PDT 24
Finished May 30 01:23:20 PM PDT 24
Peak memory 248708 kb
Host smart-aa88116e-395a-4b55-b08f-2ccaa32817bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13529
24223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.1352924223
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1907703535
Short name T282
Test name
Test status
Simulation time 164377697762 ps
CPU time 3413.64 seconds
Started May 30 01:22:33 PM PDT 24
Finished May 30 02:19:28 PM PDT 24
Peak memory 304560 kb
Host smart-822476b0-4846-4b2a-acbc-de5ac5946c46
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907703535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1907703535
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.774104313
Short name T626
Test name
Test status
Simulation time 68780369143 ps
CPU time 2381.89 seconds
Started May 30 01:22:34 PM PDT 24
Finished May 30 02:02:17 PM PDT 24
Peak memory 289216 kb
Host smart-e7ad8e22-5c91-4b26-bd59-b371dcb5372f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774104313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.774104313
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.2109977460
Short name T424
Test name
Test status
Simulation time 2070058008 ps
CPU time 115.96 seconds
Started May 30 01:22:34 PM PDT 24
Finished May 30 01:24:31 PM PDT 24
Peak memory 249232 kb
Host smart-3c287240-a991-419c-8d96-4750473a09ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21099
77460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2109977460
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2312757213
Short name T73
Test name
Test status
Simulation time 955071020 ps
CPU time 31.88 seconds
Started May 30 01:22:33 PM PDT 24
Finished May 30 01:23:06 PM PDT 24
Peak memory 255660 kb
Host smart-84843605-218c-4ca7-a86b-71885fe4737c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23127
57213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2312757213
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.145701661
Short name T312
Test name
Test status
Simulation time 88659557353 ps
CPU time 2673.7 seconds
Started May 30 01:22:38 PM PDT 24
Finished May 30 02:07:14 PM PDT 24
Peak memory 289044 kb
Host smart-a24b00a8-fa0c-4771-9896-b68b97342e7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145701661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.145701661
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2360415632
Short name T667
Test name
Test status
Simulation time 27369051253 ps
CPU time 1830.88 seconds
Started May 30 01:22:38 PM PDT 24
Finished May 30 01:53:11 PM PDT 24
Peak memory 273432 kb
Host smart-8d59bb7e-fee5-45ea-b49f-b69d9e8ddcfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360415632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2360415632
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1670045348
Short name T311
Test name
Test status
Simulation time 10595741727 ps
CPU time 416.43 seconds
Started May 30 01:22:35 PM PDT 24
Finished May 30 01:29:32 PM PDT 24
Peak memory 248228 kb
Host smart-44c0b3eb-a868-49f3-8bde-8de9669d9485
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670045348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1670045348
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.690625364
Short name T687
Test name
Test status
Simulation time 433391979 ps
CPU time 16.89 seconds
Started May 30 01:22:33 PM PDT 24
Finished May 30 01:22:50 PM PDT 24
Peak memory 253376 kb
Host smart-9288e8db-d3fb-45de-bf0a-84402cec8a89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69062
5364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.690625364
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1224534984
Short name T517
Test name
Test status
Simulation time 160437985 ps
CPU time 3.97 seconds
Started May 30 01:22:38 PM PDT 24
Finished May 30 01:22:44 PM PDT 24
Peak memory 240568 kb
Host smart-bafe0786-ccc8-408b-a43b-03bdbf752cc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12245
34984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1224534984
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.4225133056
Short name T283
Test name
Test status
Simulation time 853871421 ps
CPU time 34.35 seconds
Started May 30 01:22:35 PM PDT 24
Finished May 30 01:23:10 PM PDT 24
Peak memory 255920 kb
Host smart-a775c269-c29a-4fb2-b0fb-096213d75957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42251
33056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.4225133056
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.415543380
Short name T518
Test name
Test status
Simulation time 5158598861 ps
CPU time 77.91 seconds
Started May 30 01:22:33 PM PDT 24
Finished May 30 01:23:52 PM PDT 24
Peak memory 256108 kb
Host smart-005ff7f0-26d3-4941-b4a5-5ec0a26c51b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41554
3380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.415543380
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.1106211089
Short name T203
Test name
Test status
Simulation time 321614656806 ps
CPU time 7691.93 seconds
Started May 30 01:22:38 PM PDT 24
Finished May 30 03:30:52 PM PDT 24
Peak memory 354768 kb
Host smart-2e5b9fbd-3aac-47b2-a5d1-c2f40aab60f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106211089 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.1106211089
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.68459416
Short name T220
Test name
Test status
Simulation time 31321602 ps
CPU time 2.99 seconds
Started May 30 01:19:55 PM PDT 24
Finished May 30 01:19:59 PM PDT 24
Peak memory 248924 kb
Host smart-989abe24-e4ec-41a8-92c5-d5d9d51c2940
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=68459416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.68459416
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3713712703
Short name T116
Test name
Test status
Simulation time 9897563162 ps
CPU time 906.98 seconds
Started May 30 01:19:34 PM PDT 24
Finished May 30 01:34:42 PM PDT 24
Peak memory 268296 kb
Host smart-476ae81d-94e1-4d2c-9bdd-f91ac46f8655
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713712703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3713712703
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2973503243
Short name T237
Test name
Test status
Simulation time 2091006842 ps
CPU time 43.31 seconds
Started May 30 01:19:37 PM PDT 24
Finished May 30 01:20:21 PM PDT 24
Peak memory 248772 kb
Host smart-f7f9a970-6993-4a01-ba84-a311f866c297
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2973503243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2973503243
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.1297265309
Short name T410
Test name
Test status
Simulation time 1061984447 ps
CPU time 57.13 seconds
Started May 30 01:19:32 PM PDT 24
Finished May 30 01:20:30 PM PDT 24
Peak memory 256812 kb
Host smart-2d227022-f6d1-48ac-a843-3b1faac64331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12972
65309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.1297265309
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.1946545588
Short name T688
Test name
Test status
Simulation time 904592557 ps
CPU time 9.01 seconds
Started May 30 01:19:38 PM PDT 24
Finished May 30 01:19:48 PM PDT 24
Peak memory 251716 kb
Host smart-5d20a30d-ddf0-47de-be61-b4ce0b0bf394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19465
45588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1946545588
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1484458520
Short name T345
Test name
Test status
Simulation time 53853465364 ps
CPU time 1082.77 seconds
Started May 30 01:19:32 PM PDT 24
Finished May 30 01:37:37 PM PDT 24
Peak memory 272764 kb
Host smart-38dd2c7d-9fde-4995-b8a6-2f25f2aac1d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484458520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1484458520
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.4218806298
Short name T428
Test name
Test status
Simulation time 55025137517 ps
CPU time 1019.23 seconds
Started May 30 01:19:34 PM PDT 24
Finished May 30 01:36:35 PM PDT 24
Peak memory 273436 kb
Host smart-2e44b397-709e-45d7-90ea-6428e4f76677
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218806298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.4218806298
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.3353202904
Short name T299
Test name
Test status
Simulation time 20922032927 ps
CPU time 167.47 seconds
Started May 30 01:19:32 PM PDT 24
Finished May 30 01:22:21 PM PDT 24
Peak memory 248232 kb
Host smart-eeebe971-967f-469f-a43a-a9c3bf9e5986
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353202904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3353202904
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1968547158
Short name T396
Test name
Test status
Simulation time 3437399227 ps
CPU time 47.24 seconds
Started May 30 01:19:36 PM PDT 24
Finished May 30 01:20:24 PM PDT 24
Peak memory 248776 kb
Host smart-2642acd3-9335-419f-a9f3-6b5e0c73704a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19685
47158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1968547158
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3412938511
Short name T566
Test name
Test status
Simulation time 168871857 ps
CPU time 20.83 seconds
Started May 30 01:19:34 PM PDT 24
Finished May 30 01:19:56 PM PDT 24
Peak memory 255976 kb
Host smart-586547d3-5113-4944-bfe9-9c28f4724231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34129
38511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3412938511
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.1535791365
Short name T601
Test name
Test status
Simulation time 1675746527 ps
CPU time 26.17 seconds
Started May 30 01:19:37 PM PDT 24
Finished May 30 01:20:04 PM PDT 24
Peak memory 255912 kb
Host smart-44329f09-8fc6-4898-bf96-ca7a47186923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15357
91365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1535791365
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.990206359
Short name T362
Test name
Test status
Simulation time 250823683 ps
CPU time 14.67 seconds
Started May 30 01:19:36 PM PDT 24
Finished May 30 01:19:52 PM PDT 24
Peak memory 255888 kb
Host smart-8f35b40e-282d-4704-aa63-9d74e1daba45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99020
6359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.990206359
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3309870510
Short name T690
Test name
Test status
Simulation time 872955622 ps
CPU time 26.48 seconds
Started May 30 01:19:36 PM PDT 24
Finished May 30 01:20:04 PM PDT 24
Peak memory 254880 kb
Host smart-01950d1f-0c6f-4463-be8e-f754cf465b9f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309870510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3309870510
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.965624226
Short name T257
Test name
Test status
Simulation time 943801611311 ps
CPU time 9557.56 seconds
Started May 30 01:19:56 PM PDT 24
Finished May 30 03:59:15 PM PDT 24
Peak memory 354524 kb
Host smart-cf8bbf04-574d-4904-8490-d90a0a90ee55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965624226 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.965624226
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.3185151897
Short name T218
Test name
Test status
Simulation time 82061869 ps
CPU time 3.56 seconds
Started May 30 01:19:54 PM PDT 24
Finished May 30 01:19:58 PM PDT 24
Peak memory 248908 kb
Host smart-36c9f2bc-c559-4bac-8b15-f8193822c4d5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3185151897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3185151897
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.937050579
Short name T516
Test name
Test status
Simulation time 13840293814 ps
CPU time 1407.69 seconds
Started May 30 01:19:59 PM PDT 24
Finished May 30 01:43:28 PM PDT 24
Peak memory 289560 kb
Host smart-35231384-5a87-423d-88fa-4b8e6955f8ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937050579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.937050579
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1342775706
Short name T519
Test name
Test status
Simulation time 842201737 ps
CPU time 33.6 seconds
Started May 30 01:19:57 PM PDT 24
Finished May 30 01:20:31 PM PDT 24
Peak memory 248752 kb
Host smart-62d1e7a3-43ef-45ab-912f-9591a4817bf7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1342775706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1342775706
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.773565281
Short name T245
Test name
Test status
Simulation time 24196687069 ps
CPU time 312.28 seconds
Started May 30 01:19:55 PM PDT 24
Finished May 30 01:25:08 PM PDT 24
Peak memory 251184 kb
Host smart-9dfc60ab-a0c7-43a4-b4ae-53d49838898b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77356
5281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.773565281
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2025429710
Short name T702
Test name
Test status
Simulation time 529296281 ps
CPU time 8.49 seconds
Started May 30 01:19:59 PM PDT 24
Finished May 30 01:20:09 PM PDT 24
Peak memory 250900 kb
Host smart-fa5a1009-28c7-402e-b160-89785d280f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20254
29710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2025429710
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.685925834
Short name T653
Test name
Test status
Simulation time 36877148790 ps
CPU time 898.62 seconds
Started May 30 01:19:54 PM PDT 24
Finished May 30 01:34:53 PM PDT 24
Peak memory 273288 kb
Host smart-cb61fa5f-8247-4b6e-8bf0-3c59d4cacb8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685925834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.685925834
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.986382424
Short name T707
Test name
Test status
Simulation time 50138208324 ps
CPU time 1500.69 seconds
Started May 30 01:19:54 PM PDT 24
Finished May 30 01:44:55 PM PDT 24
Peak memory 273464 kb
Host smart-5a80bb7f-2483-4d60-a7d8-cc3af9085f72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986382424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.986382424
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3425845001
Short name T672
Test name
Test status
Simulation time 44471138834 ps
CPU time 525.16 seconds
Started May 30 01:19:53 PM PDT 24
Finished May 30 01:28:39 PM PDT 24
Peak memory 248308 kb
Host smart-140e4af7-4984-45fb-8729-5ada446b2491
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425845001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3425845001
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2411906668
Short name T699
Test name
Test status
Simulation time 416528427 ps
CPU time 23.22 seconds
Started May 30 01:19:55 PM PDT 24
Finished May 30 01:20:19 PM PDT 24
Peak memory 248752 kb
Host smart-3f6d7c17-8d65-4550-968d-f3a875d22051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24119
06668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2411906668
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1917591518
Short name T269
Test name
Test status
Simulation time 1267308514 ps
CPU time 69.31 seconds
Started May 30 01:19:59 PM PDT 24
Finished May 30 01:21:09 PM PDT 24
Peak memory 248728 kb
Host smart-930ed355-ad4e-4d83-9bae-236973a07554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19175
91518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1917591518
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.3332792830
Short name T479
Test name
Test status
Simulation time 294286630 ps
CPU time 25.05 seconds
Started May 30 01:19:53 PM PDT 24
Finished May 30 01:20:19 PM PDT 24
Peak memory 247592 kb
Host smart-9c2aec9d-dfff-4838-83bc-4f2fcdb859de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33327
92830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.3332792830
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.4169886360
Short name T448
Test name
Test status
Simulation time 1597063202 ps
CPU time 47.11 seconds
Started May 30 01:19:54 PM PDT 24
Finished May 30 01:20:41 PM PDT 24
Peak memory 248760 kb
Host smart-53f44536-cc30-41f8-92ed-ba99ed80535d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41698
86360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.4169886360
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.3030892578
Short name T258
Test name
Test status
Simulation time 81870153403 ps
CPU time 1269.98 seconds
Started May 30 01:19:54 PM PDT 24
Finished May 30 01:41:05 PM PDT 24
Peak memory 273180 kb
Host smart-b95e74e8-3394-4333-b801-bc898b5a9389
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030892578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.3030892578
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.2003004448
Short name T210
Test name
Test status
Simulation time 101061299 ps
CPU time 3.98 seconds
Started May 30 01:19:56 PM PDT 24
Finished May 30 01:20:01 PM PDT 24
Peak memory 248872 kb
Host smart-2ace69f3-3ed6-4945-8f69-2d4c8c893e80
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2003004448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2003004448
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1636225747
Short name T58
Test name
Test status
Simulation time 20661832862 ps
CPU time 901.92 seconds
Started May 30 01:19:56 PM PDT 24
Finished May 30 01:34:59 PM PDT 24
Peak memory 289364 kb
Host smart-9c6dace3-69d3-4429-b0e1-24cd54cbc24e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636225747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1636225747
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.4004065521
Short name T547
Test name
Test status
Simulation time 3262805963 ps
CPU time 11.49 seconds
Started May 30 01:19:58 PM PDT 24
Finished May 30 01:20:10 PM PDT 24
Peak memory 248828 kb
Host smart-dad98b95-004f-43f7-ab71-62e49b90632f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4004065521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.4004065521
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.3300864770
Short name T440
Test name
Test status
Simulation time 504333032 ps
CPU time 30.37 seconds
Started May 30 01:19:55 PM PDT 24
Finished May 30 01:20:26 PM PDT 24
Peak memory 256160 kb
Host smart-18cd7aa7-32f0-4322-b780-e4e6eeba2f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33008
64770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.3300864770
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2412770934
Short name T600
Test name
Test status
Simulation time 221195248 ps
CPU time 21.81 seconds
Started May 30 01:19:56 PM PDT 24
Finished May 30 01:20:19 PM PDT 24
Peak memory 248768 kb
Host smart-cc7554d1-c5d3-40fd-92f4-3fbff7b18933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24127
70934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2412770934
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.117789609
Short name T338
Test name
Test status
Simulation time 30661144074 ps
CPU time 1838.74 seconds
Started May 30 01:19:57 PM PDT 24
Finished May 30 01:50:36 PM PDT 24
Peak memory 282600 kb
Host smart-35543d44-a609-4ebc-8092-e64ad102a1bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117789609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.117789609
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.593944201
Short name T115
Test name
Test status
Simulation time 33701920541 ps
CPU time 1023.17 seconds
Started May 30 01:19:58 PM PDT 24
Finished May 30 01:37:03 PM PDT 24
Peak memory 273164 kb
Host smart-8a4170de-6483-43b2-92e2-f874919069ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593944201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.593944201
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1608145624
Short name T310
Test name
Test status
Simulation time 17654045470 ps
CPU time 363.23 seconds
Started May 30 01:19:55 PM PDT 24
Finished May 30 01:26:00 PM PDT 24
Peak memory 247204 kb
Host smart-f5f28c03-cf0c-4da9-8ff0-38934b97b740
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608145624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1608145624
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3917232126
Short name T406
Test name
Test status
Simulation time 363544792 ps
CPU time 13.39 seconds
Started May 30 01:19:59 PM PDT 24
Finished May 30 01:20:13 PM PDT 24
Peak memory 248732 kb
Host smart-da018689-ffd9-48a7-8862-d31261449a93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39172
32126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3917232126
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.1441612905
Short name T268
Test name
Test status
Simulation time 92771876 ps
CPU time 10.6 seconds
Started May 30 01:19:56 PM PDT 24
Finished May 30 01:20:08 PM PDT 24
Peak memory 255616 kb
Host smart-4594a9da-930a-4d58-a127-4f2ef591a95b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14416
12905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1441612905
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.712351634
Short name T260
Test name
Test status
Simulation time 993045099 ps
CPU time 36.13 seconds
Started May 30 01:19:54 PM PDT 24
Finished May 30 01:20:31 PM PDT 24
Peak memory 254812 kb
Host smart-0dbbc803-7511-495a-ad11-48759f7cc231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71235
1634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.712351634
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.1927962867
Short name T594
Test name
Test status
Simulation time 62636190 ps
CPU time 6.16 seconds
Started May 30 01:19:56 PM PDT 24
Finished May 30 01:20:04 PM PDT 24
Peak memory 250620 kb
Host smart-10508182-7d66-47e1-97a3-ddbed05e2a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19279
62867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1927962867
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2248242576
Short name T113
Test name
Test status
Simulation time 58986456140 ps
CPU time 3146.16 seconds
Started May 30 01:19:55 PM PDT 24
Finished May 30 02:12:23 PM PDT 24
Peak memory 289756 kb
Host smart-cfbcd3e3-2f8b-43b1-83db-c70d2adda49a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248242576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2248242576
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.2189234814
Short name T211
Test name
Test status
Simulation time 13295989 ps
CPU time 2.32 seconds
Started May 30 01:19:56 PM PDT 24
Finished May 30 01:20:00 PM PDT 24
Peak memory 248920 kb
Host smart-1d1a2197-c41c-4947-be9c-baa245a60f40
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2189234814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2189234814
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1331035493
Short name T493
Test name
Test status
Simulation time 30987039943 ps
CPU time 1125.53 seconds
Started May 30 01:19:56 PM PDT 24
Finished May 30 01:38:43 PM PDT 24
Peak memory 265204 kb
Host smart-6c1a0fd0-7d4a-48fa-8b23-4eb197f26145
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331035493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1331035493
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.338090735
Short name T386
Test name
Test status
Simulation time 860889765 ps
CPU time 36.44 seconds
Started May 30 01:19:55 PM PDT 24
Finished May 30 01:20:33 PM PDT 24
Peak memory 248784 kb
Host smart-bd3c69cf-fa11-4ba2-890d-2de67404d286
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=338090735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.338090735
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.1200670414
Short name T435
Test name
Test status
Simulation time 36780276472 ps
CPU time 304.18 seconds
Started May 30 01:19:56 PM PDT 24
Finished May 30 01:25:02 PM PDT 24
Peak memory 250832 kb
Host smart-7f8750c2-3515-4c35-b0c6-ecf24f2a1c8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12006
70414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1200670414
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.1322644500
Short name T71
Test name
Test status
Simulation time 4768538409 ps
CPU time 26.14 seconds
Started May 30 01:19:54 PM PDT 24
Finished May 30 01:20:21 PM PDT 24
Peak memory 248832 kb
Host smart-8ad6862e-15cb-412d-ad21-1a1f071a4550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13226
44500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.1322644500
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.3284228780
Short name T333
Test name
Test status
Simulation time 530481316668 ps
CPU time 2202.03 seconds
Started May 30 01:19:59 PM PDT 24
Finished May 30 01:56:42 PM PDT 24
Peak memory 282972 kb
Host smart-610eb0bb-53c2-4fba-9b0a-87c80747a782
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284228780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3284228780
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.2832693378
Short name T504
Test name
Test status
Simulation time 135581911177 ps
CPU time 2016.7 seconds
Started May 30 01:19:55 PM PDT 24
Finished May 30 01:53:32 PM PDT 24
Peak memory 288968 kb
Host smart-5a25b692-31ff-4518-b43c-7cf03f00d81b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832693378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2832693378
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.2291385943
Short name T477
Test name
Test status
Simulation time 7279501876 ps
CPU time 76.26 seconds
Started May 30 01:19:55 PM PDT 24
Finished May 30 01:21:13 PM PDT 24
Peak memory 248188 kb
Host smart-7602d507-7255-4018-b42c-661d3aa84b0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291385943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.2291385943
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3275473026
Short name T633
Test name
Test status
Simulation time 428839536 ps
CPU time 11.01 seconds
Started May 30 01:19:57 PM PDT 24
Finished May 30 01:20:09 PM PDT 24
Peak memory 248716 kb
Host smart-26aa089e-2588-47b3-affa-e9b605b507c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32754
73026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3275473026
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3358590194
Short name T230
Test name
Test status
Simulation time 304376842 ps
CPU time 17.18 seconds
Started May 30 01:19:57 PM PDT 24
Finished May 30 01:20:15 PM PDT 24
Peak memory 248760 kb
Host smart-5644c2b3-faa3-48ac-b81d-fef2ca654f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33585
90194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3358590194
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.1630958816
Short name T399
Test name
Test status
Simulation time 91707182 ps
CPU time 7.62 seconds
Started May 30 01:19:55 PM PDT 24
Finished May 30 01:20:04 PM PDT 24
Peak memory 251620 kb
Host smart-d6f2f5a7-31ce-4bea-b696-6395fa605504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16309
58816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1630958816
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.1532205290
Short name T558
Test name
Test status
Simulation time 561114616 ps
CPU time 20.2 seconds
Started May 30 01:19:57 PM PDT 24
Finished May 30 01:20:18 PM PDT 24
Peak memory 248916 kb
Host smart-99b1a0d7-d6ed-427e-a45e-5b54f5b63fb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15322
05290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1532205290
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.333349855
Short name T569
Test name
Test status
Simulation time 2405476196 ps
CPU time 235.87 seconds
Started May 30 01:19:59 PM PDT 24
Finished May 30 01:23:56 PM PDT 24
Peak memory 256980 kb
Host smart-c0e04b5a-3a30-4fa8-b070-8afcb22e7539
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333349855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand
ler_stress_all.333349855
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.2313305577
Short name T207
Test name
Test status
Simulation time 37934214 ps
CPU time 3.68 seconds
Started May 30 01:19:56 PM PDT 24
Finished May 30 01:20:01 PM PDT 24
Peak memory 248836 kb
Host smart-ac21bef6-e2d9-40f4-8891-a29abf9ee342
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2313305577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2313305577
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.4043358607
Short name T68
Test name
Test status
Simulation time 52429723212 ps
CPU time 1296.21 seconds
Started May 30 01:20:00 PM PDT 24
Finished May 30 01:41:37 PM PDT 24
Peak memory 281632 kb
Host smart-83fc5eab-d842-4382-a29d-416e3052fd8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043358607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.4043358607
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1796838799
Short name T620
Test name
Test status
Simulation time 752100585 ps
CPU time 35.62 seconds
Started May 30 01:19:55 PM PDT 24
Finished May 30 01:20:32 PM PDT 24
Peak memory 248768 kb
Host smart-fa2d95c6-26bd-4e4f-8c9c-6efa7508f26a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1796838799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1796838799
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.4132323760
Short name T265
Test name
Test status
Simulation time 2693485177 ps
CPU time 133.52 seconds
Started May 30 01:19:54 PM PDT 24
Finished May 30 01:22:09 PM PDT 24
Peak memory 256948 kb
Host smart-f44f6b15-8910-46dc-b33b-0fba5edf8286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41323
23760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.4132323760
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.15901706
Short name T76
Test name
Test status
Simulation time 335697308 ps
CPU time 5.49 seconds
Started May 30 01:19:55 PM PDT 24
Finished May 30 01:20:02 PM PDT 24
Peak memory 240560 kb
Host smart-92fd4057-b10d-45f4-80b0-7cd1de00d777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15901
706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.15901706
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2015842846
Short name T598
Test name
Test status
Simulation time 168310606404 ps
CPU time 1246.06 seconds
Started May 30 01:19:58 PM PDT 24
Finished May 30 01:40:45 PM PDT 24
Peak memory 289404 kb
Host smart-acff6a82-118e-4980-9783-64d7a1dde869
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015842846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2015842846
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2768263749
Short name T657
Test name
Test status
Simulation time 9204470100 ps
CPU time 888.33 seconds
Started May 30 01:19:55 PM PDT 24
Finished May 30 01:34:44 PM PDT 24
Peak memory 271932 kb
Host smart-c7e4c0a8-9d84-4e00-9adf-be0fd3a8f2b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768263749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2768263749
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3756865880
Short name T225
Test name
Test status
Simulation time 29277316524 ps
CPU time 312.35 seconds
Started May 30 01:19:56 PM PDT 24
Finished May 30 01:25:10 PM PDT 24
Peak memory 248164 kb
Host smart-4694d5cf-a7a6-4c0b-9c58-03fd8f0436dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756865880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3756865880
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.1624211134
Short name T466
Test name
Test status
Simulation time 787921925 ps
CPU time 45.05 seconds
Started May 30 01:19:59 PM PDT 24
Finished May 30 01:20:45 PM PDT 24
Peak memory 256128 kb
Host smart-a9f2c82d-f30b-419f-9063-dbf003a2e4db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16242
11134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1624211134
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.577217588
Short name T695
Test name
Test status
Simulation time 480734316 ps
CPU time 6.76 seconds
Started May 30 01:19:55 PM PDT 24
Finished May 30 01:20:02 PM PDT 24
Peak memory 240668 kb
Host smart-946bcceb-5a0a-4f4a-a447-f958ea8a4970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57721
7588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.577217588
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.637122575
Short name T238
Test name
Test status
Simulation time 3579746884 ps
CPU time 53.2 seconds
Started May 30 01:19:56 PM PDT 24
Finished May 30 01:20:50 PM PDT 24
Peak memory 249180 kb
Host smart-2fac4bb6-7e8c-40bf-a5dc-ab02b514e04f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63712
2575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.637122575
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.107357800
Short name T559
Test name
Test status
Simulation time 1108406691 ps
CPU time 41.48 seconds
Started May 30 01:19:59 PM PDT 24
Finished May 30 01:20:42 PM PDT 24
Peak memory 248844 kb
Host smart-3a23b385-7635-4f2c-ab17-668e377a0194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10735
7800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.107357800
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.800751387
Short name T70
Test name
Test status
Simulation time 3848574481 ps
CPU time 339.48 seconds
Started May 30 01:19:57 PM PDT 24
Finished May 30 01:25:37 PM PDT 24
Peak memory 265352 kb
Host smart-125e2268-70ca-400c-986f-b39c2da66c98
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800751387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_hand
ler_stress_all.800751387
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.2820344193
Short name T30
Test name
Test status
Simulation time 61033181525 ps
CPU time 5352.4 seconds
Started May 30 01:19:55 PM PDT 24
Finished May 30 02:49:09 PM PDT 24
Peak memory 322448 kb
Host smart-83fe3850-e38d-41f5-9ed7-1ee74f056bd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820344193 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.2820344193
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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