Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	98846	1			T23	57		T31	128		T34	15
class_i[0x1]	52074	1			T23	10		T18	7		T31	2
class_i[0x2]	66509	1			T23	9		T31	41		T34	129
class_i[0x3]	55730	1			T34	20		T45	712		T82	1

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	67130	1			T23	23		T18	1		T31	56
alert[0x1]	73837	1			T23	13		T18	5		T31	35
alert[0x2]	67548	1			T23	21		T18	1		T31	52
alert[0x3]	64644	1			T23	19		T31	28		T34	1072

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

272862

1

T23

76

T18

7

T31

171

esc_ping_fail

297

1

T9

5

T10

3

T11

6

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	67058	1			T23	23		T18	1		T31	56
esc_integrity_fail	alert[0x1]	73760	1			T23	13		T18	5		T31	35
esc_integrity_fail	alert[0x2]	67461	1			T23	21		T18	1		T31	52
esc_integrity_fail	alert[0x3]	64583	1			T23	19		T31	28		T34	1072
esc_ping_fail	alert[0x0]	72	1			T9	1		T10	1		T11	1
esc_ping_fail	alert[0x1]	77	1			T9	1		T11	2		T292	1
esc_ping_fail	alert[0x2]	87	1			T9	2		T10	1		T11	1
esc_ping_fail	alert[0x3]	61	1			T9	1		T10	1		T11	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	98754	1			T23	57		T31	128		T34	15
esc_integrity_fail	class_i[0x1]	51998	1			T23	10		T18	7		T31	2
esc_integrity_fail	class_i[0x2]	66438	1			T23	9		T31	41		T34	129
esc_integrity_fail	class_i[0x3]	55672	1			T34	20		T45	712		T82	1
esc_ping_fail	class_i[0x0]	92	1			T9	1		T11	1		T265	9
esc_ping_fail	class_i[0x1]	76	1			T9	3		T10	3		T289	1
esc_ping_fail	class_i[0x2]	71	1			T9	1		T286	8		T293	5
esc_ping_fail	class_i[0x3]	58	1			T11	5		T292	3		T293	2