Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	699833099	0	0	626
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	699833099	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	699833099	699662186	0	0
tb.dut.CheckAccuCntDw	0	0	626	626	0	0
tb.dut.CheckEscCntDw	0	0	626	626	0	0
tb.dut.CheckNAlerts	0	0	626	626	0	0
tb.dut.CheckNClasses	0	0	626	626	0	0
tb.dut.CheckNEscSev	0	0	626	626	0	0
tb.dut.CrashdumpKnownO_A	0	0	699833099	699662186	0	0
tb.dut.EdnKnownO_A	0	0	699833099	699662186	0	0
tb.dut.EscPKnownO_A	0	0	699833099	699662186	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	699833099	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	699833099	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	699833099	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	699833099	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	699833099	80	0	0
tb.dut.IrqAKnownO_A	0	0	699833099	699662186	0	0
tb.dut.IrqBKnownO_A	0	0	699833099	699662186	0	0
tb.dut.IrqCKnownO_A	0	0	699833099	699662186	0	0
tb.dut.IrqDKnownO_A	0	0	699833099	699662186	0	0
tb.dut.TlAReadyKnownO_A	0	0	699833099	699662186	0	0
tb.dut.TlDValidKnownO_A	0	0	699833099	699662186	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	726129133	3596006	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	726129133	17893	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	726129133	17798	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	726129133	18091	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	726129133	18490	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	726129133	17676	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	726129133	17573	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	726129133	17713	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	726129133	18297	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	726129133	17781	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	726129133	17965	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	726129133	17486	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	726129133	18595	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	726129133	17735	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	726129133	17489	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	726129133	18700	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	726129133	17973	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	726129133	17489	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	726129133	17665	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	726129133	18225	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	726129133	17655	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	726129133	18002	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	726129133	17632	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	726129133	18031	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	726129133	17789	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	726129133	17802	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	726129133	18516	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	726129133	17781	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	726129133	17880	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	726129133	18436	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	726129133	17743	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	726129133	17406	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	726129133	18265	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	726129133	17496	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	726129133	17758	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	726129133	17545	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	726129133	17474	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	726129133	18470	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	726129133	18182	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	726129133	17586	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	726129133	17841	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	726129133	17518	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	726129133	17870	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	726129133	18753	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	726129133	17707	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	726129133	18462	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	726129133	18174	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	726129133	17370	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	726129133	17720	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	726129133	17644	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	726129133	17686	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	726129133	17752	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	726129133	17697	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	726129133	18146	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	726129133	18112	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	726129133	17288	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	726129133	17823	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	726129133	17836	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	726129133	17514	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	726129133	17601	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	726129133	18271	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	726129133	17568	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	726129133	17312	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	726129133	17583	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	726129133	18390	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	726129133	17098	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	726129133	18105	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	726129133	17518	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	726129133	18398	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	726129133	17933	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	726129133	35420	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	726129133	18504	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	726129133	17476	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	726129133	17610	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	726129133	17684	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	726129133	18485	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	726129133	17974	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	726129133	17609	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	726129133	17633	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	699833099	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	699833099	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	699833099	80	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	699833099	4383	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	699833099	313629	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	699833099	323246627	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	699833099	294	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	699833099	953	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	699833099	50	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	699833099	493	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	699590607	242051233	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	699833099	1046	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	699833099	1025	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	699833099	999	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	699833099	979	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	699833099	1060	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	699833099	109551	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	699833099	951	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	699833099	59	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	699833099	1419	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	699833099	1179	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	699588861	699519572	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	699833099	699662186	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	699833099	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	699833099	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	699833099	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	699833099	1974	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	699833099	191066	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	699833099	393423280	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	699833099	253	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	699833099	469	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	699833099	15	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	699833099	193	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	699590607	295798761	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	699833099	537	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	699833099	530	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	699833099	527	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	699833099	515	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	699833099	1029	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	699833099	127108	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	699833099	946	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	699833099	68	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	699833099	1446	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	699833099	1206	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	699588861	699519572	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	699833099	699662186	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	699833099	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	699833099	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	699833099	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	699833099	4823	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	699833099	178990	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	699833099	430984253	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	699833099	312	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	699833099	467	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	699833099	21	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	699833099	199	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	699590607	349168106	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	699833099	545	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	699833099	541	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	699833099	534	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	699833099	523	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	699833099	1219	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	699833099	113541	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	699833099	1129	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	699833099	68	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	699833099	1485	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	699833099	1245	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	699588861	699519572	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	699833099	699662186	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	699833099	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	699833099	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	699833099	80	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	699833099	1512	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	699833099	184567	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	699833099	410653597	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	699833099	277	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	699833099	508	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	699833099	22	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	699833099	253	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	699590607	327625581	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	699833099	575	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	699833099	563	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	699833099	554	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	699833099	542	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	699833099	1572	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	699833099	134656	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	699833099	1490	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	699833099	59	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	699833099	1506	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	699833099	1266	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	699588861	699519572	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	699833099	699662186	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	726129133	143683523	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	726129133	725401245	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	726129133	725401245	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	726129133	193691122	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	726129133	725401245	0	0
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