Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.22	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	4	40	90.91

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	4	40	90.91	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	177	1			T4	3		T18	1		T6	1
index[0x1]	161	1			T15	1		T30	1		T18	1
index[0x2]	165	1			T15	1		T17	1		T30	2
index[0x3]	166	1			T4	1		T18	1		T77	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	224	1			T4	1		T17	1		T30	1
lens_less_than_1000[1]	119	1			T4	3		T30	1		T32	1
lens_less_than_1000[2]	85	1			T30	1		T46	1		T31	2
lens_less_than_1000[3]	60	1			T6	1		T34	1		T25	2
lens_less_than_1000[4]	36	1			T31	1		T26	1		T70	1
lens_less_than_1000[5]	71	1			T15	1		T77	1		T42	2
lens_less_than_1000[6]	41	1			T34	1		T117	1		T86	1
lens_less_than_1000[7]	8	1			T15	1		T112	1		T264	1
lens_less_than_1000[8]	14	1			T70	1		T97	1		T265	1
lens_less_than_1000[9]	2	1			T99	1		T246	1		-	-
len_2	9	1			T31	1		T60	1		T266	2

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	4	40	90.91	4

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[8]]	0	1	1
[index[0x1]]	[lens_less_than_1000[7]]	0	1	1
[index[0x1]]	[lens_less_than_1000[9]]	0	1	1
[index[0x2]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	67	1			T18	1		T34	2		T25	1
index[0x0]	lens_less_than_1000[1]	36	1			T4	3		T45	1		T82	1
index[0x0]	lens_less_than_1000[2]	16	1			T34	1		T56	1		T267	1
index[0x0]	lens_less_than_1000[3]	15	1			T6	1		T25	2		T116	1
index[0x0]	lens_less_than_1000[4]	10	1			T70	1		T88	1		T58	1
index[0x0]	lens_less_than_1000[5]	21	1			T77	1		T34	4		T112	1
index[0x0]	lens_less_than_1000[6]	7	1			T34	1		T268	1		T127	1
index[0x0]	lens_less_than_1000[7]	2	1			T269	1		T218	1		-	-
index[0x0]	lens_less_than_1000[9]	1	1			T99	1		-	-		-	-
index[0x0]	len_2	2	1			T60	1		T270	1		-	-
index[0x1]	lens_less_than_1000[0]	56	1			T30	1		T18	1		T47	1
index[0x1]	lens_less_than_1000[1]	23	1			T45	1		T50	1		T112	1
index[0x1]	lens_less_than_1000[2]	19	1			T31	2		T26	1		T28	1
index[0x1]	lens_less_than_1000[3]	14	1			T34	1		T35	1		T51	1
index[0x1]	lens_less_than_1000[4]	12	1			T31	1		T26	1		T35	1
index[0x1]	lens_less_than_1000[5]	14	1			T15	1		T101	1		T112	1
index[0x1]	lens_less_than_1000[6]	14	1			T117	1		T86	1		T53	6
index[0x1]	lens_less_than_1000[8]	6	1			T265	1		T219	3		T271	1
index[0x1]	len_2	3	1			T31	1		T266	1		T270	1
index[0x2]	lens_less_than_1000[0]	53	1			T17	1		T34	1		T25	2
index[0x2]	lens_less_than_1000[1]	26	1			T30	1		T32	1		T44	1
index[0x2]	lens_less_than_1000[2]	28	1			T30	1		T46	1		T49	1
index[0x2]	lens_less_than_1000[3]	13	1			T272	1		T102	1		T273	1
index[0x2]	lens_less_than_1000[4]	6	1			T226	1		T115	1		T274	1
index[0x2]	lens_less_than_1000[5]	22	1			T53	6		T275	2		T123	1
index[0x2]	lens_less_than_1000[6]	9	1			T124	1		T112	1		T100	1
index[0x2]	lens_less_than_1000[7]	2	1			T15	1		T112	1		-	-
index[0x2]	lens_less_than_1000[8]	4	1			T70	1		T99	1		T195	1
index[0x2]	len_2	2	1			T270	2		-	-		-	-
index[0x3]	lens_less_than_1000[0]	48	1			T4	1		T18	1		T34	1
index[0x3]	lens_less_than_1000[1]	34	1			T77	1		T44	1		T73	1
index[0x3]	lens_less_than_1000[2]	22	1			T78	1		T26	1		T276	1
index[0x3]	lens_less_than_1000[3]	18	1			T51	1		T109	2		T275	3
index[0x3]	lens_less_than_1000[4]	8	1			T51	1		T57	1		T92	1
index[0x3]	lens_less_than_1000[5]	14	1			T42	2		T98	1		T55	1
index[0x3]	lens_less_than_1000[6]	11	1			T53	6		T256	1		T277	1
index[0x3]	lens_less_than_1000[7]	4	1			T264	1		T92	1		T246	2
index[0x3]	lens_less_than_1000[8]	4	1			T97	1		T119	1		T278	1
index[0x3]	lens_less_than_1000[9]	1	1			T246	1		-	-		-	-
index[0x3]	len_2	2	1			T266	1		T270	1		-	-