Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	6	34	85.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	6	34	85.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	59	1			T24	1		T25	1		T70	1
class_index[0x1]	68	1			T23	1		T31	1		T34	1
class_index[0x2]	68	1			T21	1		T45	2		T25	1
class_index[0x3]	59	1			T23	1		T42	2		T45	3

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	98	1			T21	1		T23	1		T42	2
intr_timeout_cnt[1]	53	1			T45	1		T25	1		T70	2
intr_timeout_cnt[2]	23	1			T34	1		T51	1		T243	1
intr_timeout_cnt[3]	17	1			T57	1		T197	1		T100	1
intr_timeout_cnt[4]	14	1			T45	1		T25	1		T53	1
intr_timeout_cnt[5]	12	1			T45	1		T98	1		T244	1
intr_timeout_cnt[6]	14	1			T23	1		T31	1		T120	1
intr_timeout_cnt[7]	16	1			T45	1		T25	1		T100	3
intr_timeout_cnt[8]	5	1			T24	1		T45	2		T100	1
intr_timeout_cnt[9]	2	1			T51	1		T226	1		-	-

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	6	34	85.00	6

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x1] , class_index[0x2]]	[intr_timeout_cnt[8] , intr_timeout_cnt[9]]	--	--	4
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	21	1			T88	1		T29	5		T91	1
class_index[0x0]	intr_timeout_cnt[1]	23	1			T25	1		T70	1		T50	1
class_index[0x0]	intr_timeout_cnt[2]	5	1			T59	1		T245	1		T246	1
class_index[0x0]	intr_timeout_cnt[3]	3	1			T57	1		T228	2		-	-
class_index[0x0]	intr_timeout_cnt[4]	2	1			T247	1		T248	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	1	1			T249	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	1	1			T250	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[8]	1	1			T24	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T51	1		T226	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	22	1			T45	1		T25	1		T86	1
class_index[0x1]	intr_timeout_cnt[1]	16	1			T50	1		T86	1		T90	1
class_index[0x1]	intr_timeout_cnt[2]	6	1			T34	1		T123	1		T99	1
class_index[0x1]	intr_timeout_cnt[3]	3	1			T197	1		T65	1		T251	1
class_index[0x1]	intr_timeout_cnt[4]	3	1			T100	1		T252	2		-	-
class_index[0x1]	intr_timeout_cnt[5]	3	1			T253	1		T249	1		T245	1
class_index[0x1]	intr_timeout_cnt[6]	5	1			T23	1		T31	1		T254	1
class_index[0x1]	intr_timeout_cnt[7]	10	1			T45	1		T100	3		T114	2
class_index[0x2]	intr_timeout_cnt[0]	31	1			T21	1		T26	1		T87	1
class_index[0x2]	intr_timeout_cnt[1]	8	1			T45	1		T55	1		T99	2
class_index[0x2]	intr_timeout_cnt[2]	4	1			T243	1		T64	1		T65	1
class_index[0x2]	intr_timeout_cnt[3]	8	1			T100	1		T226	1		T254	1
class_index[0x2]	intr_timeout_cnt[4]	5	1			T45	1		T53	1		T255	1
class_index[0x2]	intr_timeout_cnt[5]	4	1			T244	1		T256	1		T248	1
class_index[0x2]	intr_timeout_cnt[6]	5	1			T120	1		T62	1		T257	1
class_index[0x2]	intr_timeout_cnt[7]	3	1			T25	1		T219	1		T114	1
class_index[0x3]	intr_timeout_cnt[0]	24	1			T23	1		T42	2		T25	1
class_index[0x3]	intr_timeout_cnt[1]	6	1			T70	1		T86	1		T124	1
class_index[0x3]	intr_timeout_cnt[2]	8	1			T51	1		T92	1		T123	1
class_index[0x3]	intr_timeout_cnt[3]	3	1			T258	1		T248	2		-	-
class_index[0x3]	intr_timeout_cnt[4]	4	1			T25	1		T59	1		T197	1
class_index[0x3]	intr_timeout_cnt[5]	4	1			T45	1		T98	1		T258	1
class_index[0x3]	intr_timeout_cnt[6]	4	1			T259	1		T249	1		T260	1
class_index[0x3]	intr_timeout_cnt[7]	2	1			T248	2		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	4	1			T45	2		T100	1		T261	1