Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	363404	1			T1	1625		T2	37		T3	1179
all_values[1]	363404	1			T1	1625		T2	37		T3	1179
all_values[2]	363404	1			T1	1625		T2	37		T3	1179
all_values[3]	363404	1			T1	1625		T2	37		T3	1179

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

723391

1

T1

3220

T2

86

T3

2343

auto[1]

730225

1

T1

3280

T2

62

T3

2373

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

879221

1

T1

3271

T2

76

T3

3642

auto[1]

574395

1

T1

3229

T2

72

T3

1074

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	104507	1			T1	426		T2	14		T3	570
all_values[0]	auto[0]	auto[1]	76459	1			T1	405		T2	13		T5	2
all_values[0]	auto[1]	auto[0]	105967	1			T1	402		T2	5		T3	607
all_values[0]	auto[1]	auto[1]	76471	1			T1	392		T2	5		T3	2
all_values[1]	auto[0]	auto[0]	108624	1			T1	385		T2	11		T3	345
all_values[1]	auto[0]	auto[1]	71898	1			T1	380		T2	11		T3	263
all_values[1]	auto[1]	auto[0]	110844	1			T1	432		T2	8		T3	323
all_values[1]	auto[1]	auto[1]	72038	1			T1	428		T2	7		T3	248
all_values[2]	auto[0]	auto[0]	111070	1			T1	400		T2	9		T3	284
all_values[2]	auto[0]	auto[1]	69661	1			T1	400		T2	9		T3	262
all_values[2]	auto[1]	auto[0]	112630	1			T1	413		T2	10		T3	335
all_values[2]	auto[1]	auto[1]	70043	1			T1	412		T2	9		T3	298
all_values[3]	auto[0]	auto[0]	112342	1			T1	412		T2	10		T3	618
all_values[3]	auto[0]	auto[1]	68830	1			T1	412		T2	9		T3	1
all_values[3]	auto[1]	auto[0]	113237	1			T1	401		T2	9		T3	560
all_values[3]	auto[1]	auto[1]	68995	1			T1	400		T2	9		T20	34