Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	363404	1			T1	1625		T2	37		T3	1179
all_pins[1]	363404	1			T1	1625		T2	37		T3	1179
all_pins[2]	363404	1			T1	1625		T2	37		T3	1179
all_pins[3]	363404	1			T1	1625		T2	37		T3	1179

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1166069	1			T1	4868		T2	118		T3	4168
values[0x1]	287547	1			T1	1632		T2	30		T3	548
transitions[0x0=>0x1]	191743	1			T1	979		T2	17		T3	428
transitions[0x1=>0x0]	191968	1			T1	980		T2	17		T3	429

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	286933	1			T1	1233		T2	32		T3	1177
all_pins[0]	values[0x1]	76471	1			T1	392		T2	5		T3	2
all_pins[0]	transitions[0x0=>0x1]	75851	1			T1	391		T2	5		T3	1
all_pins[0]	transitions[0x1=>0x0]	68600	1			T1	400		T2	9		T20	34
all_pins[1]	values[0x0]	291366	1			T1	1197		T2	30		T3	931
all_pins[1]	values[0x1]	72038	1			T1	428		T2	7		T3	248
all_pins[1]	transitions[0x0=>0x1]	39882	1			T1	218		T2	4		T3	247
all_pins[1]	transitions[0x1=>0x0]	44315	1			T1	182		T2	2		T3	1
all_pins[2]	values[0x0]	293361	1			T1	1213		T2	28		T3	881
all_pins[2]	values[0x1]	70043	1			T1	412		T2	9		T3	298
all_pins[2]	transitions[0x0=>0x1]	38124	1			T1	182		T2	3		T3	180
all_pins[2]	transitions[0x1=>0x0]	40119	1			T1	198		T2	1		T3	130
all_pins[3]	values[0x0]	294409	1			T1	1225		T2	28		T3	1179
all_pins[3]	values[0x1]	68995	1			T1	400		T2	9		T20	34
all_pins[3]	transitions[0x0=>0x1]	37886	1			T1	188		T2	5		T20	20
all_pins[3]	transitions[0x1=>0x0]	38934	1			T1	200		T2	5		T3	298