Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	87381	1			T1	491		T4	613		T15	735
accum_cnt_1000	223971	1			T1	633		T20	9		T4	1327
accum_cnt_100	25751	1			T1	41		T2	4		T20	37
accum_cnt_50	65995	1			T1	1217		T2	96		T20	27
accum_cnt_10	181835	1			T1	1222		T2	36		T5	9
accum_cnt_0	440283	1			T1	1212		T2	8		T3	3484

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	267983	1			T1	1204		T2	36		T3	871
class_index[0x1]	267983	1			T1	1204		T2	36		T3	871
class_index[0x2]	267983	1			T1	1204		T2	36		T3	871
class_index[0x3]	267983	1			T1	1204		T2	36		T3	871

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	26564	1			T1	491		T4	318		T15	358
class_index[0x0]	accum_cnt_1000	68269	1			T1	633		T4	343		T15	684
class_index[0x0]	accum_cnt_100	8417	1			T1	41		T4	19		T15	33
class_index[0x0]	accum_cnt_50	18008	1			T1	29		T2	22		T4	15
class_index[0x0]	accum_cnt_10	42520	1			T1	8		T2	10		T21	9
class_index[0x0]	accum_cnt_0	87379	1			T1	2		T2	4		T3	871
class_index[0x1]	accum_cnt_2000	20014	1			T31	170		T225	121		T82	420
class_index[0x1]	accum_cnt_1000	56013	1			T4	630		T30	3		T6	1318
class_index[0x1]	accum_cnt_100	6220	1			T2	4		T4	35		T30	29
class_index[0x1]	accum_cnt_50	13536	1			T2	26		T4	29		T17	822
class_index[0x1]	accum_cnt_10	49327	1			T1	2		T2	6		T5	3
class_index[0x1]	accum_cnt_0	113794	1			T1	1202		T3	871		T20	1
class_index[0x2]	accum_cnt_2000	19982	1			T4	295		T15	377		T6	67
class_index[0x2]	accum_cnt_1000	48804	1			T20	9		T4	354		T15	663
class_index[0x2]	accum_cnt_100	5970	1			T20	37		T4	20		T15	34
class_index[0x2]	accum_cnt_50	15838	1			T2	20		T20	27		T4	15
class_index[0x2]	accum_cnt_10	45891	1			T1	1199		T2	12		T5	3
class_index[0x2]	accum_cnt_0	120916	1			T1	5		T2	4		T3	871
class_index[0x3]	accum_cnt_2000	20821	1			T18	249		T77	484		T33	424
class_index[0x3]	accum_cnt_1000	50885	1			T17	718		T30	12		T18	222
class_index[0x3]	accum_cnt_100	5144	1			T17	51		T30	19		T18	9
class_index[0x3]	accum_cnt_50	18613	1			T1	1188		T2	28		T17	47
class_index[0x3]	accum_cnt_10	44097	1			T1	13		T2	8		T5	3
class_index[0x3]	accum_cnt_0	118194	1			T1	3		T3	871		T20	85