Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	8920	1			T18	1157		T31	6		T34	47
alert[0x1]	8894	1			T225	83		T73	68		T49	12
alert[0x2]	7143	1			T45	2		T225	2648		T26	828
alert[0x3]	13814	1			T18	15		T34	71		T26	70
alert[0x4]	9583	1			T23	1		T9	1		T26	42
alert[0x5]	3270	1			T18	74		T6	1		T31	6
alert[0x6]	4312	1			T8	1		T34	253		T225	351
alert[0x7]	6847	1			T31	300		T34	927		T225	941
alert[0x8]	9967	1			T18	14		T31	10		T9	1
alert[0x9]	7543	1			T34	107		T225	132		T25	4
alert[0xa]	5320	1			T34	219		T225	419		T26	176
alert[0xb]	5756	1			T31	157		T34	127		T9	2
alert[0xc]	10503	1			T34	57		T225	52		T26	2
alert[0xd]	7692	1			T18	14		T34	8		T49	908
alert[0xe]	2704	1			T31	136		T225	1		T73	134
alert[0xf]	14620	1			T31	2		T34	4		T225	396
alert[0x10]	7956	1			T31	74		T73	7		T49	111
alert[0x11]	10562	1			T31	19		T225	41		T73	245
alert[0x12]	4221	1			T18	101		T225	403		T73	208
alert[0x13]	8718	1			T23	5		T18	660		T6	4
alert[0x14]	2466	1			T31	326		T73	54		T86	2
alert[0x15]	3325	1			T34	4		T25	1		T73	440
alert[0x16]	7042	1			T31	313		T34	31		T225	16
alert[0x17]	7395	1			T34	167		T45	2		T225	535
alert[0x18]	7975	1			T31	75		T34	62		T225	129
alert[0x19]	4320	1			T34	23		T225	49		T26	18
alert[0x1a]	6035	1			T45	18		T97	42		T50	32
alert[0x1b]	4314	1			T31	15		T45	4		T26	84
alert[0x1c]	5776	1			T31	1		T34	55		T73	717
alert[0x1d]	7526	1			T31	11		T225	169		T26	55
alert[0x1e]	4360	1			T31	14		T49	161		T97	27
alert[0x1f]	2839	1			T25	1		T97	462		T98	625
alert[0x20]	8366	1			T225	83		T26	934		T49	2856
alert[0x21]	5937	1			T9	2		T26	23		T49	6
alert[0x22]	5338	1			T6	1		T31	39		T34	28
alert[0x23]	4227	1			T18	80		T31	13		T45	127
alert[0x24]	7598	1			T31	6		T34	98		T45	55
alert[0x25]	6633	1			T34	5		T225	628		T9	1
alert[0x26]	5455	1			T18	319		T31	9		T225	37
alert[0x27]	10621	1			T31	32		T34	142		T225	56
alert[0x28]	5411	1			T23	1		T31	115		T45	29
alert[0x29]	4187	1			T31	25		T34	84		T225	2
alert[0x2a]	4407	1			T18	440		T9	1		T25	3
alert[0x2b]	3786	1			T18	36		T26	758		T73	665
alert[0x2c]	2653	1			T7	1		T31	19		T49	71
alert[0x2d]	4519	1			T31	55		T34	475		T225	75
alert[0x2e]	8989	1			T31	16		T34	31		T26	255
alert[0x2f]	11808	1			T31	100		T34	54		T225	118
alert[0x30]	6559	1			T6	1		T31	13		T97	1197
alert[0x31]	15228	1			T31	5		T34	16		T25	14
alert[0x32]	9504	1			T34	256		T97	42		T98	85
alert[0x33]	4954	1			T34	14		T45	4		T225	89
alert[0x34]	14749	1			T34	144		T45	21		T26	2256
alert[0x35]	10330	1			T18	43		T31	5		T225	146
alert[0x36]	4714	1			T18	46		T31	344		T34	727
alert[0x37]	6028	1			T18	6		T34	61		T45	406
alert[0x38]	9459	1			T31	85		T26	15		T97	24
alert[0x39]	5635	1			T34	13		T45	2		T225	54
alert[0x3a]	14270	1			T31	11		T34	107		T26	662
alert[0x3b]	3055	1			T18	119		T34	54		T45	1
alert[0x3c]	4083	1			T34	546		T45	8		T26	588
alert[0x3d]	11476	1			T34	722		T45	1		T26	215
alert[0x3e]	5028	1			T225	324		T25	10		T26	17
alert[0x3f]	10600	1			T18	243		T31	40		T225	123
alert[0x40]	5032	1			T31	103		T34	12		T225	89

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	123743	1			T31	172		T34	38		T45	483
class_i[0x1]	130258	1			T23	6		T6	7		T31	2290
class_i[0x2]	92400	1			T7	1		T8	1		T31	112
class_i[0x3]	115956	1			T23	1		T18	3367		T31	1

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

461678

1

T23

7

T18

3367

T31

2575

alert_ping_fail

679

1

T6

7

T7

1

T8

1

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	8913	1			T18	1157		T31	6		T34	47
alert_integrity_fail	alert[0x1]	8886	1			T225	83		T73	68		T49	12
alert_integrity_fail	alert[0x2]	7132	1			T45	2		T225	2648		T26	828
alert_integrity_fail	alert[0x3]	13808	1			T18	15		T34	71		T26	70
alert_integrity_fail	alert[0x4]	9568	1			T23	1		T26	42		T73	227
alert_integrity_fail	alert[0x5]	3255	1			T18	74		T31	6		T225	28
alert_integrity_fail	alert[0x6]	4300	1			T34	253		T225	351		T25	2
alert_integrity_fail	alert[0x7]	6834	1			T31	300		T34	927		T225	941
alert_integrity_fail	alert[0x8]	9946	1			T18	14		T31	10		T26	358
alert_integrity_fail	alert[0x9]	7538	1			T34	107		T225	132		T25	4
alert_integrity_fail	alert[0xa]	5310	1			T34	219		T225	419		T26	176
alert_integrity_fail	alert[0xb]	5746	1			T31	157		T34	127		T98	7
alert_integrity_fail	alert[0xc]	10497	1			T34	57		T225	52		T26	2
alert_integrity_fail	alert[0xd]	7683	1			T18	14		T34	8		T49	908
alert_integrity_fail	alert[0xe]	2698	1			T31	136		T225	1		T73	134
alert_integrity_fail	alert[0xf]	14606	1			T31	2		T34	4		T225	396
alert_integrity_fail	alert[0x10]	7942	1			T31	74		T73	7		T49	111
alert_integrity_fail	alert[0x11]	10555	1			T31	19		T225	41		T73	245
alert_integrity_fail	alert[0x12]	4214	1			T18	101		T225	403		T73	208
alert_integrity_fail	alert[0x13]	8704	1			T23	5		T18	660		T31	75
alert_integrity_fail	alert[0x14]	2453	1			T31	326		T73	54		T86	2
alert_integrity_fail	alert[0x15]	3309	1			T34	4		T25	1		T73	440
alert_integrity_fail	alert[0x16]	7032	1			T31	313		T34	31		T225	16
alert_integrity_fail	alert[0x17]	7387	1			T34	167		T45	2		T225	535
alert_integrity_fail	alert[0x18]	7970	1			T31	75		T34	62		T225	129
alert_integrity_fail	alert[0x19]	4311	1			T34	23		T225	49		T26	18
alert_integrity_fail	alert[0x1a]	6026	1			T45	18		T97	42		T50	32
alert_integrity_fail	alert[0x1b]	4305	1			T31	15		T45	4		T26	84
alert_integrity_fail	alert[0x1c]	5769	1			T31	1		T34	55		T73	717
alert_integrity_fail	alert[0x1d]	7514	1			T31	11		T225	169		T26	55
alert_integrity_fail	alert[0x1e]	4354	1			T31	14		T49	161		T97	27
alert_integrity_fail	alert[0x1f]	2822	1			T25	1		T97	462		T98	625
alert_integrity_fail	alert[0x20]	8356	1			T225	83		T26	934		T49	2856
alert_integrity_fail	alert[0x21]	5926	1			T26	23		T49	6		T97	1286
alert_integrity_fail	alert[0x22]	5325	1			T31	39		T34	28		T225	36
alert_integrity_fail	alert[0x23]	4220	1			T18	80		T31	13		T45	127
alert_integrity_fail	alert[0x24]	7592	1			T31	6		T34	98		T45	55
alert_integrity_fail	alert[0x25]	6627	1			T34	5		T225	628		T26	66
alert_integrity_fail	alert[0x26]	5444	1			T18	319		T31	9		T225	37
alert_integrity_fail	alert[0x27]	10611	1			T31	32		T34	142		T225	56
alert_integrity_fail	alert[0x28]	5399	1			T23	1		T31	115		T45	29
alert_integrity_fail	alert[0x29]	4170	1			T31	25		T34	84		T225	2
alert_integrity_fail	alert[0x2a]	4389	1			T18	440		T25	3		T49	110
alert_integrity_fail	alert[0x2b]	3770	1			T18	36		T26	758		T73	665
alert_integrity_fail	alert[0x2c]	2639	1			T31	19		T49	71		T97	6
alert_integrity_fail	alert[0x2d]	4509	1			T31	55		T34	475		T225	75
alert_integrity_fail	alert[0x2e]	8974	1			T31	16		T34	31		T26	255
alert_integrity_fail	alert[0x2f]	11794	1			T31	100		T34	54		T225	118
alert_integrity_fail	alert[0x30]	6547	1			T31	13		T97	1197		T282	27
alert_integrity_fail	alert[0x31]	15216	1			T31	5		T34	16		T25	14
alert_integrity_fail	alert[0x32]	9494	1			T34	256		T97	42		T98	85
alert_integrity_fail	alert[0x33]	4946	1			T34	14		T45	4		T225	89
alert_integrity_fail	alert[0x34]	14742	1			T34	144		T45	21		T26	2256
alert_integrity_fail	alert[0x35]	10317	1			T18	43		T31	5		T225	146
alert_integrity_fail	alert[0x36]	4706	1			T18	46		T31	344		T34	727
alert_integrity_fail	alert[0x37]	6019	1			T18	6		T34	61		T45	406
alert_integrity_fail	alert[0x38]	9450	1			T31	85		T26	15		T97	24
alert_integrity_fail	alert[0x39]	5624	1			T34	13		T45	2		T225	54
alert_integrity_fail	alert[0x3a]	14260	1			T31	11		T34	107		T26	662
alert_integrity_fail	alert[0x3b]	3042	1			T18	119		T34	54		T45	1
alert_integrity_fail	alert[0x3c]	4075	1			T34	546		T45	8		T26	588
alert_integrity_fail	alert[0x3d]	11467	1			T34	722		T45	1		T26	215
alert_integrity_fail	alert[0x3e]	5020	1			T225	324		T25	10		T26	17
alert_integrity_fail	alert[0x3f]	10592	1			T18	243		T31	40		T225	123
alert_integrity_fail	alert[0x40]	5029	1			T31	103		T34	12		T225	89
alert_ping_fail	alert[0x0]	7	1			T283	1		T284	1		T285	1
alert_ping_fail	alert[0x1]	8	1			T10	1		T286	1		T287	1
alert_ping_fail	alert[0x2]	11	1			T10	1		T287	1		T288	2
alert_ping_fail	alert[0x3]	6	1			T289	1		T290	1		T291	1
alert_ping_fail	alert[0x4]	15	1			T9	1		T292	1		T265	1
alert_ping_fail	alert[0x5]	15	1			T6	1		T286	1		T265	1
alert_ping_fail	alert[0x6]	12	1			T8	1		T10	1		T287	1
alert_ping_fail	alert[0x7]	13	1			T293	1		T287	1		T294	1
alert_ping_fail	alert[0x8]	21	1			T9	1		T292	1		T293	1
alert_ping_fail	alert[0x9]	5	1			T287	1		T295	1		T296	1
alert_ping_fail	alert[0xa]	10	1			T10	1		T286	1		T265	1
alert_ping_fail	alert[0xb]	10	1			T9	2		T286	1		T295	1
alert_ping_fail	alert[0xc]	6	1			T297	1		T287	1		T291	1
alert_ping_fail	alert[0xd]	9	1			T290	2		T296	1		T298	1
alert_ping_fail	alert[0xe]	6	1			T286	1		T299	1		T296	1
alert_ping_fail	alert[0xf]	14	1			T286	1		T287	1		T300	2
alert_ping_fail	alert[0x10]	14	1			T292	1		T293	1		T289	1
alert_ping_fail	alert[0x11]	7	1			T297	1		T295	1		T299	1
alert_ping_fail	alert[0x12]	7	1			T11	1		T265	1		T301	1
alert_ping_fail	alert[0x13]	14	1			T6	4		T11	1		T288	1
alert_ping_fail	alert[0x14]	13	1			T195	1		T302	1		T300	1
alert_ping_fail	alert[0x15]	16	1			T11	1		T287	1		T303	1
alert_ping_fail	alert[0x16]	10	1			T286	2		T300	1		T301	1
alert_ping_fail	alert[0x17]	8	1			T10	1		T286	1		T284	1
alert_ping_fail	alert[0x18]	5	1			T11	1		T301	1		T283	1
alert_ping_fail	alert[0x19]	9	1			T265	1		T295	1		T299	1
alert_ping_fail	alert[0x1a]	9	1			T11	1		T265	1		T302	1
alert_ping_fail	alert[0x1b]	9	1			T300	1		T301	1		T304	2
alert_ping_fail	alert[0x1c]	7	1			T286	1		T221	1		T299	1
alert_ping_fail	alert[0x1d]	12	1			T239	1		T294	1		T221	2
alert_ping_fail	alert[0x1e]	6	1			T193	1		T296	1		T304	3
alert_ping_fail	alert[0x1f]	17	1			T297	1		T288	1		T305	1
alert_ping_fail	alert[0x20]	10	1			T11	1		T286	1		T293	2
alert_ping_fail	alert[0x21]	11	1			T9	2		T10	1		T306	1
alert_ping_fail	alert[0x22]	13	1			T6	1		T288	1		T305	1
alert_ping_fail	alert[0x23]	7	1			T289	1		T288	1		T302	1
alert_ping_fail	alert[0x24]	6	1			T193	1		T299	1		T307	2
alert_ping_fail	alert[0x25]	6	1			T9	1		T10	1		T301	1
alert_ping_fail	alert[0x26]	11	1			T9	1		T11	1		T265	1
alert_ping_fail	alert[0x27]	10	1			T288	1		T193	1		T300	1
alert_ping_fail	alert[0x28]	12	1			T293	1		T308	2		T295	1
alert_ping_fail	alert[0x29]	17	1			T10	1		T286	1		T293	1
alert_ping_fail	alert[0x2a]	18	1			T9	1		T10	1		T309	1
alert_ping_fail	alert[0x2b]	16	1			T11	2		T288	1		T291	1
alert_ping_fail	alert[0x2c]	14	1			T7	1		T310	2		T301	1
alert_ping_fail	alert[0x2d]	10	1			T10	1		T11	1		T290	1
alert_ping_fail	alert[0x2e]	15	1			T11	2		T293	1		T265	1
alert_ping_fail	alert[0x2f]	14	1			T11	1		T293	1		T193	2
alert_ping_fail	alert[0x30]	12	1			T6	1		T11	1		T265	1
alert_ping_fail	alert[0x31]	12	1			T297	1		T287	1		T309	1
alert_ping_fail	alert[0x32]	10	1			T286	1		T293	1		T265	1
alert_ping_fail	alert[0x33]	8	1			T288	1		T290	1		T301	1
alert_ping_fail	alert[0x34]	7	1			T286	1		T265	1		T311	1
alert_ping_fail	alert[0x35]	13	1			T193	1		T295	1		T283	1
alert_ping_fail	alert[0x36]	8	1			T293	1		T288	1		T283	1
alert_ping_fail	alert[0x37]	9	1			T11	1		T309	1		T312	1
alert_ping_fail	alert[0x38]	9	1			T11	2		T290	2		T284	1
alert_ping_fail	alert[0x39]	11	1			T11	2		T289	1		T291	1
alert_ping_fail	alert[0x3a]	10	1			T10	1		T293	1		T300	1
alert_ping_fail	alert[0x3b]	13	1			T9	1		T286	1		T300	1
alert_ping_fail	alert[0x3c]	8	1			T265	2		T300	1		T313	1
alert_ping_fail	alert[0x3d]	9	1			T286	1		T265	1		T288	1
alert_ping_fail	alert[0x3e]	8	1			T11	1		T290	1		T291	1
alert_ping_fail	alert[0x3f]	8	1			T265	1		T193	1		T313	1
alert_ping_fail	alert[0x40]	3	1			T286	1		T265	1		T314	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	123547	1			T31	172		T34	38		T45	483
alert_integrity_fail	class_i[0x1]	130101	1			T23	6		T31	2290		T34	5773
alert_integrity_fail	class_i[0x2]	92204	1			T31	112		T45	185		T25	16
alert_integrity_fail	class_i[0x3]	115826	1			T23	1		T18	3367		T31	1
alert_ping_fail	class_i[0x0]	196	1			T10	5		T306	1		T286	15
alert_ping_fail	class_i[0x1]	157	1			T6	7		T9	2		T10	3
alert_ping_fail	class_i[0x2]	196	1			T7	1		T8	1		T10	2
alert_ping_fail	class_i[0x3]	130	1			T9	8		T239	1		T10	1