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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.99 98.64 100.00 100.00 100.00 99.38 99.40


Total test records in report: 831
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T177 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2808313459 Jun 02 01:51:37 PM PDT 24 Jun 02 01:52:20 PM PDT 24 333303582 ps
T776 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2763274566 Jun 02 01:51:38 PM PDT 24 Jun 02 01:51:40 PM PDT 24 9746048 ps
T777 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2290176041 Jun 02 01:51:27 PM PDT 24 Jun 02 01:53:26 PM PDT 24 13044839929 ps
T263 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3735965491 Jun 02 01:51:54 PM PDT 24 Jun 02 01:51:57 PM PDT 24 89808916 ps
T778 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.199277579 Jun 02 01:51:31 PM PDT 24 Jun 02 01:55:11 PM PDT 24 23824364799 ps
T779 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3323360853 Jun 02 01:51:41 PM PDT 24 Jun 02 01:51:50 PM PDT 24 108904102 ps
T780 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2324530292 Jun 02 01:51:31 PM PDT 24 Jun 02 01:54:04 PM PDT 24 4518609645 ps
T781 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3361487609 Jun 02 01:52:08 PM PDT 24 Jun 02 01:52:10 PM PDT 24 7714265 ps
T782 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.923625163 Jun 02 01:51:51 PM PDT 24 Jun 02 01:51:59 PM PDT 24 1003315891 ps
T168 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2993653506 Jun 02 01:51:50 PM PDT 24 Jun 02 01:53:02 PM PDT 24 3491551606 ps
T133 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2799014503 Jun 02 01:51:41 PM PDT 24 Jun 02 01:56:18 PM PDT 24 4126502541 ps
T151 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2704669197 Jun 02 01:51:55 PM PDT 24 Jun 02 01:58:22 PM PDT 24 2220365709 ps
T783 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3046806623 Jun 02 01:52:05 PM PDT 24 Jun 02 01:52:07 PM PDT 24 10891971 ps
T784 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1219091525 Jun 02 01:51:53 PM PDT 24 Jun 02 01:51:55 PM PDT 24 18591269 ps
T785 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.4259707124 Jun 02 01:51:38 PM PDT 24 Jun 02 01:51:48 PM PDT 24 239644298 ps
T786 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1431726332 Jun 02 01:51:42 PM PDT 24 Jun 02 01:51:43 PM PDT 24 24142092 ps
T137 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.557811481 Jun 02 01:51:59 PM PDT 24 Jun 02 02:03:44 PM PDT 24 4408373041 ps
T144 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3054473750 Jun 02 01:51:31 PM PDT 24 Jun 02 01:57:41 PM PDT 24 5223493200 ps
T787 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.589068097 Jun 02 01:51:43 PM PDT 24 Jun 02 01:52:29 PM PDT 24 667345697 ps
T150 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.438364757 Jun 02 01:51:40 PM PDT 24 Jun 02 01:56:33 PM PDT 24 28970404151 ps
T167 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2428415100 Jun 02 01:51:32 PM PDT 24 Jun 02 01:51:34 PM PDT 24 233634077 ps
T170 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1735492189 Jun 02 01:52:01 PM PDT 24 Jun 02 01:53:03 PM PDT 24 954050797 ps
T788 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.442882021 Jun 02 01:52:00 PM PDT 24 Jun 02 01:52:06 PM PDT 24 218024806 ps
T789 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2975418527 Jun 02 01:51:37 PM PDT 24 Jun 02 01:51:42 PM PDT 24 51704831 ps
T790 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.881085817 Jun 02 01:52:05 PM PDT 24 Jun 02 01:52:07 PM PDT 24 8372126 ps
T791 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2382666782 Jun 02 01:51:36 PM PDT 24 Jun 02 01:52:21 PM PDT 24 1069718725 ps
T147 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.551416496 Jun 02 01:52:01 PM PDT 24 Jun 02 01:53:39 PM PDT 24 1455367634 ps
T792 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.4014876548 Jun 02 01:51:38 PM PDT 24 Jun 02 01:51:51 PM PDT 24 87302427 ps
T793 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3384672968 Jun 02 01:51:39 PM PDT 24 Jun 02 01:51:48 PM PDT 24 95053404 ps
T794 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1257870558 Jun 02 01:51:55 PM PDT 24 Jun 02 01:51:59 PM PDT 24 36055662 ps
T795 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3234892301 Jun 02 01:51:53 PM PDT 24 Jun 02 01:51:59 PM PDT 24 128987858 ps
T796 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.526197275 Jun 02 01:51:37 PM PDT 24 Jun 02 01:51:49 PM PDT 24 276912744 ps
T797 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3604363211 Jun 02 01:51:52 PM PDT 24 Jun 02 01:52:02 PM PDT 24 258731058 ps
T798 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3247326647 Jun 02 01:52:08 PM PDT 24 Jun 02 01:52:10 PM PDT 24 8847175 ps
T799 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1409281690 Jun 02 01:52:05 PM PDT 24 Jun 02 01:52:07 PM PDT 24 9985527 ps
T149 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3531892088 Jun 02 01:51:52 PM PDT 24 Jun 02 02:03:48 PM PDT 24 8541315036 ps
T800 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.878798252 Jun 02 01:52:06 PM PDT 24 Jun 02 01:52:08 PM PDT 24 7340097 ps
T801 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1363861991 Jun 02 01:51:49 PM PDT 24 Jun 02 01:51:55 PM PDT 24 38536244 ps
T172 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.326428679 Jun 02 01:51:38 PM PDT 24 Jun 02 01:52:01 PM PDT 24 548113247 ps
T802 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1387155280 Jun 02 01:52:05 PM PDT 24 Jun 02 01:52:07 PM PDT 24 14027407 ps
T156 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2342871059 Jun 02 01:52:01 PM PDT 24 Jun 02 02:04:29 PM PDT 24 9158404968 ps
T803 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3603432943 Jun 02 01:51:57 PM PDT 24 Jun 02 01:52:17 PM PDT 24 548385254 ps
T804 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3434987122 Jun 02 01:51:28 PM PDT 24 Jun 02 01:51:29 PM PDT 24 13815637 ps
T805 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2781110498 Jun 02 01:51:59 PM PDT 24 Jun 02 01:53:44 PM PDT 24 6665701720 ps
T148 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2179112705 Jun 02 01:51:48 PM PDT 24 Jun 02 02:01:02 PM PDT 24 22158670325 ps
T152 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3145209181 Jun 02 01:51:51 PM PDT 24 Jun 02 01:57:45 PM PDT 24 51382894799 ps
T806 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.265147631 Jun 02 01:51:57 PM PDT 24 Jun 02 01:52:09 PM PDT 24 526955394 ps
T807 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2932527869 Jun 02 01:51:49 PM PDT 24 Jun 02 01:51:54 PM PDT 24 278914368 ps
T808 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3804323191 Jun 02 01:51:38 PM PDT 24 Jun 02 01:51:50 PM PDT 24 683571865 ps
T158 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2733481554 Jun 02 01:51:52 PM PDT 24 Jun 02 02:11:03 PM PDT 24 14816740831 ps
T809 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2601067700 Jun 02 01:51:41 PM PDT 24 Jun 02 01:51:43 PM PDT 24 51236211 ps
T810 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.25165284 Jun 02 01:51:43 PM PDT 24 Jun 02 01:51:54 PM PDT 24 1215916149 ps
T811 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3400014142 Jun 02 01:51:41 PM PDT 24 Jun 02 01:51:51 PM PDT 24 1958250462 ps
T812 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2326257332 Jun 02 01:51:50 PM PDT 24 Jun 02 01:51:55 PM PDT 24 123064170 ps
T813 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3928949963 Jun 02 01:51:46 PM PDT 24 Jun 02 01:52:02 PM PDT 24 305440537 ps
T814 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1789842329 Jun 02 01:51:52 PM PDT 24 Jun 02 01:51:58 PM PDT 24 40642901 ps
T153 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.792978161 Jun 02 01:51:41 PM PDT 24 Jun 02 02:10:56 PM PDT 24 15168192943 ps
T815 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.832352294 Jun 02 01:52:04 PM PDT 24 Jun 02 01:52:06 PM PDT 24 68161174 ps
T816 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2607687181 Jun 02 01:52:00 PM PDT 24 Jun 02 01:52:06 PM PDT 24 376781342 ps
T178 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2522936054 Jun 02 01:51:30 PM PDT 24 Jun 02 01:52:41 PM PDT 24 1821078183 ps
T342 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2721533652 Jun 02 01:51:33 PM PDT 24 Jun 02 01:59:33 PM PDT 24 6424783670 ps
T817 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.331743285 Jun 02 01:51:38 PM PDT 24 Jun 02 01:51:45 PM PDT 24 70836742 ps
T818 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.292031031 Jun 02 01:51:38 PM PDT 24 Jun 02 02:01:34 PM PDT 24 33259784026 ps
T819 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.308408838 Jun 02 01:52:00 PM PDT 24 Jun 02 01:52:05 PM PDT 24 193800743 ps
T343 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1045075741 Jun 02 01:51:48 PM PDT 24 Jun 02 01:59:59 PM PDT 24 6319289391 ps
T820 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.696614703 Jun 02 01:51:37 PM PDT 24 Jun 02 01:51:47 PM PDT 24 987927556 ps
T155 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.4036977676 Jun 02 01:51:39 PM PDT 24 Jun 02 01:56:47 PM PDT 24 3918247270 ps
T821 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3525588924 Jun 02 01:51:31 PM PDT 24 Jun 02 01:51:37 PM PDT 24 98595955 ps
T822 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3829798556 Jun 02 01:51:57 PM PDT 24 Jun 02 01:52:11 PM PDT 24 162666045 ps
T344 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1736668084 Jun 02 01:51:57 PM PDT 24 Jun 02 02:13:22 PM PDT 24 17698762489 ps
T159 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.481942842 Jun 02 01:51:31 PM PDT 24 Jun 02 01:57:11 PM PDT 24 8129952825 ps
T823 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1887405330 Jun 02 01:51:30 PM PDT 24 Jun 02 01:51:32 PM PDT 24 8301613 ps
T824 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3124548161 Jun 02 01:51:39 PM PDT 24 Jun 02 02:13:09 PM PDT 24 34298436398 ps
T825 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.993428585 Jun 02 01:51:38 PM PDT 24 Jun 02 01:51:44 PM PDT 24 99821298 ps
T826 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2053377637 Jun 02 01:51:32 PM PDT 24 Jun 02 01:51:39 PM PDT 24 47823999 ps
T827 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.4283734790 Jun 02 01:51:49 PM PDT 24 Jun 02 01:53:38 PM PDT 24 3544901004 ps
T828 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3786970563 Jun 02 01:51:30 PM PDT 24 Jun 02 01:51:41 PM PDT 24 511705686 ps
T829 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1263707412 Jun 02 01:51:31 PM PDT 24 Jun 02 02:03:12 PM PDT 24 8279651375 ps
T830 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2780700608 Jun 02 01:52:04 PM PDT 24 Jun 02 01:52:09 PM PDT 24 113727500 ps
T831 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3479594739 Jun 02 01:51:47 PM PDT 24 Jun 02 01:52:00 PM PDT 24 353460791 ps
T157 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.724905537 Jun 02 01:51:54 PM PDT 24 Jun 02 01:57:26 PM PDT 24 18904002152 ps

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.2449773126
Short name T1
Test name
Test status
Simulation time 80028303601 ps
CPU time 2378.64 seconds
Started Jun 02 01:55:52 PM PDT 24
Finished Jun 02 02:35:32 PM PDT 24
Peak memory 287316 kb
Host smart-16aba4d8-d6af-4ba9-a2fc-2c2c23b934ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449773126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2449773126
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.541074007
Short name T45
Test name
Test status
Simulation time 108379340800 ps
CPU time 1841.32 seconds
Started Jun 02 01:56:34 PM PDT 24
Finished Jun 02 02:27:16 PM PDT 24
Peak memory 289012 kb
Host smart-136f8f11-eef9-4fe6-ba52-03e9218ebf3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541074007 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.541074007
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3335077387
Short name T37
Test name
Test status
Simulation time 1538842599 ps
CPU time 18.78 seconds
Started Jun 02 01:52:48 PM PDT 24
Finished Jun 02 01:53:07 PM PDT 24
Peak memory 269100 kb
Host smart-bbf0be17-0044-4a4f-baa4-f81b5d1c77ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3335077387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3335077387
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2993523316
Short name T34
Test name
Test status
Simulation time 54594745639 ps
CPU time 1466.67 seconds
Started Jun 02 01:53:56 PM PDT 24
Finished Jun 02 02:18:23 PM PDT 24
Peak memory 289656 kb
Host smart-55d90fcb-43e4-432f-a3f4-bc7ecb5a49f9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993523316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2993523316
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.767530854
Short name T160
Test name
Test status
Simulation time 7417585488 ps
CPU time 34.27 seconds
Started Jun 02 01:51:45 PM PDT 24
Finished Jun 02 01:52:19 PM PDT 24
Peak memory 245512 kb
Host smart-6a7fde6e-cf2a-4aa4-b9fb-e77f84a9aa6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=767530854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.767530854
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.3699917778
Short name T18
Test name
Test status
Simulation time 31306067232 ps
CPU time 1810.8 seconds
Started Jun 02 01:55:53 PM PDT 24
Finished Jun 02 02:26:04 PM PDT 24
Peak memory 269268 kb
Host smart-dcb7918f-802a-4dc2-8958-f4822871e09f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699917778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.3699917778
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.467516895
Short name T31
Test name
Test status
Simulation time 20342599764 ps
CPU time 1833.67 seconds
Started Jun 02 01:55:21 PM PDT 24
Finished Jun 02 02:25:55 PM PDT 24
Peak memory 289880 kb
Host smart-f6511779-8319-46e7-8771-0824ddc19c6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467516895 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.467516895
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.598531386
Short name T97
Test name
Test status
Simulation time 322681375740 ps
CPU time 3657.07 seconds
Started Jun 02 01:55:40 PM PDT 24
Finished Jun 02 02:56:38 PM PDT 24
Peak memory 299832 kb
Host smart-22fb2772-dff7-4afb-a33d-f778090b1d38
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598531386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_han
dler_stress_all.598531386
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.3298263798
Short name T107
Test name
Test status
Simulation time 121155477658 ps
CPU time 1162.72 seconds
Started Jun 02 01:56:40 PM PDT 24
Finished Jun 02 02:16:03 PM PDT 24
Peak memory 281564 kb
Host smart-5e48b8ac-58c8-45cc-8eb3-b103898b1345
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298263798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.3298263798
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3233507363
Short name T131
Test name
Test status
Simulation time 6652764296 ps
CPU time 454.98 seconds
Started Jun 02 01:51:26 PM PDT 24
Finished Jun 02 01:59:01 PM PDT 24
Peak memory 265612 kb
Host smart-2accbe83-64e5-47f3-ad21-893b5e05214b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3233507363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3233507363
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.3473904910
Short name T59
Test name
Test status
Simulation time 2232815126716 ps
CPU time 7661.15 seconds
Started Jun 02 01:53:17 PM PDT 24
Finished Jun 02 04:01:00 PM PDT 24
Peak memory 354360 kb
Host smart-9b50be17-12f9-4413-b3b1-56eb47c90536
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473904910 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.3473904910
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2433394063
Short name T25
Test name
Test status
Simulation time 90033975527 ps
CPU time 2310.91 seconds
Started Jun 02 01:55:46 PM PDT 24
Finished Jun 02 02:34:17 PM PDT 24
Peak memory 282344 kb
Host smart-bb0e11eb-1c61-4d51-af66-6ecadd338ccd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433394063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2433394063
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3584920094
Short name T128
Test name
Test status
Simulation time 21146966161 ps
CPU time 622.54 seconds
Started Jun 02 01:51:46 PM PDT 24
Finished Jun 02 02:02:09 PM PDT 24
Peak memory 265464 kb
Host smart-2e52e269-a780-4215-88c7-1e5f17059a97
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584920094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3584920094
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.4257482860
Short name T138
Test name
Test status
Simulation time 11304365373 ps
CPU time 291.45 seconds
Started Jun 02 01:51:46 PM PDT 24
Finished Jun 02 01:56:37 PM PDT 24
Peak memory 270292 kb
Host smart-1dbabf60-3963-48b0-b84b-d6c7a9dcb6d5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4257482860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.4257482860
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.415180834
Short name T6
Test name
Test status
Simulation time 452061462912 ps
CPU time 3448.11 seconds
Started Jun 02 01:54:17 PM PDT 24
Finished Jun 02 02:51:46 PM PDT 24
Peak memory 289356 kb
Host smart-6d452e45-db78-474f-8b1f-0951c6e9f22b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415180834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.415180834
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.391548502
Short name T101
Test name
Test status
Simulation time 137102250945 ps
CPU time 2046.47 seconds
Started Jun 02 01:53:34 PM PDT 24
Finished Jun 02 02:27:41 PM PDT 24
Peak memory 289680 kb
Host smart-1f657096-c8a1-4ea9-8793-37677f8c8a56
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391548502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_han
dler_stress_all.391548502
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.367977285
Short name T99
Test name
Test status
Simulation time 325051128641 ps
CPU time 6007 seconds
Started Jun 02 01:52:55 PM PDT 24
Finished Jun 02 03:33:03 PM PDT 24
Peak memory 349632 kb
Host smart-4b6f4f8d-c1a7-41a9-acef-607cc5a8c90c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367977285 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.367977285
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2177678716
Short name T195
Test name
Test status
Simulation time 124592889815 ps
CPU time 2192.45 seconds
Started Jun 02 01:53:14 PM PDT 24
Finished Jun 02 02:29:47 PM PDT 24
Peak memory 282060 kb
Host smart-c144e401-9721-471a-a802-234cf199554a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177678716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2177678716
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2733481554
Short name T158
Test name
Test status
Simulation time 14816740831 ps
CPU time 1149.94 seconds
Started Jun 02 01:51:52 PM PDT 24
Finished Jun 02 02:11:03 PM PDT 24
Peak memory 272968 kb
Host smart-361c4e6a-1998-425a-b5de-ebc0c17fe5b4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733481554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.2733481554
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.4187236576
Short name T11
Test name
Test status
Simulation time 70734321342 ps
CPU time 793.14 seconds
Started Jun 02 01:54:52 PM PDT 24
Finished Jun 02 02:08:05 PM PDT 24
Peak memory 248096 kb
Host smart-1ee1ca9d-2547-4af6-94fc-ecd6e21419f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187236576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.4187236576
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.686718427
Short name T331
Test name
Test status
Simulation time 15936791 ps
CPU time 1.57 seconds
Started Jun 02 01:52:07 PM PDT 24
Finished Jun 02 01:52:09 PM PDT 24
Peak memory 236928 kb
Host smart-ecbe5e62-1b27-428c-9562-98d22c6e2bce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=686718427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.686718427
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2687597397
Short name T15
Test name
Test status
Simulation time 8673687308 ps
CPU time 950.48 seconds
Started Jun 02 01:53:52 PM PDT 24
Finished Jun 02 02:09:43 PM PDT 24
Peak memory 289300 kb
Host smart-22108166-c33d-4057-8704-5f956f19beee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687597397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2687597397
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3054473750
Short name T144
Test name
Test status
Simulation time 5223493200 ps
CPU time 369.23 seconds
Started Jun 02 01:51:31 PM PDT 24
Finished Jun 02 01:57:41 PM PDT 24
Peak memory 265368 kb
Host smart-bcb2c756-e405-4b32-9c91-c45ab31c7858
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3054473750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.3054473750
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3471402414
Short name T145
Test name
Test status
Simulation time 16938057348 ps
CPU time 1214.85 seconds
Started Jun 02 01:51:41 PM PDT 24
Finished Jun 02 02:11:57 PM PDT 24
Peak memory 265424 kb
Host smart-2a3c4d90-becb-4560-965d-cf7b8e40ea1b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471402414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3471402414
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3202181560
Short name T239
Test name
Test status
Simulation time 259057829316 ps
CPU time 1751.29 seconds
Started Jun 02 01:56:13 PM PDT 24
Finished Jun 02 02:25:25 PM PDT 24
Peak memory 267372 kb
Host smart-0c6de904-196e-4ae5-bf02-26c834211bfd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202181560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3202181560
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.831305079
Short name T134
Test name
Test status
Simulation time 4101903573 ps
CPU time 102.21 seconds
Started Jun 02 01:51:35 PM PDT 24
Finished Jun 02 01:53:18 PM PDT 24
Peak memory 265328 kb
Host smart-59b7c958-dd53-4627-9b73-769915f9d32a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=831305079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_error
s.831305079
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1566156114
Short name T296
Test name
Test status
Simulation time 46007710146 ps
CPU time 506.78 seconds
Started Jun 02 01:56:15 PM PDT 24
Finished Jun 02 02:04:42 PM PDT 24
Peak memory 254156 kb
Host smart-75208c2b-8a9e-43c7-b931-69b768c9604c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566156114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1566156114
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.403878403
Short name T347
Test name
Test status
Simulation time 1636644216 ps
CPU time 224.08 seconds
Started Jun 02 01:51:39 PM PDT 24
Finished Jun 02 01:55:23 PM PDT 24
Peak memory 236828 kb
Host smart-625a5393-9287-47f0-9f4f-5b9f9b088420
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=403878403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.403878403
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3262269773
Short name T265
Test name
Test status
Simulation time 20115356421 ps
CPU time 408.25 seconds
Started Jun 02 01:56:22 PM PDT 24
Finished Jun 02 02:03:10 PM PDT 24
Peak memory 255108 kb
Host smart-56993886-a92a-4e40-ae21-737c3ddb8343
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262269773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3262269773
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.419878749
Short name T132
Test name
Test status
Simulation time 4608345415 ps
CPU time 207.1 seconds
Started Jun 02 01:51:52 PM PDT 24
Finished Jun 02 01:55:20 PM PDT 24
Peak memory 265404 kb
Host smart-dffe7b6a-eef5-4ac7-9778-dd3e6836841e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=419878749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_erro
rs.419878749
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1841989485
Short name T10
Test name
Test status
Simulation time 38006481356 ps
CPU time 361.45 seconds
Started Jun 02 01:53:18 PM PDT 24
Finished Jun 02 01:59:20 PM PDT 24
Peak memory 247148 kb
Host smart-e5e066a8-41b3-40c9-98b6-ca43bba21d65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841989485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1841989485
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.2806939146
Short name T316
Test name
Test status
Simulation time 257749394004 ps
CPU time 2802.78 seconds
Started Jun 02 01:54:12 PM PDT 24
Finished Jun 02 02:40:55 PM PDT 24
Peak memory 281568 kb
Host smart-e7f06ef3-7b49-4c0d-bea0-5cdd5e61aaa6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806939146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2806939146
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.4247645337
Short name T41
Test name
Test status
Simulation time 1398227151 ps
CPU time 32.47 seconds
Started Jun 02 01:52:50 PM PDT 24
Finished Jun 02 01:53:23 PM PDT 24
Peak memory 248748 kb
Host smart-9657ec03-5b17-40ac-9a06-c921ba96c670
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4247645337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.4247645337
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.70064405
Short name T100
Test name
Test status
Simulation time 1399937210257 ps
CPU time 5774.7 seconds
Started Jun 02 01:54:46 PM PDT 24
Finished Jun 02 03:31:02 PM PDT 24
Peak memory 332456 kb
Host smart-c6e6612c-901f-4180-9e28-f25fc278fede
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70064405 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.70064405
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3531892088
Short name T149
Test name
Test status
Simulation time 8541315036 ps
CPU time 715.64 seconds
Started Jun 02 01:51:52 PM PDT 24
Finished Jun 02 02:03:48 PM PDT 24
Peak memory 265352 kb
Host smart-1ba2df86-8cc1-4518-8776-e5807aa2615e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531892088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3531892088
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.2356427332
Short name T621
Test name
Test status
Simulation time 10707215655 ps
CPU time 401.26 seconds
Started Jun 02 01:53:32 PM PDT 24
Finished Jun 02 02:00:13 PM PDT 24
Peak memory 248176 kb
Host smart-b26c9e75-d041-44ca-b00c-c3e80639c10b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356427332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.2356427332
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.438364757
Short name T150
Test name
Test status
Simulation time 28970404151 ps
CPU time 293.19 seconds
Started Jun 02 01:51:40 PM PDT 24
Finished Jun 02 01:56:33 PM PDT 24
Peak memory 266356 kb
Host smart-062cc7b4-46cf-466b-9f55-52be2347637d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=438364757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_error
s.438364757
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2695036745
Short name T163
Test name
Test status
Simulation time 24225865 ps
CPU time 1.47 seconds
Started Jun 02 01:52:08 PM PDT 24
Finished Jun 02 01:52:10 PM PDT 24
Peak memory 235960 kb
Host smart-7e8f7c73-7e36-4b78-87a8-a7ad22f9e4e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2695036745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2695036745
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.4274602821
Short name T517
Test name
Test status
Simulation time 173215302307 ps
CPU time 2073.85 seconds
Started Jun 02 01:52:51 PM PDT 24
Finished Jun 02 02:27:26 PM PDT 24
Peak memory 282120 kb
Host smart-583d3d5d-b90e-4636-b5b7-3028c364db0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274602821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.4274602821
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.2207663941
Short name T602
Test name
Test status
Simulation time 11257030035 ps
CPU time 382.28 seconds
Started Jun 02 01:53:22 PM PDT 24
Finished Jun 02 01:59:44 PM PDT 24
Peak memory 247848 kb
Host smart-40a2f594-e177-4686-812e-6274a3f431f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207663941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2207663941
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.4057849250
Short name T248
Test name
Test status
Simulation time 200415800683 ps
CPU time 2072.16 seconds
Started Jun 02 01:52:53 PM PDT 24
Finished Jun 02 02:27:26 PM PDT 24
Peak memory 289516 kb
Host smart-b3d362e6-e072-422a-922f-f39cc43198c8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057849250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.4057849250
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.2984890294
Short name T51
Test name
Test status
Simulation time 58757687902 ps
CPU time 4588.25 seconds
Started Jun 02 01:53:40 PM PDT 24
Finished Jun 02 03:10:09 PM PDT 24
Peak memory 354632 kb
Host smart-2b3d3a6a-8828-43cc-957f-bf05259e1dc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984890294 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.2984890294
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2724790286
Short name T162
Test name
Test status
Simulation time 52227433 ps
CPU time 2.53 seconds
Started Jun 02 01:52:05 PM PDT 24
Finished Jun 02 01:52:08 PM PDT 24
Peak memory 237116 kb
Host smart-481eec52-eca5-40f7-90c7-5384c33816ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2724790286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2724790286
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2179112705
Short name T148
Test name
Test status
Simulation time 22158670325 ps
CPU time 553.6 seconds
Started Jun 02 01:51:48 PM PDT 24
Finished Jun 02 02:01:02 PM PDT 24
Peak memory 272688 kb
Host smart-fc515f8f-2663-4d33-95bb-8ac47a76e365
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179112705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2179112705
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1294803297
Short name T308
Test name
Test status
Simulation time 48998520533 ps
CPU time 2383.51 seconds
Started Jun 02 01:53:16 PM PDT 24
Finished Jun 02 02:33:00 PM PDT 24
Peak memory 284156 kb
Host smart-5b19f24f-6517-45b0-aa50-56361d002885
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294803297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1294803297
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2725142227
Short name T249
Test name
Test status
Simulation time 35196526754 ps
CPU time 1982.46 seconds
Started Jun 02 01:54:04 PM PDT 24
Finished Jun 02 02:27:07 PM PDT 24
Peak memory 273408 kb
Host smart-b01cdec1-8fba-4127-8bf8-6bf4d5275a17
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725142227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2725142227
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.2607037219
Short name T228
Test name
Test status
Simulation time 192841538176 ps
CPU time 3197.84 seconds
Started Jun 02 01:54:30 PM PDT 24
Finished Jun 02 02:47:48 PM PDT 24
Peak memory 298048 kb
Host smart-89b9a0a8-e501-4e7d-bb32-9c2175e36067
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607037219 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.2607037219
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.1100797039
Short name T270
Test name
Test status
Simulation time 78014664342 ps
CPU time 1795.03 seconds
Started Jun 02 01:55:25 PM PDT 24
Finished Jun 02 02:25:20 PM PDT 24
Peak memory 289804 kb
Host smart-47eb1707-0cb0-4eed-845a-768a56775069
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100797039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.1100797039
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.2129983167
Short name T88
Test name
Test status
Simulation time 100022784523 ps
CPU time 1773.45 seconds
Started Jun 02 01:56:27 PM PDT 24
Finished Jun 02 02:26:01 PM PDT 24
Peak memory 289928 kb
Host smart-62e356ec-4e48-4190-a15c-fe98178d548b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129983167 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.2129983167
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3604340978
Short name T142
Test name
Test status
Simulation time 12945365437 ps
CPU time 302.57 seconds
Started Jun 02 01:51:57 PM PDT 24
Finished Jun 02 01:57:01 PM PDT 24
Peak memory 265328 kb
Host smart-6170a912-4fce-4f3b-994f-5648b1c55b56
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3604340978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3604340978
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2802221252
Short name T16
Test name
Test status
Simulation time 28169568166 ps
CPU time 1448.7 seconds
Started Jun 02 01:53:13 PM PDT 24
Finished Jun 02 02:17:22 PM PDT 24
Peak memory 265132 kb
Host smart-29372d9c-9168-4a34-9df9-ad6d58b6324d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802221252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2802221252
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.981724052
Short name T65
Test name
Test status
Simulation time 173646772892 ps
CPU time 9215.98 seconds
Started Jun 02 01:56:07 PM PDT 24
Finished Jun 02 04:29:44 PM PDT 24
Peak memory 387028 kb
Host smart-7fed05e4-e388-4ed9-8a9f-aa9f2d9eba4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981724052 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.981724052
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2807441561
Short name T212
Test name
Test status
Simulation time 163904642 ps
CPU time 3.61 seconds
Started Jun 02 01:52:52 PM PDT 24
Finished Jun 02 01:52:57 PM PDT 24
Peak memory 248828 kb
Host smart-6fdf2215-57fc-4d76-8ff0-a6b9f92173fe
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2807441561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2807441561
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.3066847937
Short name T39
Test name
Test status
Simulation time 67014850 ps
CPU time 3.23 seconds
Started Jun 02 01:52:51 PM PDT 24
Finished Jun 02 01:52:55 PM PDT 24
Peak memory 248808 kb
Host smart-c1a3e3c1-c57a-4b7d-b4a2-b245f6df3964
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3066847937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3066847937
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.4214046085
Short name T211
Test name
Test status
Simulation time 160164642 ps
CPU time 3.04 seconds
Started Jun 02 01:53:31 PM PDT 24
Finished Jun 02 01:53:34 PM PDT 24
Peak memory 248860 kb
Host smart-d195d291-7574-4b26-9162-a4e4404b9fa2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4214046085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.4214046085
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.2666777577
Short name T213
Test name
Test status
Simulation time 128037764 ps
CPU time 3.15 seconds
Started Jun 02 01:53:40 PM PDT 24
Finished Jun 02 01:53:43 PM PDT 24
Peak memory 248904 kb
Host smart-5d563277-806d-485c-b24f-2336c58cfed2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2666777577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2666777577
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.724905537
Short name T157
Test name
Test status
Simulation time 18904002152 ps
CPU time 330.77 seconds
Started Jun 02 01:51:54 PM PDT 24
Finished Jun 02 01:57:26 PM PDT 24
Peak memory 265260 kb
Host smart-8f23d46d-aa73-4111-860f-d6f0bdf7b61e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=724905537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.724905537
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.515115301
Short name T146
Test name
Test status
Simulation time 8050124028 ps
CPU time 290.4 seconds
Started Jun 02 01:51:48 PM PDT 24
Finished Jun 02 01:56:38 PM PDT 24
Peak memory 273564 kb
Host smart-8241ad98-a878-4cc9-9693-bb565fedff05
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=515115301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro
rs.515115301
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.1621126650
Short name T743
Test name
Test status
Simulation time 27194889 ps
CPU time 1.42 seconds
Started Jun 02 01:51:52 PM PDT 24
Finished Jun 02 01:51:54 PM PDT 24
Peak memory 235992 kb
Host smart-cef4a72d-0cac-4478-bdf6-4725774d34c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1621126650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.1621126650
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.801834536
Short name T285
Test name
Test status
Simulation time 12994924992 ps
CPU time 547.67 seconds
Started Jun 02 01:52:52 PM PDT 24
Finished Jun 02 02:02:01 PM PDT 24
Peak memory 254376 kb
Host smart-c2c68ac1-0d42-47dc-9e03-21fb0cf2b076
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801834536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.801834536
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3904669644
Short name T86
Test name
Test status
Simulation time 39983580274 ps
CPU time 1917.26 seconds
Started Jun 02 01:53:53 PM PDT 24
Finished Jun 02 02:25:51 PM PDT 24
Peak memory 289300 kb
Host smart-7dc8ce0a-ca39-4339-b2fe-860b8808e979
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904669644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3904669644
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.4175792089
Short name T246
Test name
Test status
Simulation time 360867605863 ps
CPU time 2718.89 seconds
Started Jun 02 01:54:54 PM PDT 24
Finished Jun 02 02:40:13 PM PDT 24
Peak memory 289456 kb
Host smart-0ac1e546-36c2-42a1-8f84-5a256d24d47f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175792089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.4175792089
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.271640535
Short name T8
Test name
Test status
Simulation time 12411187950 ps
CPU time 1073.98 seconds
Started Jun 02 01:56:33 PM PDT 24
Finished Jun 02 02:14:27 PM PDT 24
Peak memory 273352 kb
Host smart-d06c4022-f010-4bff-b4e8-62f8775ae371
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271640535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.271640535
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2492423575
Short name T129
Test name
Test status
Simulation time 8220073905 ps
CPU time 557.69 seconds
Started Jun 02 01:51:26 PM PDT 24
Finished Jun 02 02:00:44 PM PDT 24
Peak memory 265524 kb
Host smart-1663f3d7-5e92-4887-8a33-ddba476f8aae
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492423575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.2492423575
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2425348493
Short name T62
Test name
Test status
Simulation time 3048862825 ps
CPU time 169.62 seconds
Started Jun 02 01:52:53 PM PDT 24
Finished Jun 02 01:55:43 PM PDT 24
Peak memory 256972 kb
Host smart-3125ac93-6a95-4246-9d17-2d087ea3f4cb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425348493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2425348493
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.4172179872
Short name T49
Test name
Test status
Simulation time 49942850144 ps
CPU time 2912.27 seconds
Started Jun 02 01:52:52 PM PDT 24
Finished Jun 02 02:41:26 PM PDT 24
Peak memory 281580 kb
Host smart-628a1133-eb92-4871-bbb2-4a3e785debe7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172179872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.4172179872
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2441161685
Short name T110
Test name
Test status
Simulation time 2100516629 ps
CPU time 118.46 seconds
Started Jun 02 01:53:19 PM PDT 24
Finished Jun 02 01:55:18 PM PDT 24
Peak memory 256792 kb
Host smart-993bcd4f-4305-409c-a1cc-8f167aa0fbc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24411
61685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2441161685
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2625766153
Short name T470
Test name
Test status
Simulation time 46659340011 ps
CPU time 2472.4 seconds
Started Jun 02 01:53:23 PM PDT 24
Finished Jun 02 02:34:36 PM PDT 24
Peak memory 289308 kb
Host smart-71db0fd1-1cda-4bcf-b1d9-e68ce36a5f3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625766153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2625766153
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.1218235293
Short name T615
Test name
Test status
Simulation time 10050897204 ps
CPU time 227.62 seconds
Started Jun 02 01:53:24 PM PDT 24
Finished Jun 02 01:57:12 PM PDT 24
Peak memory 248128 kb
Host smart-16d7385f-65f7-4de4-892e-aa4342fa4088
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218235293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1218235293
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.2173833374
Short name T193
Test name
Test status
Simulation time 25578869937 ps
CPU time 291.73 seconds
Started Jun 02 01:53:32 PM PDT 24
Finished Jun 02 01:58:24 PM PDT 24
Peak memory 248112 kb
Host smart-2e9e933d-df56-4fb6-808c-7f7e7880eb4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173833374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.2173833374
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1871809390
Short name T250
Test name
Test status
Simulation time 1152000710 ps
CPU time 36.39 seconds
Started Jun 02 01:53:41 PM PDT 24
Finished Jun 02 01:54:18 PM PDT 24
Peak memory 254276 kb
Host smart-110ab3c7-21f9-40c6-b9d8-09962721e65b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18718
09390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1871809390
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2104176292
Short name T24
Test name
Test status
Simulation time 1998484851 ps
CPU time 53.82 seconds
Started Jun 02 01:53:46 PM PDT 24
Finished Jun 02 01:54:41 PM PDT 24
Peak memory 248708 kb
Host smart-6ff5abbb-38da-4de5-ae2f-a16478bc6ebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21041
76292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2104176292
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.3325196429
Short name T280
Test name
Test status
Simulation time 255089515888 ps
CPU time 3523.16 seconds
Started Jun 02 01:53:56 PM PDT 24
Finished Jun 02 02:52:39 PM PDT 24
Peak memory 289288 kb
Host smart-a1990246-d944-4df8-aedc-62095c4eb206
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325196429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.3325196429
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.4236333002
Short name T218
Test name
Test status
Simulation time 32296249902 ps
CPU time 3433.13 seconds
Started Jun 02 01:52:58 PM PDT 24
Finished Jun 02 02:50:11 PM PDT 24
Peak memory 322140 kb
Host smart-fba86b14-d902-440f-a383-83fe82292692
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236333002 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.4236333002
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.2530260596
Short name T13
Test name
Test status
Simulation time 209271969 ps
CPU time 13.4 seconds
Started Jun 02 01:52:51 PM PDT 24
Finished Jun 02 01:53:05 PM PDT 24
Peak memory 277496 kb
Host smart-8033f3a1-5e02-47aa-a848-b6d41bc4b556
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2530260596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2530260596
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2905433101
Short name T169
Test name
Test status
Simulation time 2442092858 ps
CPU time 87.2 seconds
Started Jun 02 01:51:31 PM PDT 24
Finished Jun 02 01:52:58 PM PDT 24
Peak memory 240504 kb
Host smart-c5d44ffa-7ae7-441c-9fae-3eeeb905aa11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2905433101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.2905433101
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2428415100
Short name T167
Test name
Test status
Simulation time 233634077 ps
CPU time 2.1 seconds
Started Jun 02 01:51:32 PM PDT 24
Finished Jun 02 01:51:34 PM PDT 24
Peak memory 237800 kb
Host smart-c8f4b9d6-b77a-4d90-913f-aa4ffbfda6a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2428415100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2428415100
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2993653506
Short name T168
Test name
Test status
Simulation time 3491551606 ps
CPU time 71.89 seconds
Started Jun 02 01:51:50 PM PDT 24
Finished Jun 02 01:53:02 PM PDT 24
Peak memory 238208 kb
Host smart-9031576b-e2aa-4889-88c1-d533495b34dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2993653506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2993653506
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.4132286274
Short name T166
Test name
Test status
Simulation time 178683620 ps
CPU time 25.03 seconds
Started Jun 02 01:51:56 PM PDT 24
Finished Jun 02 01:52:21 PM PDT 24
Peak memory 240456 kb
Host smart-24cfbcd5-56b0-44cd-aa24-33a1691cb327
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4132286274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.4132286274
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1735492189
Short name T170
Test name
Test status
Simulation time 954050797 ps
CPU time 61.78 seconds
Started Jun 02 01:52:01 PM PDT 24
Finished Jun 02 01:53:03 PM PDT 24
Peak memory 239708 kb
Host smart-b4fced3e-9d3a-4e88-afeb-948248109847
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1735492189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.1735492189
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3175434926
Short name T136
Test name
Test status
Simulation time 17151544069 ps
CPU time 321.4 seconds
Started Jun 02 01:51:33 PM PDT 24
Finished Jun 02 01:56:54 PM PDT 24
Peak memory 265348 kb
Host smart-733d1451-7499-4bda-a17f-e345202b516b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3175434926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.3175434926
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1650888581
Short name T171
Test name
Test status
Simulation time 35538608 ps
CPU time 2.27 seconds
Started Jun 02 01:51:54 PM PDT 24
Finished Jun 02 01:51:57 PM PDT 24
Peak memory 236808 kb
Host smart-3c842a02-efd5-4c13-a06e-423ca4805f9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1650888581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1650888581
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3501869328
Short name T175
Test name
Test status
Simulation time 31063383 ps
CPU time 2.21 seconds
Started Jun 02 01:51:57 PM PDT 24
Finished Jun 02 01:51:59 PM PDT 24
Peak memory 237240 kb
Host smart-820551ca-ce84-41bf-b78b-2a924d906a9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3501869328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.3501869328
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2522936054
Short name T178
Test name
Test status
Simulation time 1821078183 ps
CPU time 70.64 seconds
Started Jun 02 01:51:30 PM PDT 24
Finished Jun 02 01:52:41 PM PDT 24
Peak memory 239732 kb
Host smart-caa50204-a9c4-4e7b-a6af-21fefb889e7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2522936054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2522936054
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.326428679
Short name T172
Test name
Test status
Simulation time 548113247 ps
CPU time 22.36 seconds
Started Jun 02 01:51:38 PM PDT 24
Finished Jun 02 01:52:01 PM PDT 24
Peak memory 239824 kb
Host smart-cf7bd14e-1293-46a3-aaaf-5eaea0ebfdd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=326428679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.326428679
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2808313459
Short name T177
Test name
Test status
Simulation time 333303582 ps
CPU time 42.64 seconds
Started Jun 02 01:51:37 PM PDT 24
Finished Jun 02 01:52:20 PM PDT 24
Peak memory 239684 kb
Host smart-422ba37b-0467-48a6-ba29-38899741f26e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2808313459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2808313459
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.513568040
Short name T27
Test name
Test status
Simulation time 26185669727 ps
CPU time 1500.38 seconds
Started Jun 02 01:54:52 PM PDT 24
Finished Jun 02 02:19:53 PM PDT 24
Peak memory 305408 kb
Host smart-568dd572-5731-4a2c-a6bb-0009a5f6b154
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513568040 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.513568040
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.646098512
Short name T105
Test name
Test status
Simulation time 829838617 ps
CPU time 54.31 seconds
Started Jun 02 01:56:04 PM PDT 24
Finished Jun 02 01:56:59 PM PDT 24
Peak memory 248752 kb
Host smart-aac4ea40-147c-455b-94a1-b5b4068667f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64609
8512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.646098512
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.940197746
Short name T28
Test name
Test status
Simulation time 5635421892 ps
CPU time 402.55 seconds
Started Jun 02 01:53:12 PM PDT 24
Finished Jun 02 01:59:55 PM PDT 24
Peak memory 265008 kb
Host smart-c638d874-d936-41cc-b520-21febd258739
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940197746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand
ler_stress_all.940197746
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2290176041
Short name T777
Test name
Test status
Simulation time 13044839929 ps
CPU time 118.38 seconds
Started Jun 02 01:51:27 PM PDT 24
Finished Jun 02 01:53:26 PM PDT 24
Peak memory 236912 kb
Host smart-1e7db19b-0d06-4347-907a-827a651d90e8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2290176041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2290176041
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2790548830
Short name T749
Test name
Test status
Simulation time 7825156579 ps
CPU time 419.47 seconds
Started Jun 02 01:51:26 PM PDT 24
Finished Jun 02 01:58:26 PM PDT 24
Peak memory 235952 kb
Host smart-dfdd1181-e9b8-4df4-84a2-8c56e683c4e6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2790548830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2790548830
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3352969665
Short name T734
Test name
Test status
Simulation time 21858419 ps
CPU time 4.2 seconds
Started Jun 02 01:51:27 PM PDT 24
Finished Jun 02 01:51:32 PM PDT 24
Peak memory 240396 kb
Host smart-ebba8f9f-621f-4937-a40e-42a0672e069b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3352969665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3352969665
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.673861000
Short name T774
Test name
Test status
Simulation time 663551121 ps
CPU time 12.11 seconds
Started Jun 02 01:51:32 PM PDT 24
Finished Jun 02 01:51:44 PM PDT 24
Peak memory 252276 kb
Host smart-d66e3185-668c-4971-be40-2458ebe425fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673861000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.673861000
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3786970563
Short name T828
Test name
Test status
Simulation time 511705686 ps
CPU time 10.12 seconds
Started Jun 02 01:51:30 PM PDT 24
Finished Jun 02 01:51:41 PM PDT 24
Peak memory 236840 kb
Host smart-6348f0cf-eec7-4461-a7f9-8398226f10ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3786970563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3786970563
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3434987122
Short name T804
Test name
Test status
Simulation time 13815637 ps
CPU time 1.33 seconds
Started Jun 02 01:51:28 PM PDT 24
Finished Jun 02 01:51:29 PM PDT 24
Peak memory 234980 kb
Host smart-505aa86c-f541-4e97-98ef-d9497cb32fbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3434987122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3434987122
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.4078542332
Short name T717
Test name
Test status
Simulation time 493212012 ps
CPU time 19.89 seconds
Started Jun 02 01:51:29 PM PDT 24
Finished Jun 02 01:51:49 PM PDT 24
Peak memory 245104 kb
Host smart-22f1e6ac-e2aa-4eae-94e8-a2f086f157dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4078542332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.4078542332
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.617590386
Short name T715
Test name
Test status
Simulation time 102420630 ps
CPU time 7.39 seconds
Started Jun 02 01:51:28 PM PDT 24
Finished Jun 02 01:51:36 PM PDT 24
Peak memory 248720 kb
Host smart-0eee01c8-d0a4-4a52-98e8-4c4c529b8531
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=617590386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.617590386
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2631357761
Short name T181
Test name
Test status
Simulation time 7640604724 ps
CPU time 122.48 seconds
Started Jun 02 01:51:32 PM PDT 24
Finished Jun 02 01:53:35 PM PDT 24
Peak memory 240468 kb
Host smart-6fff2d14-c20b-4b91-876c-a9ff3a277516
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2631357761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2631357761
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.199277579
Short name T778
Test name
Test status
Simulation time 23824364799 ps
CPU time 219.64 seconds
Started Jun 02 01:51:31 PM PDT 24
Finished Jun 02 01:55:11 PM PDT 24
Peak memory 236904 kb
Host smart-76aa46e0-1dfd-46d2-8d04-0533b251a708
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=199277579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.199277579
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3739923234
Short name T714
Test name
Test status
Simulation time 98905632 ps
CPU time 8.81 seconds
Started Jun 02 01:51:34 PM PDT 24
Finished Jun 02 01:51:43 PM PDT 24
Peak memory 240392 kb
Host smart-3e60bbee-e5e2-4594-8c33-957e12b4cece
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3739923234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.3739923234
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3430760138
Short name T231
Test name
Test status
Simulation time 418302162 ps
CPU time 8.04 seconds
Started Jun 02 01:51:33 PM PDT 24
Finished Jun 02 01:51:41 PM PDT 24
Peak memory 239696 kb
Host smart-498b438d-460c-41e5-9928-cbd9aff3ea44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430760138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3430760138
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2437987536
Short name T184
Test name
Test status
Simulation time 63105566 ps
CPU time 6.1 seconds
Started Jun 02 01:51:33 PM PDT 24
Finished Jun 02 01:51:39 PM PDT 24
Peak memory 236764 kb
Host smart-5520eabb-e6a5-40a4-b21e-1d5f01cd0514
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2437987536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2437987536
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.585109002
Short name T765
Test name
Test status
Simulation time 17046836 ps
CPU time 1.39 seconds
Started Jun 02 01:51:31 PM PDT 24
Finished Jun 02 01:51:33 PM PDT 24
Peak memory 236904 kb
Host smart-fff69640-1147-4b79-b90d-bed8abc310ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=585109002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.585109002
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3101489708
Short name T773
Test name
Test status
Simulation time 2856321404 ps
CPU time 23.21 seconds
Started Jun 02 01:51:31 PM PDT 24
Finished Jun 02 01:51:55 PM PDT 24
Peak memory 240540 kb
Host smart-3213ae27-1acb-4820-8f0b-dd6d3f19e7b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3101489708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3101489708
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.481942842
Short name T159
Test name
Test status
Simulation time 8129952825 ps
CPU time 339.77 seconds
Started Jun 02 01:51:31 PM PDT 24
Finished Jun 02 01:57:11 PM PDT 24
Peak memory 265464 kb
Host smart-0d6b6f31-ae41-4137-a3a4-cf614113d70b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=481942842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_error
s.481942842
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2721533652
Short name T342
Test name
Test status
Simulation time 6424783670 ps
CPU time 479.59 seconds
Started Jun 02 01:51:33 PM PDT 24
Finished Jun 02 01:59:33 PM PDT 24
Peak memory 269088 kb
Host smart-5608daf6-7cca-4311-9b15-24b1acbf707d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721533652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.2721533652
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2053377637
Short name T826
Test name
Test status
Simulation time 47823999 ps
CPU time 6.51 seconds
Started Jun 02 01:51:32 PM PDT 24
Finished Jun 02 01:51:39 PM PDT 24
Peak memory 252040 kb
Host smart-18a2574a-5f93-4e51-be2b-78c986752014
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2053377637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.2053377637
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3053830118
Short name T262
Test name
Test status
Simulation time 61530691 ps
CPU time 4.3 seconds
Started Jun 02 01:51:37 PM PDT 24
Finished Jun 02 01:51:41 PM PDT 24
Peak memory 236084 kb
Host smart-67e8a43d-c6e4-445d-9933-ff673e971d8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3053830118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.3053830118
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1363861991
Short name T801
Test name
Test status
Simulation time 38536244 ps
CPU time 5.81 seconds
Started Jun 02 01:51:49 PM PDT 24
Finished Jun 02 01:51:55 PM PDT 24
Peak memory 256664 kb
Host smart-04aba451-b76f-4fb7-b534-80630bcc3e87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363861991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.1363861991
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.740620503
Short name T341
Test name
Test status
Simulation time 68946479 ps
CPU time 5.31 seconds
Started Jun 02 01:51:46 PM PDT 24
Finished Jun 02 01:51:52 PM PDT 24
Peak memory 239616 kb
Host smart-a597d5e1-49b3-467c-97a4-550c6dbe3c44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=740620503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.740620503
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1658571773
Short name T164
Test name
Test status
Simulation time 104665384 ps
CPU time 1.47 seconds
Started Jun 02 01:51:50 PM PDT 24
Finished Jun 02 01:51:51 PM PDT 24
Peak memory 236748 kb
Host smart-74e334ca-a96a-4d8c-bf87-d76e0f6509cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1658571773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1658571773
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3479594739
Short name T831
Test name
Test status
Simulation time 353460791 ps
CPU time 12.87 seconds
Started Jun 02 01:51:47 PM PDT 24
Finished Jun 02 01:52:00 PM PDT 24
Peak memory 245068 kb
Host smart-04cc64ec-9741-4c3a-8959-4b2cbaedc929
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3479594739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3479594739
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2336836594
Short name T141
Test name
Test status
Simulation time 16741536370 ps
CPU time 525.73 seconds
Started Jun 02 01:51:49 PM PDT 24
Finished Jun 02 02:00:35 PM PDT 24
Peak memory 265384 kb
Host smart-efa4639c-245f-4d73-ba89-d6f8d4debfb5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336836594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2336836594
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.923625163
Short name T782
Test name
Test status
Simulation time 1003315891 ps
CPU time 7.69 seconds
Started Jun 02 01:51:51 PM PDT 24
Finished Jun 02 01:51:59 PM PDT 24
Peak memory 248720 kb
Host smart-c1be2f85-a306-40aa-b69b-9715dfb8ab5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=923625163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.923625163
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2158026748
Short name T745
Test name
Test status
Simulation time 656866799 ps
CPU time 39.79 seconds
Started Jun 02 01:51:48 PM PDT 24
Finished Jun 02 01:52:28 PM PDT 24
Peak memory 239736 kb
Host smart-ac4a9f37-db0b-456e-8fcd-20055c3570e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2158026748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2158026748
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3469663187
Short name T340
Test name
Test status
Simulation time 400716777 ps
CPU time 6.48 seconds
Started Jun 02 01:51:47 PM PDT 24
Finished Jun 02 01:51:54 PM PDT 24
Peak memory 238748 kb
Host smart-72775e9b-a7b9-4c87-a054-459039879740
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469663187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.3469663187
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3180714231
Short name T186
Test name
Test status
Simulation time 185135968 ps
CPU time 7.64 seconds
Started Jun 02 01:51:46 PM PDT 24
Finished Jun 02 01:51:54 PM PDT 24
Peak memory 237104 kb
Host smart-7da7cb0e-21fb-4710-991e-3f4180b18aa9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3180714231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.3180714231
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1125579270
Short name T772
Test name
Test status
Simulation time 13801001 ps
CPU time 1.29 seconds
Started Jun 02 01:51:47 PM PDT 24
Finished Jun 02 01:51:48 PM PDT 24
Peak memory 236012 kb
Host smart-36a6b0db-060a-4684-9274-ef6b7a4fa5b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1125579270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1125579270
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1491276997
Short name T185
Test name
Test status
Simulation time 84801710 ps
CPU time 11.6 seconds
Started Jun 02 01:51:47 PM PDT 24
Finished Jun 02 01:51:59 PM PDT 24
Peak memory 245116 kb
Host smart-a80a62e3-c3d5-4599-bb71-ed1e277e0f4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1491276997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1491276997
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1045075741
Short name T343
Test name
Test status
Simulation time 6319289391 ps
CPU time 491.26 seconds
Started Jun 02 01:51:48 PM PDT 24
Finished Jun 02 01:59:59 PM PDT 24
Peak memory 265328 kb
Host smart-b6e0ddd6-3f0c-497a-a959-4368c6afc819
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045075741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1045075741
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3928949963
Short name T813
Test name
Test status
Simulation time 305440537 ps
CPU time 15.93 seconds
Started Jun 02 01:51:46 PM PDT 24
Finished Jun 02 01:52:02 PM PDT 24
Peak memory 252748 kb
Host smart-adde1448-ba84-4166-8062-227d331186d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3928949963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3928949963
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3941072898
Short name T759
Test name
Test status
Simulation time 1350419787 ps
CPU time 35.69 seconds
Started Jun 02 01:51:45 PM PDT 24
Finished Jun 02 01:52:21 PM PDT 24
Peak memory 240456 kb
Host smart-fd3be692-fdbd-4a25-acd6-1f8c2623889d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3941072898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3941072898
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2692065385
Short name T746
Test name
Test status
Simulation time 388164146 ps
CPU time 5.66 seconds
Started Jun 02 01:51:46 PM PDT 24
Finished Jun 02 01:51:52 PM PDT 24
Peak memory 239784 kb
Host smart-97c343fd-2e15-438c-9e99-c769864d45c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692065385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.2692065385
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2326257332
Short name T812
Test name
Test status
Simulation time 123064170 ps
CPU time 4.66 seconds
Started Jun 02 01:51:50 PM PDT 24
Finished Jun 02 01:51:55 PM PDT 24
Peak memory 238760 kb
Host smart-3a7efc3e-8465-4e80-9711-8890c453ce46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2326257332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2326257332
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1125020157
Short name T720
Test name
Test status
Simulation time 12744106 ps
CPU time 1.31 seconds
Started Jun 02 01:51:48 PM PDT 24
Finished Jun 02 01:51:50 PM PDT 24
Peak memory 236884 kb
Host smart-05ae8a48-5406-4261-aee1-c614ab28a79e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1125020157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1125020157
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1854196196
Short name T750
Test name
Test status
Simulation time 86465158 ps
CPU time 10.21 seconds
Started Jun 02 01:51:46 PM PDT 24
Finished Jun 02 01:51:56 PM PDT 24
Peak memory 248640 kb
Host smart-56745224-d22c-491b-9e8d-66ef2f2cecc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1854196196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1854196196
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2932527869
Short name T807
Test name
Test status
Simulation time 278914368 ps
CPU time 4.5 seconds
Started Jun 02 01:51:49 PM PDT 24
Finished Jun 02 01:51:54 PM PDT 24
Peak memory 252864 kb
Host smart-31aa342a-1659-4731-b897-b333ba599948
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2932527869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.2932527869
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3604363211
Short name T797
Test name
Test status
Simulation time 258731058 ps
CPU time 9.45 seconds
Started Jun 02 01:51:52 PM PDT 24
Finished Jun 02 01:52:02 PM PDT 24
Peak memory 240512 kb
Host smart-86f0ff98-dc62-4e95-aa97-1c5f7fb3d6c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604363211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.3604363211
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1257870558
Short name T794
Test name
Test status
Simulation time 36055662 ps
CPU time 3.62 seconds
Started Jun 02 01:51:55 PM PDT 24
Finished Jun 02 01:51:59 PM PDT 24
Peak memory 239720 kb
Host smart-f0b1b4e9-2f5f-4d8d-af24-35bc97af5384
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1257870558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.1257870558
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2837466324
Short name T165
Test name
Test status
Simulation time 6765162 ps
CPU time 1.43 seconds
Started Jun 02 01:51:54 PM PDT 24
Finished Jun 02 01:51:56 PM PDT 24
Peak memory 235932 kb
Host smart-9aa2a63e-5506-45d7-8c3a-9ac79966581e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2837466324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.2837466324
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3256791931
Short name T183
Test name
Test status
Simulation time 1166605019 ps
CPU time 22.47 seconds
Started Jun 02 01:51:52 PM PDT 24
Finished Jun 02 01:52:15 PM PDT 24
Peak memory 244168 kb
Host smart-39919ffa-0caa-4a4b-b0a4-cd06b9eacbac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3256791931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.3256791931
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.674161243
Short name T130
Test name
Test status
Simulation time 1778191020 ps
CPU time 93.75 seconds
Started Jun 02 01:51:51 PM PDT 24
Finished Jun 02 01:53:26 PM PDT 24
Peak memory 257164 kb
Host smart-5db9d116-700a-4353-b946-be29f76397e8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=674161243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_erro
rs.674161243
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2195568751
Short name T741
Test name
Test status
Simulation time 1086542995 ps
CPU time 17.66 seconds
Started Jun 02 01:51:54 PM PDT 24
Finished Jun 02 01:52:13 PM PDT 24
Peak memory 253888 kb
Host smart-986984de-949b-40f3-9199-c9b8a81762e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2195568751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2195568751
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3735965491
Short name T263
Test name
Test status
Simulation time 89808916 ps
CPU time 2.49 seconds
Started Jun 02 01:51:54 PM PDT 24
Finished Jun 02 01:51:57 PM PDT 24
Peak memory 236868 kb
Host smart-5b1a511e-a98d-4d6e-9a5d-828e9b785873
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3735965491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3735965491
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1789842329
Short name T814
Test name
Test status
Simulation time 40642901 ps
CPU time 5.66 seconds
Started Jun 02 01:51:52 PM PDT 24
Finished Jun 02 01:51:58 PM PDT 24
Peak memory 256412 kb
Host smart-90002432-afcb-4466-828a-e65f1bd0df88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789842329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1789842329
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1681820563
Short name T744
Test name
Test status
Simulation time 63573436 ps
CPU time 5.02 seconds
Started Jun 02 01:51:52 PM PDT 24
Finished Jun 02 01:51:57 PM PDT 24
Peak memory 235880 kb
Host smart-fbaee649-ce05-4fbb-9805-a17d03a50a5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1681820563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1681820563
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1772243849
Short name T738
Test name
Test status
Simulation time 306832573 ps
CPU time 20.89 seconds
Started Jun 02 01:51:54 PM PDT 24
Finished Jun 02 01:52:15 PM PDT 24
Peak memory 248632 kb
Host smart-0d1fa187-3cfc-40ec-8a9b-b969a0a2c84f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1772243849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.1772243849
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3145209181
Short name T152
Test name
Test status
Simulation time 51382894799 ps
CPU time 353.06 seconds
Started Jun 02 01:51:51 PM PDT 24
Finished Jun 02 01:57:45 PM PDT 24
Peak memory 273248 kb
Host smart-057df905-9b5b-41cd-8c36-47e4be11eb64
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3145209181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3145209181
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2704669197
Short name T151
Test name
Test status
Simulation time 2220365709 ps
CPU time 386.97 seconds
Started Jun 02 01:51:55 PM PDT 24
Finished Jun 02 01:58:22 PM PDT 24
Peak memory 265488 kb
Host smart-83afcf49-4ed4-4318-a394-81bf882c5630
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704669197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.2704669197
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1155649066
Short name T747
Test name
Test status
Simulation time 370058273 ps
CPU time 13.24 seconds
Started Jun 02 01:51:54 PM PDT 24
Finished Jun 02 01:52:07 PM PDT 24
Peak memory 252724 kb
Host smart-71372bc3-40eb-4669-a8d2-718097d82d3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1155649066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1155649066
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1591988824
Short name T757
Test name
Test status
Simulation time 1990982067 ps
CPU time 9.92 seconds
Started Jun 02 01:51:53 PM PDT 24
Finished Jun 02 01:52:03 PM PDT 24
Peak memory 240968 kb
Host smart-614014cf-ca3e-4f05-b25c-bc1ebaed40fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591988824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1591988824
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3234892301
Short name T795
Test name
Test status
Simulation time 128987858 ps
CPU time 5.32 seconds
Started Jun 02 01:51:53 PM PDT 24
Finished Jun 02 01:51:59 PM PDT 24
Peak memory 240364 kb
Host smart-601e4d0f-05d3-4d2e-a759-b6eb10a0904c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3234892301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3234892301
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2577951857
Short name T742
Test name
Test status
Simulation time 11203968 ps
CPU time 1.27 seconds
Started Jun 02 01:51:53 PM PDT 24
Finished Jun 02 01:51:55 PM PDT 24
Peak memory 234952 kb
Host smart-814b6358-1168-4a97-b113-f03732813597
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2577951857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2577951857
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1340896321
Short name T187
Test name
Test status
Simulation time 350387107 ps
CPU time 23.7 seconds
Started Jun 02 01:51:54 PM PDT 24
Finished Jun 02 01:52:18 PM PDT 24
Peak memory 245100 kb
Host smart-c5bee9bd-8115-4b49-8c2c-edddd2495804
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1340896321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1340896321
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3851873982
Short name T140
Test name
Test status
Simulation time 3073241685 ps
CPU time 193.35 seconds
Started Jun 02 01:51:53 PM PDT 24
Finished Jun 02 01:55:07 PM PDT 24
Peak memory 265368 kb
Host smart-5b10f930-1cb6-4fcb-9402-676f0490e531
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3851873982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3851873982
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3198314254
Short name T737
Test name
Test status
Simulation time 822675724 ps
CPU time 15.88 seconds
Started Jun 02 01:51:54 PM PDT 24
Finished Jun 02 01:52:11 PM PDT 24
Peak memory 252732 kb
Host smart-e6bf6cd2-1503-441b-8a2e-66213af878cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3198314254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3198314254
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1074908561
Short name T198
Test name
Test status
Simulation time 39076930 ps
CPU time 3.07 seconds
Started Jun 02 01:51:54 PM PDT 24
Finished Jun 02 01:51:57 PM PDT 24
Peak memory 236912 kb
Host smart-a370d0b0-b719-4589-80cd-d7ea5982be40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1074908561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1074908561
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.265147631
Short name T806
Test name
Test status
Simulation time 526955394 ps
CPU time 11.22 seconds
Started Jun 02 01:51:57 PM PDT 24
Finished Jun 02 01:52:09 PM PDT 24
Peak memory 250872 kb
Host smart-515fea34-bcfc-46ad-ace4-7af77964a20b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265147631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.265147631
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2607687181
Short name T816
Test name
Test status
Simulation time 376781342 ps
CPU time 5.04 seconds
Started Jun 02 01:52:00 PM PDT 24
Finished Jun 02 01:52:06 PM PDT 24
Peak memory 236808 kb
Host smart-7fd1a0df-1060-412c-a46e-c86a947bd935
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2607687181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2607687181
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1219091525
Short name T784
Test name
Test status
Simulation time 18591269 ps
CPU time 1.23 seconds
Started Jun 02 01:51:53 PM PDT 24
Finished Jun 02 01:51:55 PM PDT 24
Peak memory 236936 kb
Host smart-44709590-1d33-42dc-9fbd-39e21a97b949
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1219091525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1219091525
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3829798556
Short name T822
Test name
Test status
Simulation time 162666045 ps
CPU time 13.36 seconds
Started Jun 02 01:51:57 PM PDT 24
Finished Jun 02 01:52:11 PM PDT 24
Peak memory 245284 kb
Host smart-b0109742-6b0e-4701-a7ea-4c8a451e22bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3829798556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3829798556
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.385170304
Short name T723
Test name
Test status
Simulation time 345097699 ps
CPU time 11.27 seconds
Started Jun 02 01:51:52 PM PDT 24
Finished Jun 02 01:52:04 PM PDT 24
Peak memory 248720 kb
Host smart-d5b33fac-c2b5-499f-a58c-187c3afe7baf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=385170304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.385170304
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.442882021
Short name T788
Test name
Test status
Simulation time 218024806 ps
CPU time 5.11 seconds
Started Jun 02 01:52:00 PM PDT 24
Finished Jun 02 01:52:06 PM PDT 24
Peak memory 239592 kb
Host smart-dd1469a0-5b2b-46e5-9679-9a87c7ad1a59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442882021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.442882021
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.308408838
Short name T819
Test name
Test status
Simulation time 193800743 ps
CPU time 4.75 seconds
Started Jun 02 01:52:00 PM PDT 24
Finished Jun 02 01:52:05 PM PDT 24
Peak memory 236828 kb
Host smart-42cdc802-c13a-4bd5-b9f2-ae24ae318bc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=308408838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.308408838
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3848654906
Short name T739
Test name
Test status
Simulation time 18596530 ps
CPU time 1.36 seconds
Started Jun 02 01:51:58 PM PDT 24
Finished Jun 02 01:51:59 PM PDT 24
Peak memory 235992 kb
Host smart-e73ec621-5bcf-4284-9565-52b132675a7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3848654906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3848654906
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1833767912
Short name T758
Test name
Test status
Simulation time 655843566 ps
CPU time 25.57 seconds
Started Jun 02 01:51:57 PM PDT 24
Finished Jun 02 01:52:24 PM PDT 24
Peak memory 245056 kb
Host smart-5f844557-30f8-474d-9b73-39be881ad9d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1833767912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.1833767912
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.551416496
Short name T147
Test name
Test status
Simulation time 1455367634 ps
CPU time 97.89 seconds
Started Jun 02 01:52:01 PM PDT 24
Finished Jun 02 01:53:39 PM PDT 24
Peak memory 257104 kb
Host smart-ae65d07b-de57-4a14-8a75-23f55ec3ef1f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=551416496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_erro
rs.551416496
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2342871059
Short name T156
Test name
Test status
Simulation time 9158404968 ps
CPU time 747.88 seconds
Started Jun 02 01:52:01 PM PDT 24
Finished Jun 02 02:04:29 PM PDT 24
Peak memory 265416 kb
Host smart-1bde6c4e-b90e-4dbc-a090-be9b419a3998
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342871059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.2342871059
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.1373992462
Short name T718
Test name
Test status
Simulation time 330494041 ps
CPU time 11.88 seconds
Started Jun 02 01:51:59 PM PDT 24
Finished Jun 02 01:52:11 PM PDT 24
Peak memory 248696 kb
Host smart-9f1fcb86-dfaf-4c32-84b1-e1e9c4ecd716
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1373992462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.1373992462
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.264142888
Short name T174
Test name
Test status
Simulation time 937777974 ps
CPU time 9.04 seconds
Started Jun 02 01:51:58 PM PDT 24
Finished Jun 02 01:52:08 PM PDT 24
Peak memory 238244 kb
Host smart-b4042d47-3f03-49a1-aa69-10f090cee6c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264142888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.264142888
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2980670032
Short name T732
Test name
Test status
Simulation time 134732676 ps
CPU time 5.96 seconds
Started Jun 02 01:51:58 PM PDT 24
Finished Jun 02 01:52:04 PM PDT 24
Peak memory 236740 kb
Host smart-9f3fce35-4358-40d0-919a-39705e185eff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2980670032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2980670032
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2093198495
Short name T755
Test name
Test status
Simulation time 7645046 ps
CPU time 1.43 seconds
Started Jun 02 01:52:02 PM PDT 24
Finished Jun 02 01:52:04 PM PDT 24
Peak memory 236952 kb
Host smart-9de92211-017a-4222-814b-92510bfecf47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2093198495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2093198495
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.204380133
Short name T733
Test name
Test status
Simulation time 516311316 ps
CPU time 20.08 seconds
Started Jun 02 01:51:57 PM PDT 24
Finished Jun 02 01:52:18 PM PDT 24
Peak memory 245108 kb
Host smart-7e06813d-d587-4d4f-a714-28613eb659b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=204380133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_out
standing.204380133
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2781110498
Short name T805
Test name
Test status
Simulation time 6665701720 ps
CPU time 105.48 seconds
Started Jun 02 01:51:59 PM PDT 24
Finished Jun 02 01:53:44 PM PDT 24
Peak memory 266480 kb
Host smart-56836b21-9f09-4929-a4ad-3490d41e7716
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2781110498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.2781110498
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1736668084
Short name T344
Test name
Test status
Simulation time 17698762489 ps
CPU time 1284.48 seconds
Started Jun 02 01:51:57 PM PDT 24
Finished Jun 02 02:13:22 PM PDT 24
Peak memory 265544 kb
Host smart-53c914e6-c05c-4485-adf4-4b9930ba1005
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736668084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1736668084
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2813351577
Short name T237
Test name
Test status
Simulation time 1744003964 ps
CPU time 31.92 seconds
Started Jun 02 01:51:57 PM PDT 24
Finished Jun 02 01:52:29 PM PDT 24
Peak memory 246940 kb
Host smart-d65f652b-3202-4657-a6a1-f7d1bb18ed9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2813351577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.2813351577
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2780700608
Short name T830
Test name
Test status
Simulation time 113727500 ps
CPU time 5.06 seconds
Started Jun 02 01:52:04 PM PDT 24
Finished Jun 02 01:52:09 PM PDT 24
Peak memory 240368 kb
Host smart-d4d33f14-98e5-4320-a20d-cf6255cbe7e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780700608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2780700608
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2935288657
Short name T748
Test name
Test status
Simulation time 93357877 ps
CPU time 7.54 seconds
Started Jun 02 01:52:04 PM PDT 24
Finished Jun 02 01:52:12 PM PDT 24
Peak memory 235884 kb
Host smart-fa31c8e5-5533-4166-b588-a500c6928dae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2935288657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2935288657
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.4292329510
Short name T719
Test name
Test status
Simulation time 7829309 ps
CPU time 1.37 seconds
Started Jun 02 01:52:04 PM PDT 24
Finished Jun 02 01:52:05 PM PDT 24
Peak memory 235996 kb
Host smart-e1018045-94be-429c-a023-043f76ce96be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4292329510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.4292329510
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3981384180
Short name T730
Test name
Test status
Simulation time 328179085 ps
CPU time 12.08 seconds
Started Jun 02 01:52:05 PM PDT 24
Finished Jun 02 01:52:17 PM PDT 24
Peak memory 245052 kb
Host smart-725a2fba-754d-45ab-9410-9d6f2af0b43f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3981384180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3981384180
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.557811481
Short name T137
Test name
Test status
Simulation time 4408373041 ps
CPU time 704.96 seconds
Started Jun 02 01:51:59 PM PDT 24
Finished Jun 02 02:03:44 PM PDT 24
Peak memory 265384 kb
Host smart-30e8a8ee-e39d-460a-9399-c65a4a6b9597
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557811481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.557811481
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3603432943
Short name T803
Test name
Test status
Simulation time 548385254 ps
CPU time 19.19 seconds
Started Jun 02 01:51:57 PM PDT 24
Finished Jun 02 01:52:17 PM PDT 24
Peak memory 248636 kb
Host smart-85b8f183-2d75-4987-a1de-3587c283d95d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3603432943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3603432943
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2324530292
Short name T780
Test name
Test status
Simulation time 4518609645 ps
CPU time 152.29 seconds
Started Jun 02 01:51:31 PM PDT 24
Finished Jun 02 01:54:04 PM PDT 24
Peak memory 240648 kb
Host smart-38add8b6-1283-40bf-b651-23758458f62f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2324530292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.2324530292
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1187178310
Short name T180
Test name
Test status
Simulation time 22010830472 ps
CPU time 208.5 seconds
Started Jun 02 01:51:31 PM PDT 24
Finished Jun 02 01:55:00 PM PDT 24
Peak memory 240456 kb
Host smart-f316fd24-a176-4362-8a56-f648c820304d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1187178310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1187178310
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.696614703
Short name T820
Test name
Test status
Simulation time 987927556 ps
CPU time 10.12 seconds
Started Jun 02 01:51:37 PM PDT 24
Finished Jun 02 01:51:47 PM PDT 24
Peak memory 240500 kb
Host smart-b23cd466-d02a-42e8-b9f0-822191bc3452
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=696614703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.696614703
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.4176039212
Short name T176
Test name
Test status
Simulation time 543957113 ps
CPU time 9.26 seconds
Started Jun 02 01:51:32 PM PDT 24
Finished Jun 02 01:51:42 PM PDT 24
Peak memory 240504 kb
Host smart-3fdec553-7c22-4ea3-bcf8-ae311159f48e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176039212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.4176039212
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3525588924
Short name T821
Test name
Test status
Simulation time 98595955 ps
CPU time 5.46 seconds
Started Jun 02 01:51:31 PM PDT 24
Finished Jun 02 01:51:37 PM PDT 24
Peak memory 236824 kb
Host smart-02f995d7-2097-48e3-a50f-9b113a28e20a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3525588924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.3525588924
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1887405330
Short name T823
Test name
Test status
Simulation time 8301613 ps
CPU time 1.52 seconds
Started Jun 02 01:51:30 PM PDT 24
Finished Jun 02 01:51:32 PM PDT 24
Peak memory 234944 kb
Host smart-ec413405-92b0-45e1-a380-2e2a0d72709a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1887405330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1887405330
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.115427058
Short name T173
Test name
Test status
Simulation time 511953405 ps
CPU time 39.84 seconds
Started Jun 02 01:51:33 PM PDT 24
Finished Jun 02 01:52:13 PM PDT 24
Peak memory 245116 kb
Host smart-aa27b490-81da-4fe8-bfb7-a58959c2b20d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=115427058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs
tanding.115427058
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.4041403169
Short name T154
Test name
Test status
Simulation time 74306130229 ps
CPU time 661.2 seconds
Started Jun 02 01:51:31 PM PDT 24
Finished Jun 02 02:02:33 PM PDT 24
Peak memory 265516 kb
Host smart-918a394e-87b6-4746-a6bf-085ea8845c41
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041403169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.4041403169
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2379504114
Short name T713
Test name
Test status
Simulation time 403814532 ps
CPU time 4.42 seconds
Started Jun 02 01:51:31 PM PDT 24
Finished Jun 02 01:51:36 PM PDT 24
Peak memory 240416 kb
Host smart-b1ab24f0-8d30-4200-a776-0bbd6778ffc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2379504114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2379504114
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3454304166
Short name T764
Test name
Test status
Simulation time 14535437 ps
CPU time 1.29 seconds
Started Jun 02 01:52:05 PM PDT 24
Finished Jun 02 01:52:07 PM PDT 24
Peak memory 236104 kb
Host smart-fcd4443a-952a-4604-b05a-eedf2e3585f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3454304166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3454304166
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.881085817
Short name T790
Test name
Test status
Simulation time 8372126 ps
CPU time 1.54 seconds
Started Jun 02 01:52:05 PM PDT 24
Finished Jun 02 01:52:07 PM PDT 24
Peak memory 236900 kb
Host smart-040334e0-5358-43b6-825f-6d46a9be2bcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=881085817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.881085817
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3028567326
Short name T330
Test name
Test status
Simulation time 36055157 ps
CPU time 1.31 seconds
Started Jun 02 01:52:03 PM PDT 24
Finished Jun 02 01:52:05 PM PDT 24
Peak memory 235012 kb
Host smart-59062252-c201-4c3c-9b16-22f072c86480
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3028567326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.3028567326
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.832352294
Short name T815
Test name
Test status
Simulation time 68161174 ps
CPU time 1.43 seconds
Started Jun 02 01:52:04 PM PDT 24
Finished Jun 02 01:52:06 PM PDT 24
Peak memory 236752 kb
Host smart-b020032a-6862-4fad-9cf0-4ad54df5c297
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=832352294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.832352294
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1190902229
Short name T725
Test name
Test status
Simulation time 9803731 ps
CPU time 1.29 seconds
Started Jun 02 01:52:06 PM PDT 24
Finished Jun 02 01:52:08 PM PDT 24
Peak memory 235952 kb
Host smart-897ec24b-5572-42fb-b949-771335a10090
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1190902229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1190902229
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1409281690
Short name T799
Test name
Test status
Simulation time 9985527 ps
CPU time 1.63 seconds
Started Jun 02 01:52:05 PM PDT 24
Finished Jun 02 01:52:07 PM PDT 24
Peak memory 236944 kb
Host smart-89ccbb32-82cc-44c7-8bb2-3cd5e9a84202
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1409281690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1409281690
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3895513068
Short name T731
Test name
Test status
Simulation time 28152798 ps
CPU time 1.42 seconds
Started Jun 02 01:52:04 PM PDT 24
Finished Jun 02 01:52:05 PM PDT 24
Peak memory 235912 kb
Host smart-6bc71856-edca-40f9-86f1-03a4513828fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3895513068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3895513068
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2983948170
Short name T761
Test name
Test status
Simulation time 9377475 ps
CPU time 1.6 seconds
Started Jun 02 01:52:07 PM PDT 24
Finished Jun 02 01:52:09 PM PDT 24
Peak memory 235936 kb
Host smart-95776955-b9e7-46de-b911-0bbb4b26521a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2983948170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2983948170
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3615705711
Short name T336
Test name
Test status
Simulation time 11299870 ps
CPU time 1.39 seconds
Started Jun 02 01:52:07 PM PDT 24
Finished Jun 02 01:52:08 PM PDT 24
Peak memory 236888 kb
Host smart-126391b1-14f6-4adc-9b1a-f5e520843680
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3615705711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3615705711
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.878798252
Short name T800
Test name
Test status
Simulation time 7340097 ps
CPU time 1.48 seconds
Started Jun 02 01:52:06 PM PDT 24
Finished Jun 02 01:52:08 PM PDT 24
Peak memory 237040 kb
Host smart-dccae572-8552-4c17-b4a6-02b16c072c1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=878798252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.878798252
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.18651381
Short name T346
Test name
Test status
Simulation time 3459965897 ps
CPU time 258.96 seconds
Started Jun 02 01:51:37 PM PDT 24
Finished Jun 02 01:55:57 PM PDT 24
Peak memory 241540 kb
Host smart-64484407-670d-474a-b16b-a3f29696128b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=18651381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.18651381
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.993428585
Short name T825
Test name
Test status
Simulation time 99821298 ps
CPU time 5.07 seconds
Started Jun 02 01:51:38 PM PDT 24
Finished Jun 02 01:51:44 PM PDT 24
Peak memory 240368 kb
Host smart-986d215c-105f-467c-ae10-66e7dafe7b22
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=993428585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.993428585
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3004546404
Short name T753
Test name
Test status
Simulation time 635733568 ps
CPU time 5.99 seconds
Started Jun 02 01:51:39 PM PDT 24
Finished Jun 02 01:51:46 PM PDT 24
Peak memory 238944 kb
Host smart-1dd60164-b74b-48bd-bdac-ab845ef96847
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004546404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3004546404
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.331743285
Short name T817
Test name
Test status
Simulation time 70836742 ps
CPU time 6.07 seconds
Started Jun 02 01:51:38 PM PDT 24
Finished Jun 02 01:51:45 PM PDT 24
Peak memory 236788 kb
Host smart-4067bef7-d7b6-49a5-95d9-eda08fa82163
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=331743285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.331743285
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1295475716
Short name T775
Test name
Test status
Simulation time 8318640 ps
CPU time 1.36 seconds
Started Jun 02 01:51:33 PM PDT 24
Finished Jun 02 01:51:35 PM PDT 24
Peak memory 236880 kb
Host smart-2aa38cf5-6c11-4dd1-b6b8-ed28cc8ae6ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1295475716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1295475716
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.94030441
Short name T727
Test name
Test status
Simulation time 334666039 ps
CPU time 20.1 seconds
Started Jun 02 01:51:38 PM PDT 24
Finished Jun 02 01:51:58 PM PDT 24
Peak memory 248924 kb
Host smart-d92e7b39-ff33-46bb-acca-dd790b718492
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=94030441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outst
anding.94030441
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1263707412
Short name T829
Test name
Test status
Simulation time 8279651375 ps
CPU time 699.68 seconds
Started Jun 02 01:51:31 PM PDT 24
Finished Jun 02 02:03:12 PM PDT 24
Peak memory 265412 kb
Host smart-5810afbb-22ca-4fbd-8a37-9e3b9ccbd9dd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263707412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1263707412
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.529753940
Short name T751
Test name
Test status
Simulation time 318219649 ps
CPU time 22.07 seconds
Started Jun 02 01:51:32 PM PDT 24
Finished Jun 02 01:51:55 PM PDT 24
Peak memory 247588 kb
Host smart-75b1c2a8-a4f2-48cd-852b-bcd9331786fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=529753940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.529753940
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.4103628845
Short name T769
Test name
Test status
Simulation time 26113644 ps
CPU time 1.35 seconds
Started Jun 02 01:52:06 PM PDT 24
Finished Jun 02 01:52:08 PM PDT 24
Peak memory 235964 kb
Host smart-c8cfb5f3-ea88-4745-aacc-afda0abfc1c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4103628845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.4103628845
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2008589735
Short name T339
Test name
Test status
Simulation time 6281484 ps
CPU time 1.48 seconds
Started Jun 02 01:52:03 PM PDT 24
Finished Jun 02 01:52:04 PM PDT 24
Peak memory 235004 kb
Host smart-097beb9b-c681-458f-b39a-68f653514a98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2008589735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2008589735
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1387155280
Short name T802
Test name
Test status
Simulation time 14027407 ps
CPU time 1.28 seconds
Started Jun 02 01:52:05 PM PDT 24
Finished Jun 02 01:52:07 PM PDT 24
Peak memory 236944 kb
Host smart-46e93542-f4b2-43ae-b05b-b87a82c917bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1387155280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1387155280
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3046806623
Short name T783
Test name
Test status
Simulation time 10891971 ps
CPU time 1.36 seconds
Started Jun 02 01:52:05 PM PDT 24
Finished Jun 02 01:52:07 PM PDT 24
Peak memory 236928 kb
Host smart-92cd98eb-2b37-491a-9f46-93ea424846e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3046806623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3046806623
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3032789718
Short name T740
Test name
Test status
Simulation time 8633740 ps
CPU time 1.41 seconds
Started Jun 02 01:52:07 PM PDT 24
Finished Jun 02 01:52:08 PM PDT 24
Peak memory 236020 kb
Host smart-d1dec1e6-a4e8-4718-9266-8e0449f5f4e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3032789718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3032789718
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2178141220
Short name T335
Test name
Test status
Simulation time 7737092 ps
CPU time 1.47 seconds
Started Jun 02 01:52:04 PM PDT 24
Finished Jun 02 01:52:06 PM PDT 24
Peak memory 236884 kb
Host smart-f2a91f82-f189-42f4-9313-ed834ea865d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2178141220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2178141220
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.631416763
Short name T771
Test name
Test status
Simulation time 9677304 ps
CPU time 1.32 seconds
Started Jun 02 01:52:05 PM PDT 24
Finished Jun 02 01:52:07 PM PDT 24
Peak memory 236908 kb
Host smart-2e101a74-6f4c-40fa-ab96-09368b0816d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=631416763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.631416763
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1287621047
Short name T752
Test name
Test status
Simulation time 19730523 ps
CPU time 1.31 seconds
Started Jun 02 01:52:04 PM PDT 24
Finished Jun 02 01:52:06 PM PDT 24
Peak memory 236868 kb
Host smart-88687b26-6dad-405c-b8cd-9cbb88f6e3c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1287621047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1287621047
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.10747712
Short name T763
Test name
Test status
Simulation time 9054097 ps
CPU time 1.49 seconds
Started Jun 02 01:52:07 PM PDT 24
Finished Jun 02 01:52:09 PM PDT 24
Peak memory 234940 kb
Host smart-07ce67ee-7672-4708-8d8c-21547461b7d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=10747712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.10747712
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3899499805
Short name T182
Test name
Test status
Simulation time 7205980709 ps
CPU time 177.48 seconds
Started Jun 02 01:51:41 PM PDT 24
Finished Jun 02 01:54:39 PM PDT 24
Peak memory 240568 kb
Host smart-95f39992-bfdf-4aa9-8372-9edf290bcb79
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3899499805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3899499805
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.677320174
Short name T770
Test name
Test status
Simulation time 846285433 ps
CPU time 116.29 seconds
Started Jun 02 01:51:37 PM PDT 24
Finished Jun 02 01:53:33 PM PDT 24
Peak memory 240368 kb
Host smart-67dd0459-500e-48c1-b99b-4b924ab0d15d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=677320174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.677320174
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1090210530
Short name T716
Test name
Test status
Simulation time 397593330 ps
CPU time 8.47 seconds
Started Jun 02 01:51:35 PM PDT 24
Finished Jun 02 01:51:44 PM PDT 24
Peak memory 240384 kb
Host smart-b91d47e6-438e-41a7-9c52-2154af9467e4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1090210530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1090210530
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3804323191
Short name T808
Test name
Test status
Simulation time 683571865 ps
CPU time 11.52 seconds
Started Jun 02 01:51:38 PM PDT 24
Finished Jun 02 01:51:50 PM PDT 24
Peak memory 238648 kb
Host smart-925efab8-6ad8-4403-9b73-f0c70e8a32f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804323191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.3804323191
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2975418527
Short name T789
Test name
Test status
Simulation time 51704831 ps
CPU time 4.63 seconds
Started Jun 02 01:51:37 PM PDT 24
Finished Jun 02 01:51:42 PM PDT 24
Peak memory 235840 kb
Host smart-05003bd7-6e16-4aeb-ae83-d60ce20abf70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2975418527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2975418527
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2763274566
Short name T776
Test name
Test status
Simulation time 9746048 ps
CPU time 1.3 seconds
Started Jun 02 01:51:38 PM PDT 24
Finished Jun 02 01:51:40 PM PDT 24
Peak memory 236928 kb
Host smart-7d395ffa-c669-4ef1-9684-33f2c7821330
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2763274566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2763274566
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.196475654
Short name T726
Test name
Test status
Simulation time 1431631743 ps
CPU time 36.3 seconds
Started Jun 02 01:51:39 PM PDT 24
Finished Jun 02 01:52:16 PM PDT 24
Peak memory 248648 kb
Host smart-6d066a31-b8e9-47bb-9ace-dc80e307ac6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=196475654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outs
tanding.196475654
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.4036977676
Short name T155
Test name
Test status
Simulation time 3918247270 ps
CPU time 307.78 seconds
Started Jun 02 01:51:39 PM PDT 24
Finished Jun 02 01:56:47 PM PDT 24
Peak memory 265364 kb
Host smart-609c5402-ce47-4f13-9bdd-8e370e6e7258
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4036977676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.4036977676
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3124548161
Short name T824
Test name
Test status
Simulation time 34298436398 ps
CPU time 1288.93 seconds
Started Jun 02 01:51:39 PM PDT 24
Finished Jun 02 02:13:09 PM PDT 24
Peak memory 265492 kb
Host smart-f9c95941-6a73-4669-b581-902bba13fff1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124548161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.3124548161
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2154631066
Short name T724
Test name
Test status
Simulation time 41342311 ps
CPU time 5.97 seconds
Started Jun 02 01:51:39 PM PDT 24
Finished Jun 02 01:51:45 PM PDT 24
Peak memory 247156 kb
Host smart-3b0d63c0-542a-45cb-bad5-318d46e82159
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2154631066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2154631066
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1501491710
Short name T345
Test name
Test status
Simulation time 2458369889 ps
CPU time 46.45 seconds
Started Jun 02 01:51:39 PM PDT 24
Finished Jun 02 01:52:26 PM PDT 24
Peak memory 245136 kb
Host smart-9f871905-ec22-4f91-8fbe-fdfba2db6cf7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1501491710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1501491710
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3481328718
Short name T766
Test name
Test status
Simulation time 22143548 ps
CPU time 1.24 seconds
Started Jun 02 01:52:08 PM PDT 24
Finished Jun 02 01:52:09 PM PDT 24
Peak memory 234816 kb
Host smart-97efb674-267d-4d71-9980-ea135b7073e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3481328718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3481328718
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3361487609
Short name T781
Test name
Test status
Simulation time 7714265 ps
CPU time 1.42 seconds
Started Jun 02 01:52:08 PM PDT 24
Finished Jun 02 01:52:10 PM PDT 24
Peak memory 235872 kb
Host smart-cece6920-49e2-4ad5-991b-a5b0ff2a2ae8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3361487609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3361487609
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2171938742
Short name T756
Test name
Test status
Simulation time 14524377 ps
CPU time 1.18 seconds
Started Jun 02 01:52:07 PM PDT 24
Finished Jun 02 01:52:09 PM PDT 24
Peak memory 236928 kb
Host smart-492d065b-eb99-497f-af2a-5bdfff4887ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2171938742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2171938742
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3247326647
Short name T798
Test name
Test status
Simulation time 8847175 ps
CPU time 1.61 seconds
Started Jun 02 01:52:08 PM PDT 24
Finished Jun 02 01:52:10 PM PDT 24
Peak memory 236924 kb
Host smart-59ab06c6-058c-4135-82fa-3cdfe067d457
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3247326647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3247326647
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3185775024
Short name T333
Test name
Test status
Simulation time 8433208 ps
CPU time 1.49 seconds
Started Jun 02 01:52:06 PM PDT 24
Finished Jun 02 01:52:08 PM PDT 24
Peak memory 236892 kb
Host smart-a9739833-d739-444d-a887-163cc839016d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3185775024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3185775024
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.1471981232
Short name T722
Test name
Test status
Simulation time 11740268 ps
CPU time 1.54 seconds
Started Jun 02 01:52:10 PM PDT 24
Finished Jun 02 01:52:12 PM PDT 24
Peak memory 236884 kb
Host smart-ec0ca2d9-8575-4634-9eaa-bb6a00b07997
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1471981232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.1471981232
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.181255081
Short name T760
Test name
Test status
Simulation time 14323279 ps
CPU time 1.35 seconds
Started Jun 02 01:52:10 PM PDT 24
Finished Jun 02 01:52:11 PM PDT 24
Peak memory 236884 kb
Host smart-5b9bbcd4-dfb8-448d-b9f3-b038e5184105
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=181255081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.181255081
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3887514299
Short name T332
Test name
Test status
Simulation time 24800498 ps
CPU time 1.32 seconds
Started Jun 02 01:52:08 PM PDT 24
Finished Jun 02 01:52:10 PM PDT 24
Peak memory 234972 kb
Host smart-9d5db0de-193a-496e-a920-91907825e5c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3887514299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3887514299
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2432810425
Short name T768
Test name
Test status
Simulation time 10838495 ps
CPU time 1.35 seconds
Started Jun 02 01:52:08 PM PDT 24
Finished Jun 02 01:52:09 PM PDT 24
Peak memory 236936 kb
Host smart-3036bf10-47e1-40f5-be8e-d0281b87f9d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2432810425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2432810425
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.526197275
Short name T796
Test name
Test status
Simulation time 276912744 ps
CPU time 11.55 seconds
Started Jun 02 01:51:37 PM PDT 24
Finished Jun 02 01:51:49 PM PDT 24
Peak memory 248728 kb
Host smart-60f21961-7979-456b-9695-0231918eca24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526197275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.526197275
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.4259707124
Short name T785
Test name
Test status
Simulation time 239644298 ps
CPU time 9.57 seconds
Started Jun 02 01:51:38 PM PDT 24
Finished Jun 02 01:51:48 PM PDT 24
Peak memory 240376 kb
Host smart-19d7d368-2ca8-4a4d-b386-b6e905bc27a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4259707124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.4259707124
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1917291345
Short name T337
Test name
Test status
Simulation time 15709902 ps
CPU time 1.51 seconds
Started Jun 02 01:51:40 PM PDT 24
Finished Jun 02 01:51:42 PM PDT 24
Peak memory 236864 kb
Host smart-586f15cc-62f4-4d66-a6fe-3e58795f9766
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1917291345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1917291345
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2382666782
Short name T791
Test name
Test status
Simulation time 1069718725 ps
CPU time 44.09 seconds
Started Jun 02 01:51:36 PM PDT 24
Finished Jun 02 01:52:21 PM PDT 24
Peak memory 248636 kb
Host smart-13dbb54d-aa58-45f5-81ea-51ea3030eb3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2382666782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.2382666782
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.292031031
Short name T818
Test name
Test status
Simulation time 33259784026 ps
CPU time 595.45 seconds
Started Jun 02 01:51:38 PM PDT 24
Finished Jun 02 02:01:34 PM PDT 24
Peak memory 268856 kb
Host smart-08055664-1db4-4596-982e-d9321d2d49af
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292031031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.292031031
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3384672968
Short name T793
Test name
Test status
Simulation time 95053404 ps
CPU time 8.4 seconds
Started Jun 02 01:51:39 PM PDT 24
Finished Jun 02 01:51:48 PM PDT 24
Peak memory 252436 kb
Host smart-82dfdd7a-ce20-49a6-9242-daa0fdd56910
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3384672968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3384672968
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2010665837
Short name T754
Test name
Test status
Simulation time 249110411 ps
CPU time 6.28 seconds
Started Jun 02 01:51:42 PM PDT 24
Finished Jun 02 01:51:49 PM PDT 24
Peak memory 256452 kb
Host smart-89d8a30d-8f82-4007-bfda-db53b077c3a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010665837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2010665837
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2614420845
Short name T762
Test name
Test status
Simulation time 67285931 ps
CPU time 5.17 seconds
Started Jun 02 01:51:37 PM PDT 24
Finished Jun 02 01:51:43 PM PDT 24
Peak memory 236776 kb
Host smart-fc157263-164e-4a4e-bd9d-bc4717e515a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2614420845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2614420845
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1431726332
Short name T786
Test name
Test status
Simulation time 24142092 ps
CPU time 1.21 seconds
Started Jun 02 01:51:42 PM PDT 24
Finished Jun 02 01:51:43 PM PDT 24
Peak memory 236796 kb
Host smart-22fb1c7e-0842-409b-9ebe-0f3cbb5d327c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1431726332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1431726332
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.4014876548
Short name T792
Test name
Test status
Simulation time 87302427 ps
CPU time 12.59 seconds
Started Jun 02 01:51:38 PM PDT 24
Finished Jun 02 01:51:51 PM PDT 24
Peak memory 245104 kb
Host smart-71649eb9-9dc4-4591-8315-fdd82c35efa0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4014876548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.4014876548
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2462010170
Short name T139
Test name
Test status
Simulation time 18365324558 ps
CPU time 760.84 seconds
Started Jun 02 01:51:38 PM PDT 24
Finished Jun 02 02:04:19 PM PDT 24
Peak memory 273496 kb
Host smart-89a53d23-7b09-4244-bfa2-3cc0038163a9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462010170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2462010170
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2090405726
Short name T712
Test name
Test status
Simulation time 1025705098 ps
CPU time 16.38 seconds
Started Jun 02 01:51:36 PM PDT 24
Finished Jun 02 01:51:53 PM PDT 24
Peak memory 248700 kb
Host smart-ac0a2446-4405-441d-a388-05ee10d8afe8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2090405726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2090405726
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.440707485
Short name T199
Test name
Test status
Simulation time 90520566 ps
CPU time 6.99 seconds
Started Jun 02 01:51:42 PM PDT 24
Finished Jun 02 01:51:50 PM PDT 24
Peak memory 239772 kb
Host smart-667b3e41-0b4e-4dc2-8ff0-cd30e8308a3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440707485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.440707485
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.25165284
Short name T810
Test name
Test status
Simulation time 1215916149 ps
CPU time 10.77 seconds
Started Jun 02 01:51:43 PM PDT 24
Finished Jun 02 01:51:54 PM PDT 24
Peak memory 240324 kb
Host smart-507c34ef-8bd9-4e60-8e68-19b2ae8f132b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=25165284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.25165284
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1871655644
Short name T767
Test name
Test status
Simulation time 31332437 ps
CPU time 1.3 seconds
Started Jun 02 01:51:42 PM PDT 24
Finished Jun 02 01:51:44 PM PDT 24
Peak memory 236908 kb
Host smart-16d9a0e0-4635-4b35-a2bd-5a2281189c56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1871655644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1871655644
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.589068097
Short name T787
Test name
Test status
Simulation time 667345697 ps
CPU time 45.72 seconds
Started Jun 02 01:51:43 PM PDT 24
Finished Jun 02 01:52:29 PM PDT 24
Peak memory 245064 kb
Host smart-3a561a22-8453-4544-b135-07a52e02fc27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=589068097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outs
tanding.589068097
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.419252717
Short name T135
Test name
Test status
Simulation time 6994074031 ps
CPU time 200.38 seconds
Started Jun 02 01:51:41 PM PDT 24
Finished Jun 02 01:55:02 PM PDT 24
Peak memory 265412 kb
Host smart-0e3bb73a-f1f9-48f7-af1a-46954acaa038
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=419252717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_error
s.419252717
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.792978161
Short name T153
Test name
Test status
Simulation time 15168192943 ps
CPU time 1154.42 seconds
Started Jun 02 01:51:41 PM PDT 24
Finished Jun 02 02:10:56 PM PDT 24
Peak memory 265352 kb
Host smart-56f2001d-ddc6-45fb-a6ef-0e9129bc5a25
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792978161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.792978161
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3323360853
Short name T779
Test name
Test status
Simulation time 108904102 ps
CPU time 7.9 seconds
Started Jun 02 01:51:41 PM PDT 24
Finished Jun 02 01:51:50 PM PDT 24
Peak memory 247812 kb
Host smart-ce8ad50c-e5f1-49d7-ab2f-961b634a66f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3323360853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3323360853
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1935064523
Short name T161
Test name
Test status
Simulation time 101186648 ps
CPU time 2.47 seconds
Started Jun 02 01:51:42 PM PDT 24
Finished Jun 02 01:51:45 PM PDT 24
Peak memory 236916 kb
Host smart-f647a3d3-c324-41c1-af63-8f07957d820f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1935064523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.1935064523
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3400014142
Short name T811
Test name
Test status
Simulation time 1958250462 ps
CPU time 9.32 seconds
Started Jun 02 01:51:41 PM PDT 24
Finished Jun 02 01:51:51 PM PDT 24
Peak memory 239996 kb
Host smart-65df0ac3-fed3-4dec-ab2a-0554f10147e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400014142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3400014142
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2748795353
Short name T736
Test name
Test status
Simulation time 62307363 ps
CPU time 6.01 seconds
Started Jun 02 01:51:44 PM PDT 24
Finished Jun 02 01:51:51 PM PDT 24
Peak memory 236800 kb
Host smart-c329c2c6-7d74-4243-85c1-0f7f0da7b52c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2748795353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2748795353
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2598878629
Short name T334
Test name
Test status
Simulation time 15819310 ps
CPU time 1.32 seconds
Started Jun 02 01:51:50 PM PDT 24
Finished Jun 02 01:51:52 PM PDT 24
Peak memory 234964 kb
Host smart-3490e67e-8d71-4fde-8d9e-d96e3bf6bfee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2598878629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2598878629
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2651205384
Short name T729
Test name
Test status
Simulation time 668694353 ps
CPU time 42.39 seconds
Started Jun 02 01:51:45 PM PDT 24
Finished Jun 02 01:52:28 PM PDT 24
Peak memory 248648 kb
Host smart-30c3c348-4796-401d-96b4-85ec566d0adf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2651205384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2651205384
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2799014503
Short name T133
Test name
Test status
Simulation time 4126502541 ps
CPU time 275.79 seconds
Started Jun 02 01:51:41 PM PDT 24
Finished Jun 02 01:56:18 PM PDT 24
Peak memory 272684 kb
Host smart-485e3a4e-88bc-45b1-bc76-5404f0d6d07d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2799014503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.2799014503
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.4235052144
Short name T143
Test name
Test status
Simulation time 15949247895 ps
CPU time 622.25 seconds
Started Jun 02 01:51:42 PM PDT 24
Finished Jun 02 02:02:04 PM PDT 24
Peak memory 265456 kb
Host smart-1f8954e7-e28a-4cb5-8f89-1f5f6b0a7f68
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235052144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.4235052144
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1720149469
Short name T735
Test name
Test status
Simulation time 651863296 ps
CPU time 12.46 seconds
Started Jun 02 01:51:43 PM PDT 24
Finished Jun 02 01:51:55 PM PDT 24
Peak memory 253504 kb
Host smart-9de19ace-0943-4351-bbca-bf9462a7c487
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1720149469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1720149469
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2601067700
Short name T809
Test name
Test status
Simulation time 51236211 ps
CPU time 2.61 seconds
Started Jun 02 01:51:41 PM PDT 24
Finished Jun 02 01:51:43 PM PDT 24
Peak memory 235992 kb
Host smart-c9ee8122-f9b9-4172-a198-1ec0dbaa1ae9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2601067700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2601067700
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1052859075
Short name T721
Test name
Test status
Simulation time 103507494 ps
CPU time 9.04 seconds
Started Jun 02 01:51:51 PM PDT 24
Finished Jun 02 01:52:00 PM PDT 24
Peak memory 240504 kb
Host smart-b3b25a8b-e4f6-4dbb-a04d-f0e8b3189cef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052859075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.1052859075
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3421894686
Short name T728
Test name
Test status
Simulation time 138900835 ps
CPU time 5.46 seconds
Started Jun 02 01:51:44 PM PDT 24
Finished Jun 02 01:51:50 PM PDT 24
Peak memory 239672 kb
Host smart-173dfb5f-e370-4080-a956-304ac2a88ffc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3421894686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3421894686
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.162305088
Short name T338
Test name
Test status
Simulation time 27252813 ps
CPU time 1.69 seconds
Started Jun 02 01:51:43 PM PDT 24
Finished Jun 02 01:51:45 PM PDT 24
Peak memory 236836 kb
Host smart-a1276243-4fd2-41b5-ae57-d490cff8ebbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=162305088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.162305088
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.4186935087
Short name T179
Test name
Test status
Simulation time 371750980 ps
CPU time 26.76 seconds
Started Jun 02 01:51:41 PM PDT 24
Finished Jun 02 01:52:08 PM PDT 24
Peak memory 245064 kb
Host smart-011d7a57-5cfb-488a-98a1-17d97d9306e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4186935087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.4186935087
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.4283734790
Short name T827
Test name
Test status
Simulation time 3544901004 ps
CPU time 108.97 seconds
Started Jun 02 01:51:49 PM PDT 24
Finished Jun 02 01:53:38 PM PDT 24
Peak memory 265412 kb
Host smart-a3f4f36f-a9e0-45fb-b2b5-53c88cb72fa7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4283734790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.4283734790
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.2865319829
Short name T238
Test name
Test status
Simulation time 1736898870 ps
CPU time 9.84 seconds
Started Jun 02 01:51:41 PM PDT 24
Finished Jun 02 01:51:52 PM PDT 24
Peak memory 248260 kb
Host smart-a1f3ff64-87d7-4d82-af4d-22f18a64325d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2865319829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.2865319829
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3097374158
Short name T378
Test name
Test status
Simulation time 29557927759 ps
CPU time 1596.01 seconds
Started Jun 02 01:52:52 PM PDT 24
Finished Jun 02 02:19:29 PM PDT 24
Peak memory 273368 kb
Host smart-168f93f2-0656-41af-bc39-a27d74a6b203
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097374158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3097374158
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.767410830
Short name T556
Test name
Test status
Simulation time 1026673408 ps
CPU time 25.66 seconds
Started Jun 02 01:52:50 PM PDT 24
Finished Jun 02 01:53:16 PM PDT 24
Peak memory 251380 kb
Host smart-117816cb-23e6-41ff-9247-b300a97f89c4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=767410830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.767410830
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.4200207543
Short name T72
Test name
Test status
Simulation time 3003282623 ps
CPU time 63.42 seconds
Started Jun 02 01:52:52 PM PDT 24
Finished Jun 02 01:53:56 PM PDT 24
Peak memory 256888 kb
Host smart-417b49db-f6e4-419f-a52b-0d140f98b6a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42002
07543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.4200207543
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2317429297
Short name T612
Test name
Test status
Simulation time 1107484559 ps
CPU time 28.05 seconds
Started Jun 02 01:52:52 PM PDT 24
Finished Jun 02 01:53:20 PM PDT 24
Peak memory 255996 kb
Host smart-fc8d22af-308d-4f7a-8e5b-d6357c46ac0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23174
29297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2317429297
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.2208820681
Short name T537
Test name
Test status
Simulation time 58895594762 ps
CPU time 1685.21 seconds
Started Jun 02 01:52:51 PM PDT 24
Finished Jun 02 02:20:56 PM PDT 24
Peak memory 272696 kb
Host smart-d9b205ad-5549-4b26-b6c5-a9500ef6b76e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208820681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2208820681
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.1601565930
Short name T647
Test name
Test status
Simulation time 114365663 ps
CPU time 11.39 seconds
Started Jun 02 01:52:51 PM PDT 24
Finished Jun 02 01:53:03 PM PDT 24
Peak memory 248752 kb
Host smart-da6e3ff5-dc0f-4ce8-b7f1-57d83208740a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16015
65930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1601565930
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.1531929658
Short name T417
Test name
Test status
Simulation time 918227763 ps
CPU time 32.5 seconds
Started Jun 02 01:52:52 PM PDT 24
Finished Jun 02 01:53:25 PM PDT 24
Peak memory 254740 kb
Host smart-e5897e5f-e17e-4f8f-804c-4334ebbf89ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15319
29658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.1531929658
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.106956044
Short name T576
Test name
Test status
Simulation time 913618403 ps
CPU time 50.76 seconds
Started Jun 02 01:52:52 PM PDT 24
Finished Jun 02 01:53:43 PM PDT 24
Peak memory 247540 kb
Host smart-093ba9b3-50d4-46a8-8f2f-73e977cf325f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10695
6044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.106956044
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1081009071
Short name T520
Test name
Test status
Simulation time 965972832 ps
CPU time 27.34 seconds
Started Jun 02 01:52:49 PM PDT 24
Finished Jun 02 01:53:17 PM PDT 24
Peak memory 248784 kb
Host smart-a4836859-9132-4f01-8019-95c2da9772ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10810
09071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1081009071
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.4203473813
Short name T414
Test name
Test status
Simulation time 4554906106 ps
CPU time 247.33 seconds
Started Jun 02 01:52:49 PM PDT 24
Finished Jun 02 01:56:57 PM PDT 24
Peak memory 256900 kb
Host smart-794a5e88-c153-4518-827f-6e52dd315943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42034
73813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.4203473813
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.2734220470
Short name T597
Test name
Test status
Simulation time 198730808 ps
CPU time 4.21 seconds
Started Jun 02 01:52:52 PM PDT 24
Finished Jun 02 01:52:57 PM PDT 24
Peak memory 240536 kb
Host smart-2813d1f1-0264-4add-bcc4-992e95ef2816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27342
20470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2734220470
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3024986605
Short name T667
Test name
Test status
Simulation time 32845752269 ps
CPU time 1815.71 seconds
Started Jun 02 01:52:50 PM PDT 24
Finished Jun 02 02:23:07 PM PDT 24
Peak memory 272900 kb
Host smart-8c830fab-dc44-41a5-a8b1-ac892f7715a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024986605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3024986605
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1415491228
Short name T358
Test name
Test status
Simulation time 43193175189 ps
CPU time 2282.61 seconds
Started Jun 02 01:52:51 PM PDT 24
Finished Jun 02 02:30:54 PM PDT 24
Peak memory 289092 kb
Host smart-6fc2a6f1-f91b-4e0f-a245-24d1a4aca2a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415491228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1415491228
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.1760856075
Short name T300
Test name
Test status
Simulation time 45152783969 ps
CPU time 480.62 seconds
Started Jun 02 01:52:52 PM PDT 24
Finished Jun 02 02:00:54 PM PDT 24
Peak memory 248304 kb
Host smart-13d0f55b-2cef-4963-8257-64f9213290b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760856075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1760856075
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2317243186
Short name T458
Test name
Test status
Simulation time 246102464 ps
CPU time 28.59 seconds
Started Jun 02 01:52:52 PM PDT 24
Finished Jun 02 01:53:21 PM PDT 24
Peak memory 248736 kb
Host smart-7bd57476-d8ed-42e2-af9c-3dbe56ee370b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23172
43186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2317243186
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2495633064
Short name T549
Test name
Test status
Simulation time 950076276 ps
CPU time 57.34 seconds
Started Jun 02 01:52:51 PM PDT 24
Finished Jun 02 01:53:49 PM PDT 24
Peak memory 255988 kb
Host smart-0d324fe2-5b90-4426-a80f-133a6aa519b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24956
33064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2495633064
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2494860922
Short name T276
Test name
Test status
Simulation time 213971487 ps
CPU time 24.11 seconds
Started Jun 02 01:52:51 PM PDT 24
Finished Jun 02 01:53:16 PM PDT 24
Peak memory 248964 kb
Host smart-e0714568-023e-411c-bb84-0c2e6b0ce152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24948
60922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2494860922
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.547531071
Short name T632
Test name
Test status
Simulation time 2919840065 ps
CPU time 44.62 seconds
Started Jun 02 01:52:52 PM PDT 24
Finished Jun 02 01:53:37 PM PDT 24
Peak memory 256948 kb
Host smart-9ccdf663-7460-4874-b04e-eed0c3e020a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54753
1071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.547531071
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.453181309
Short name T456
Test name
Test status
Simulation time 3962500742 ps
CPU time 86.81 seconds
Started Jun 02 01:52:51 PM PDT 24
Finished Jun 02 01:54:18 PM PDT 24
Peak memory 256948 kb
Host smart-b7a613bc-239a-4ba6-8ae6-2b7e91bdfd18
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453181309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.453181309
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.2393924128
Short name T260
Test name
Test status
Simulation time 234783523136 ps
CPU time 9189.87 seconds
Started Jun 02 01:52:54 PM PDT 24
Finished Jun 02 04:26:05 PM PDT 24
Peak memory 371264 kb
Host smart-6b458f9a-dcc9-4895-acb7-fa7e00bb4279
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393924128 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.2393924128
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3633692579
Short name T208
Test name
Test status
Simulation time 55516075 ps
CPU time 2.35 seconds
Started Jun 02 01:53:17 PM PDT 24
Finished Jun 02 01:53:19 PM PDT 24
Peak memory 248884 kb
Host smart-a1d693cc-0d95-480a-bbfc-a2db377579d2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3633692579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3633692579
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2920337003
Short name T426
Test name
Test status
Simulation time 87935336575 ps
CPU time 2584.69 seconds
Started Jun 02 01:53:20 PM PDT 24
Finished Jun 02 02:36:25 PM PDT 24
Peak memory 288384 kb
Host smart-7ef3bf1d-1e48-43aa-bf9d-544178630200
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920337003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2920337003
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3745120871
Short name T566
Test name
Test status
Simulation time 6202263002 ps
CPU time 25.86 seconds
Started Jun 02 01:53:17 PM PDT 24
Finished Jun 02 01:53:43 PM PDT 24
Peak memory 248740 kb
Host smart-eb55a140-a661-4f09-a387-b448dd104a44
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3745120871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3745120871
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.1659071493
Short name T405
Test name
Test status
Simulation time 705884985 ps
CPU time 34.54 seconds
Started Jun 02 01:53:16 PM PDT 24
Finished Jun 02 01:53:50 PM PDT 24
Peak memory 248740 kb
Host smart-dcad6d5f-dbe9-45c0-9345-310c8c49c253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16590
71493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.1659071493
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2531938031
Short name T279
Test name
Test status
Simulation time 118171135209 ps
CPU time 1239.12 seconds
Started Jun 02 01:53:16 PM PDT 24
Finished Jun 02 02:13:56 PM PDT 24
Peak memory 288920 kb
Host smart-e3c4d709-73dc-4845-8ef6-33769434294f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531938031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2531938031
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.3539661336
Short name T191
Test name
Test status
Simulation time 22890517336 ps
CPU time 1433.91 seconds
Started Jun 02 01:53:18 PM PDT 24
Finished Jun 02 02:17:12 PM PDT 24
Peak memory 289676 kb
Host smart-107ced68-15d6-40b5-b3ee-ddfde0300ae8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539661336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.3539661336
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.835373364
Short name T656
Test name
Test status
Simulation time 1433110115 ps
CPU time 27.99 seconds
Started Jun 02 01:53:18 PM PDT 24
Finished Jun 02 01:53:47 PM PDT 24
Peak memory 255996 kb
Host smart-eae989d8-8a1d-4c27-aeb1-9f70700975e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83537
3364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.835373364
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.1505801227
Short name T567
Test name
Test status
Simulation time 668298746 ps
CPU time 20.27 seconds
Started Jun 02 01:53:22 PM PDT 24
Finished Jun 02 01:53:43 PM PDT 24
Peak memory 255464 kb
Host smart-b37f6808-34f5-4398-b5ce-7dc801d86269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15058
01227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1505801227
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.1575552316
Short name T240
Test name
Test status
Simulation time 550757755 ps
CPU time 36.25 seconds
Started Jun 02 01:53:19 PM PDT 24
Finished Jun 02 01:53:56 PM PDT 24
Peak memory 248728 kb
Host smart-146f7710-3d9a-4259-9fe7-4988f840fd7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15755
52316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.1575552316
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1232047173
Short name T435
Test name
Test status
Simulation time 563706942 ps
CPU time 21.53 seconds
Started Jun 02 01:53:17 PM PDT 24
Finished Jun 02 01:53:39 PM PDT 24
Peak memory 248700 kb
Host smart-dda299a9-59c1-4419-bcc3-64eb6ffcadc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12320
47173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1232047173
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3148274153
Short name T124
Test name
Test status
Simulation time 8487106070 ps
CPU time 622.52 seconds
Started Jun 02 01:53:16 PM PDT 24
Finished Jun 02 02:03:39 PM PDT 24
Peak memory 270276 kb
Host smart-3e9bf1cb-ee75-4d79-a205-cb44fd5eaba6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148274153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3148274153
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3854434019
Short name T215
Test name
Test status
Simulation time 152000852 ps
CPU time 3.85 seconds
Started Jun 02 01:53:17 PM PDT 24
Finished Jun 02 01:53:21 PM PDT 24
Peak memory 248832 kb
Host smart-22808500-cf28-4b04-8c9e-1e70dd6d0305
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3854434019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3854434019
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.1843414843
Short name T497
Test name
Test status
Simulation time 61922437463 ps
CPU time 2061.68 seconds
Started Jun 02 01:53:18 PM PDT 24
Finished Jun 02 02:27:40 PM PDT 24
Peak memory 281588 kb
Host smart-cb1f650e-d9e1-4859-808c-69260a629e86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843414843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.1843414843
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1574214680
Short name T587
Test name
Test status
Simulation time 256744555 ps
CPU time 13.84 seconds
Started Jun 02 01:53:17 PM PDT 24
Finished Jun 02 01:53:31 PM PDT 24
Peak memory 248696 kb
Host smart-eee08ad5-f1ec-4ca1-ae3b-15ba8da2186e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1574214680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1574214680
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1733633016
Short name T593
Test name
Test status
Simulation time 1141858406 ps
CPU time 118.27 seconds
Started Jun 02 01:53:17 PM PDT 24
Finished Jun 02 01:55:16 PM PDT 24
Peak memory 256848 kb
Host smart-c62d6104-38e5-40ae-b8f7-cad697bdac72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17336
33016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1733633016
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.3222424461
Short name T383
Test name
Test status
Simulation time 435951133 ps
CPU time 27.58 seconds
Started Jun 02 01:53:17 PM PDT 24
Finished Jun 02 01:53:45 PM PDT 24
Peak memory 255648 kb
Host smart-706dddd9-2479-4b64-b145-1dc9d7b8fa36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32224
24461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3222424461
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.1266654905
Short name T622
Test name
Test status
Simulation time 16614695688 ps
CPU time 1092.29 seconds
Started Jun 02 01:53:16 PM PDT 24
Finished Jun 02 02:11:29 PM PDT 24
Peak memory 265208 kb
Host smart-b036a7e3-1cf9-47dc-ac0a-ae24d5cf50ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266654905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1266654905
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.2256100015
Short name T513
Test name
Test status
Simulation time 784573580 ps
CPU time 35.2 seconds
Started Jun 02 01:53:16 PM PDT 24
Finished Jun 02 01:53:51 PM PDT 24
Peak memory 248736 kb
Host smart-98f88b3d-481a-443d-9587-25b139cdeb70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22561
00015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.2256100015
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2873983780
Short name T189
Test name
Test status
Simulation time 1213554141 ps
CPU time 32.06 seconds
Started Jun 02 01:53:21 PM PDT 24
Finished Jun 02 01:53:53 PM PDT 24
Peak memory 254692 kb
Host smart-b4f8d73f-8e3e-4a2b-8c23-76b23536c956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28739
83780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2873983780
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.409442949
Short name T75
Test name
Test status
Simulation time 60525828 ps
CPU time 4.86 seconds
Started Jun 02 01:53:20 PM PDT 24
Finished Jun 02 01:53:25 PM PDT 24
Peak memory 239112 kb
Host smart-871bd4a9-4111-4beb-913d-21575d944756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40944
2949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.409442949
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.2569086168
Short name T354
Test name
Test status
Simulation time 1596461563 ps
CPU time 36.53 seconds
Started Jun 02 01:53:17 PM PDT 24
Finished Jun 02 01:53:54 PM PDT 24
Peak memory 255932 kb
Host smart-0821c365-e3ad-42b1-86a6-30b91af642bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25690
86168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2569086168
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3504799257
Short name T273
Test name
Test status
Simulation time 50969619922 ps
CPU time 753.7 seconds
Started Jun 02 01:53:18 PM PDT 24
Finished Jun 02 02:05:52 PM PDT 24
Peak memory 265144 kb
Host smart-098a2da0-1a89-4427-a6df-59bdc1fcb0bb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504799257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3504799257
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3029211462
Short name T201
Test name
Test status
Simulation time 13563266 ps
CPU time 2.58 seconds
Started Jun 02 01:53:24 PM PDT 24
Finished Jun 02 01:53:27 PM PDT 24
Peak memory 248884 kb
Host smart-f53a7493-99c7-41cb-ac4c-1484862f1747
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3029211462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3029211462
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.1801950785
Short name T368
Test name
Test status
Simulation time 57893775231 ps
CPU time 1421.63 seconds
Started Jun 02 01:53:17 PM PDT 24
Finished Jun 02 02:16:59 PM PDT 24
Peak memory 273348 kb
Host smart-2d18a808-8973-4188-9669-5f8831705531
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801950785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1801950785
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1956531384
Short name T655
Test name
Test status
Simulation time 739161981 ps
CPU time 13.53 seconds
Started Jun 02 01:53:24 PM PDT 24
Finished Jun 02 01:53:38 PM PDT 24
Peak memory 248688 kb
Host smart-5656ab50-9434-401a-affd-e1fb4d8877f2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1956531384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1956531384
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.1903673446
Short name T391
Test name
Test status
Simulation time 11399504577 ps
CPU time 162.28 seconds
Started Jun 02 01:53:18 PM PDT 24
Finished Jun 02 01:56:01 PM PDT 24
Peak memory 250156 kb
Host smart-53bc0fff-7f8e-4c03-847b-ee1c0a6fc52a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19036
73446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1903673446
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.490135203
Short name T614
Test name
Test status
Simulation time 1168261140 ps
CPU time 36.74 seconds
Started Jun 02 01:53:18 PM PDT 24
Finished Jun 02 01:53:55 PM PDT 24
Peak memory 254104 kb
Host smart-e0c30320-ac7d-430f-afa9-1a26450bcb56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49013
5203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.490135203
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3414413409
Short name T590
Test name
Test status
Simulation time 52759015967 ps
CPU time 1798.37 seconds
Started Jun 02 01:53:20 PM PDT 24
Finished Jun 02 02:23:19 PM PDT 24
Peak memory 273372 kb
Host smart-19ab7d05-5176-4707-b0ad-a08af49c8a41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414413409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3414413409
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.884598095
Short name T314
Test name
Test status
Simulation time 13303240073 ps
CPU time 489.91 seconds
Started Jun 02 01:53:22 PM PDT 24
Finished Jun 02 02:01:32 PM PDT 24
Peak memory 254852 kb
Host smart-42199e37-792d-4fe8-8fe1-1ba885852c3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884598095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.884598095
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2319180883
Short name T402
Test name
Test status
Simulation time 436830774 ps
CPU time 27.16 seconds
Started Jun 02 01:53:21 PM PDT 24
Finished Jun 02 01:53:48 PM PDT 24
Peak memory 255912 kb
Host smart-9708b746-2c4c-4148-ab27-f891fc928df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23191
80883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2319180883
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.2956715995
Short name T42
Test name
Test status
Simulation time 3408836684 ps
CPU time 53.19 seconds
Started Jun 02 01:53:20 PM PDT 24
Finished Jun 02 01:54:13 PM PDT 24
Peak memory 249232 kb
Host smart-21ee373f-3bed-40e5-bf01-889b0404f97b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29567
15995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2956715995
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.657589334
Short name T412
Test name
Test status
Simulation time 439742303 ps
CPU time 29.58 seconds
Started Jun 02 01:53:21 PM PDT 24
Finished Jun 02 01:53:51 PM PDT 24
Peak memory 255396 kb
Host smart-4d0ff0f3-7b18-442a-81bd-0f8d683a76ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65758
9334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.657589334
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2310704145
Short name T80
Test name
Test status
Simulation time 98812097 ps
CPU time 4.49 seconds
Started Jun 02 01:53:20 PM PDT 24
Finished Jun 02 01:53:25 PM PDT 24
Peak memory 240528 kb
Host smart-39ec2e4b-5642-4eb2-baad-f3d122ad6fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23107
04145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2310704145
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.4193652679
Short name T584
Test name
Test status
Simulation time 103783012175 ps
CPU time 1996.91 seconds
Started Jun 02 01:53:25 PM PDT 24
Finished Jun 02 02:26:42 PM PDT 24
Peak memory 281608 kb
Host smart-e2efcf7b-0faa-4f93-9cb4-547d15eacd4c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193652679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.4193652679
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.3797863644
Short name T227
Test name
Test status
Simulation time 244483860374 ps
CPU time 1342.8 seconds
Started Jun 02 01:53:23 PM PDT 24
Finished Jun 02 02:15:47 PM PDT 24
Peak memory 286844 kb
Host smart-a771d8bb-b1df-47ca-b2d5-252163c89407
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797863644 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.3797863644
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.29656965
Short name T74
Test name
Test status
Simulation time 32932609 ps
CPU time 2.8 seconds
Started Jun 02 01:53:24 PM PDT 24
Finished Jun 02 01:53:27 PM PDT 24
Peak memory 248892 kb
Host smart-566cbb7f-e16a-47ea-b5bd-8ede99441b6c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=29656965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.29656965
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2679052617
Short name T679
Test name
Test status
Simulation time 26771279131 ps
CPU time 1351.95 seconds
Started Jun 02 01:53:28 PM PDT 24
Finished Jun 02 02:16:01 PM PDT 24
Peak memory 287224 kb
Host smart-9ea5de87-9fb7-4b44-b069-7b7b98b6cc50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679052617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2679052617
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.331664581
Short name T519
Test name
Test status
Simulation time 149125758 ps
CPU time 9.02 seconds
Started Jun 02 01:53:24 PM PDT 24
Finished Jun 02 01:53:33 PM PDT 24
Peak memory 248760 kb
Host smart-5e754413-2bb0-4c6f-bcd6-98eedda7b816
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=331664581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.331664581
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3964414818
Short name T428
Test name
Test status
Simulation time 9375107108 ps
CPU time 142.44 seconds
Started Jun 02 01:53:24 PM PDT 24
Finished Jun 02 01:55:47 PM PDT 24
Peak memory 251228 kb
Host smart-7ceeb80e-80f7-4570-be42-9b340c9b6ccf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39644
14818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3964414818
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.239533380
Short name T397
Test name
Test status
Simulation time 1274615817 ps
CPU time 20.02 seconds
Started Jun 02 01:53:25 PM PDT 24
Finished Jun 02 01:53:45 PM PDT 24
Peak memory 255752 kb
Host smart-5a5926e8-d29e-4c87-bfd5-7096a122b6cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23953
3380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.239533380
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.247319602
Short name T455
Test name
Test status
Simulation time 20747812113 ps
CPU time 1190.17 seconds
Started Jun 02 01:53:25 PM PDT 24
Finished Jun 02 02:13:15 PM PDT 24
Peak memory 284532 kb
Host smart-1ff07908-d16b-4548-b1af-3691c39dc897
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247319602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.247319602
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.3519897551
Short name T77
Test name
Test status
Simulation time 134528736030 ps
CPU time 1900.73 seconds
Started Jun 02 01:53:24 PM PDT 24
Finished Jun 02 02:25:05 PM PDT 24
Peak memory 285200 kb
Host smart-19f34dc5-212d-4d27-839f-e160ae90ebe0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519897551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3519897551
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2679624613
Short name T545
Test name
Test status
Simulation time 1051832456 ps
CPU time 23.49 seconds
Started Jun 02 01:53:24 PM PDT 24
Finished Jun 02 01:53:48 PM PDT 24
Peak memory 248736 kb
Host smart-550f32e8-6e58-45f0-93ac-6607e2140795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26796
24613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2679624613
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.3563723743
Short name T379
Test name
Test status
Simulation time 744875014 ps
CPU time 28.79 seconds
Started Jun 02 01:53:26 PM PDT 24
Finished Jun 02 01:53:55 PM PDT 24
Peak memory 255592 kb
Host smart-a157a847-6b91-4f12-9ccc-bb9c28f86574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35637
23743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3563723743
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.4140323328
Short name T669
Test name
Test status
Simulation time 2487215028 ps
CPU time 48.01 seconds
Started Jun 02 01:53:23 PM PDT 24
Finished Jun 02 01:54:12 PM PDT 24
Peak memory 255640 kb
Host smart-9006575e-10b0-4590-a459-4a94aac8e4aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41403
23328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.4140323328
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3837311513
Short name T439
Test name
Test status
Simulation time 776104860 ps
CPU time 35.8 seconds
Started Jun 02 01:53:23 PM PDT 24
Finished Jun 02 01:53:59 PM PDT 24
Peak memory 248732 kb
Host smart-666647fa-625b-4a8a-ad54-a487faad5c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38373
11513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3837311513
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.1522245206
Short name T224
Test name
Test status
Simulation time 3597413942 ps
CPU time 62.97 seconds
Started Jun 02 01:53:24 PM PDT 24
Finished Jun 02 01:54:27 PM PDT 24
Peak memory 256424 kb
Host smart-9a34c767-d3de-4be1-80f0-6d95daa5c044
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522245206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.1522245206
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.2620319441
Short name T225
Test name
Test status
Simulation time 23285604186 ps
CPU time 1472.21 seconds
Started Jun 02 01:53:27 PM PDT 24
Finished Jun 02 02:18:00 PM PDT 24
Peak memory 273332 kb
Host smart-29b0dc33-5309-407a-b4be-650cb8e8bfcd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620319441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2620319441
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2747632681
Short name T580
Test name
Test status
Simulation time 1228684193 ps
CPU time 17.15 seconds
Started Jun 02 01:53:29 PM PDT 24
Finished Jun 02 01:53:46 PM PDT 24
Peak memory 240504 kb
Host smart-a4208453-2035-4347-b500-688bbcfc8e30
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2747632681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2747632681
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.3568360984
Short name T395
Test name
Test status
Simulation time 8047637951 ps
CPU time 117.24 seconds
Started Jun 02 01:53:24 PM PDT 24
Finished Jun 02 01:55:21 PM PDT 24
Peak memory 256952 kb
Host smart-8b0924b0-96c1-4518-98f8-da5694713f15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35683
60984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3568360984
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.2764977347
Short name T532
Test name
Test status
Simulation time 316416948 ps
CPU time 28.32 seconds
Started Jun 02 01:53:24 PM PDT 24
Finished Jun 02 01:53:53 PM PDT 24
Peak memory 255864 kb
Host smart-146a58a0-df51-4501-b70a-9b5254190895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27649
77347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2764977347
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.3683121764
Short name T320
Test name
Test status
Simulation time 37970325510 ps
CPU time 1566.43 seconds
Started Jun 02 01:53:29 PM PDT 24
Finished Jun 02 02:19:36 PM PDT 24
Peak memory 286468 kb
Host smart-4ab3158c-600a-4db2-9720-33114ea1a1a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683121764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3683121764
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.478101670
Short name T709
Test name
Test status
Simulation time 43403335799 ps
CPU time 849.6 seconds
Started Jun 02 01:53:28 PM PDT 24
Finished Jun 02 02:07:38 PM PDT 24
Peak memory 272840 kb
Host smart-406ab272-00f9-4365-b89d-79f68eb2603a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478101670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.478101670
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.1081945996
Short name T691
Test name
Test status
Simulation time 1035600054 ps
CPU time 22.8 seconds
Started Jun 02 01:53:27 PM PDT 24
Finished Jun 02 01:53:50 PM PDT 24
Peak memory 248856 kb
Host smart-3e0dd855-34c7-4c62-b062-b3da188c2cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10819
45996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.1081945996
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2748073812
Short name T421
Test name
Test status
Simulation time 837261264 ps
CPU time 15.28 seconds
Started Jun 02 01:53:24 PM PDT 24
Finished Jun 02 01:53:40 PM PDT 24
Peak memory 254856 kb
Host smart-eef30acb-247d-474e-bd4f-efad5e207908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27480
73812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2748073812
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.3283005655
Short name T544
Test name
Test status
Simulation time 270987774 ps
CPU time 17.44 seconds
Started Jun 02 01:53:25 PM PDT 24
Finished Jun 02 01:53:42 PM PDT 24
Peak memory 255448 kb
Host smart-6ac61032-59bd-44f2-a2a0-f005198e6e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32830
05655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3283005655
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.1933952212
Short name T367
Test name
Test status
Simulation time 44655337 ps
CPU time 4.89 seconds
Started Jun 02 01:53:27 PM PDT 24
Finished Jun 02 01:53:32 PM PDT 24
Peak memory 248680 kb
Host smart-c5aee05a-7af0-4b6f-b7ff-60c51ae12db9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19339
52212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1933952212
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3799354688
Short name T205
Test name
Test status
Simulation time 95785440 ps
CPU time 3.22 seconds
Started Jun 02 01:53:35 PM PDT 24
Finished Jun 02 01:53:38 PM PDT 24
Peak memory 248872 kb
Host smart-e8332d4e-cb94-4d60-b9c1-3117aec51025
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3799354688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3799354688
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.342811399
Short name T399
Test name
Test status
Simulation time 124898684474 ps
CPU time 2060.28 seconds
Started Jun 02 01:53:33 PM PDT 24
Finished Jun 02 02:27:54 PM PDT 24
Peak memory 281612 kb
Host smart-59c74bb3-6be3-4a4b-9028-8159ee2e0490
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342811399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.342811399
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.3146630221
Short name T452
Test name
Test status
Simulation time 412954410 ps
CPU time 19.1 seconds
Started Jun 02 01:53:29 PM PDT 24
Finished Jun 02 01:53:48 PM PDT 24
Peak memory 240540 kb
Host smart-f05bd716-fca5-445b-831c-229d7abf026f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3146630221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3146630221
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.982524826
Short name T610
Test name
Test status
Simulation time 12526985851 ps
CPU time 263.33 seconds
Started Jun 02 01:53:35 PM PDT 24
Finished Jun 02 01:57:58 PM PDT 24
Peak memory 251344 kb
Host smart-675a3b96-e306-4fad-943d-6ee6cfdccc19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98252
4826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.982524826
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.508250606
Short name T701
Test name
Test status
Simulation time 956866787 ps
CPU time 62.64 seconds
Started Jun 02 01:53:34 PM PDT 24
Finished Jun 02 01:54:37 PM PDT 24
Peak memory 248800 kb
Host smart-2b3c5456-555b-4502-a385-e8d4d9e9b708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50825
0606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.508250606
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.1975733366
Short name T502
Test name
Test status
Simulation time 11908439558 ps
CPU time 1000.89 seconds
Started Jun 02 01:53:29 PM PDT 24
Finished Jun 02 02:10:10 PM PDT 24
Peak memory 273304 kb
Host smart-5fd62f9c-2c79-47f8-bbb0-bfaf6ef88e85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975733366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1975733366
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.436659709
Short name T19
Test name
Test status
Simulation time 45918663415 ps
CPU time 2888.89 seconds
Started Jun 02 01:53:31 PM PDT 24
Finished Jun 02 02:41:40 PM PDT 24
Peak memory 285380 kb
Host smart-15bc4d07-855c-42de-bfef-5ccee1d8dbc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436659709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.436659709
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2987029494
Short name T294
Test name
Test status
Simulation time 3063317084 ps
CPU time 64.18 seconds
Started Jun 02 01:53:33 PM PDT 24
Finished Jun 02 01:54:38 PM PDT 24
Peak memory 252004 kb
Host smart-1d34c442-0bae-4dcd-8b72-b4c9ccd3b00b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987029494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2987029494
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3043801340
Short name T420
Test name
Test status
Simulation time 402169366 ps
CPU time 23.8 seconds
Started Jun 02 01:53:30 PM PDT 24
Finished Jun 02 01:53:54 PM PDT 24
Peak memory 255924 kb
Host smart-cf6996d9-0699-4010-9e7c-813e047b686a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30438
01340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3043801340
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3390965784
Short name T351
Test name
Test status
Simulation time 651554255 ps
CPU time 6.6 seconds
Started Jun 02 01:53:28 PM PDT 24
Finished Jun 02 01:53:35 PM PDT 24
Peak memory 250928 kb
Host smart-713aad7f-c3c0-491f-916f-c83904dcb4f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33909
65784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3390965784
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2923731244
Short name T636
Test name
Test status
Simulation time 1456826451 ps
CPU time 25.96 seconds
Started Jun 02 01:53:30 PM PDT 24
Finished Jun 02 01:53:56 PM PDT 24
Peak memory 255816 kb
Host smart-6b098a62-be28-43d0-81b2-ee6b157807c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29237
31244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2923731244
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1235948960
Short name T641
Test name
Test status
Simulation time 354719336 ps
CPU time 25.25 seconds
Started Jun 02 01:53:29 PM PDT 24
Finished Jun 02 01:53:54 PM PDT 24
Peak memory 256872 kb
Host smart-abbf46b2-e3fc-4719-8736-6dcac0681162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12359
48960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1235948960
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3795621972
Short name T381
Test name
Test status
Simulation time 1415443471 ps
CPU time 125.23 seconds
Started Jun 02 01:53:30 PM PDT 24
Finished Jun 02 01:55:35 PM PDT 24
Peak memory 256884 kb
Host smart-907e2a72-ebbf-4928-aaaa-f6751f716f0f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795621972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3795621972
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3012877169
Short name T245
Test name
Test status
Simulation time 49203969446 ps
CPU time 5332.98 seconds
Started Jun 02 01:53:33 PM PDT 24
Finished Jun 02 03:22:27 PM PDT 24
Peak memory 322532 kb
Host smart-f5eda59e-b351-455a-b125-faea3fee2df9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012877169 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3012877169
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.2693487801
Short name T214
Test name
Test status
Simulation time 62966765 ps
CPU time 3.56 seconds
Started Jun 02 01:53:34 PM PDT 24
Finished Jun 02 01:53:37 PM PDT 24
Peak memory 248868 kb
Host smart-1ea8d215-1185-4b3c-b1e7-936ef86b8ad2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2693487801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.2693487801
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1625206766
Short name T493
Test name
Test status
Simulation time 14886376928 ps
CPU time 718.41 seconds
Started Jun 02 01:53:29 PM PDT 24
Finished Jun 02 02:05:28 PM PDT 24
Peak memory 268220 kb
Host smart-46843a72-7948-4137-be70-6e1f54287af9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625206766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1625206766
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1427544894
Short name T441
Test name
Test status
Simulation time 302439396 ps
CPU time 16.05 seconds
Started Jun 02 01:53:35 PM PDT 24
Finished Jun 02 01:53:51 PM PDT 24
Peak memory 248652 kb
Host smart-6e9fb115-5375-4ad7-a91c-d3b3cf5dd2b9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1427544894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1427544894
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3315229204
Short name T528
Test name
Test status
Simulation time 394634577 ps
CPU time 39.05 seconds
Started Jun 02 01:53:32 PM PDT 24
Finished Jun 02 01:54:11 PM PDT 24
Peak memory 248772 kb
Host smart-094cf3a4-3e9b-4753-a53d-903cf47cc15c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33152
29204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3315229204
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.3871630759
Short name T70
Test name
Test status
Simulation time 568518530 ps
CPU time 35.56 seconds
Started Jun 02 01:53:32 PM PDT 24
Finished Jun 02 01:54:08 PM PDT 24
Peak memory 255776 kb
Host smart-b20e3303-b365-44a5-978c-bc866f0254bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38716
30759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3871630759
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.4277403719
Short name T326
Test name
Test status
Simulation time 42858114020 ps
CPU time 2299.99 seconds
Started Jun 02 01:53:29 PM PDT 24
Finished Jun 02 02:31:50 PM PDT 24
Peak memory 288168 kb
Host smart-2ce8b1d0-dfb8-4767-a757-b601555b828f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277403719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.4277403719
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.1551057355
Short name T352
Test name
Test status
Simulation time 124479626452 ps
CPU time 1856.47 seconds
Started Jun 02 01:53:32 PM PDT 24
Finished Jun 02 02:24:29 PM PDT 24
Peak memory 272768 kb
Host smart-16dc4664-5e7f-404e-a9c0-97a83c5c574f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551057355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1551057355
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2898284086
Short name T599
Test name
Test status
Simulation time 1847415004 ps
CPU time 26.84 seconds
Started Jun 02 01:53:30 PM PDT 24
Finished Jun 02 01:53:57 PM PDT 24
Peak memory 256000 kb
Host smart-05421978-c969-473b-9749-c65c2163d5a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28982
84086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2898284086
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1350310712
Short name T103
Test name
Test status
Simulation time 1149491719 ps
CPU time 24.52 seconds
Started Jun 02 01:53:30 PM PDT 24
Finished Jun 02 01:53:55 PM PDT 24
Peak memory 247720 kb
Host smart-4e5f3838-fdd7-44e6-bea0-576dcd3ea610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13503
10712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1350310712
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.537089873
Short name T475
Test name
Test status
Simulation time 19181060 ps
CPU time 3.56 seconds
Started Jun 02 01:53:31 PM PDT 24
Finished Jun 02 01:53:35 PM PDT 24
Peak memory 239208 kb
Host smart-1981ae73-951f-45f3-bbca-c6d52699118d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53708
9873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.537089873
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.3689793928
Short name T365
Test name
Test status
Simulation time 2735164638 ps
CPU time 76.93 seconds
Started Jun 02 01:53:32 PM PDT 24
Finished Jun 02 01:54:49 PM PDT 24
Peak memory 256936 kb
Host smart-f43f8a85-54f6-4d8d-b2a7-dc0ee1a99502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36897
93928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3689793928
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.1228242980
Short name T557
Test name
Test status
Simulation time 71599954013 ps
CPU time 1475.51 seconds
Started Jun 02 01:53:35 PM PDT 24
Finished Jun 02 02:18:11 PM PDT 24
Peak memory 289332 kb
Host smart-d5990765-ab37-4173-940f-f4d362707ca9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228242980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.1228242980
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.1201903269
Short name T484
Test name
Test status
Simulation time 31844979167 ps
CPU time 800.65 seconds
Started Jun 02 01:53:39 PM PDT 24
Finished Jun 02 02:07:00 PM PDT 24
Peak memory 272392 kb
Host smart-cc5c0e1d-91e8-410d-9cba-9c8d0b750931
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201903269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.1201903269
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.2496110670
Short name T389
Test name
Test status
Simulation time 653092521 ps
CPU time 10.15 seconds
Started Jun 02 01:53:39 PM PDT 24
Finished Jun 02 01:53:50 PM PDT 24
Peak memory 248744 kb
Host smart-998fe04e-186f-402c-825d-9768ad9003c2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2496110670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.2496110670
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2546677854
Short name T650
Test name
Test status
Simulation time 1941492036 ps
CPU time 101.28 seconds
Started Jun 02 01:53:32 PM PDT 24
Finished Jun 02 01:55:14 PM PDT 24
Peak memory 256868 kb
Host smart-70df5c00-81a9-4e77-8add-3bdf32231a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25466
77854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2546677854
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.4260104966
Short name T663
Test name
Test status
Simulation time 1556223322 ps
CPU time 45.64 seconds
Started Jun 02 01:53:35 PM PDT 24
Finished Jun 02 01:54:21 PM PDT 24
Peak memory 248696 kb
Host smart-03970b57-55f4-40e4-8faf-ee93e67d0a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42601
04966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.4260104966
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.3690353204
Short name T305
Test name
Test status
Simulation time 132582671746 ps
CPU time 2123.52 seconds
Started Jun 02 01:53:40 PM PDT 24
Finished Jun 02 02:29:05 PM PDT 24
Peak memory 283136 kb
Host smart-c3d7c5da-ffa2-4bde-9f81-377b32cb3d65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690353204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3690353204
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.1600588160
Short name T670
Test name
Test status
Simulation time 106235435085 ps
CPU time 1764.57 seconds
Started Jun 02 01:53:48 PM PDT 24
Finished Jun 02 02:23:13 PM PDT 24
Peak memory 270296 kb
Host smart-deba1444-78b9-48ba-98fd-84c6827b438f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600588160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1600588160
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.2186413266
Short name T289
Test name
Test status
Simulation time 15513278840 ps
CPU time 153.1 seconds
Started Jun 02 01:53:41 PM PDT 24
Finished Jun 02 01:56:14 PM PDT 24
Peak memory 248140 kb
Host smart-29b22385-c84a-4319-9962-69ffba387da9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186413266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.2186413266
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1532244293
Short name T525
Test name
Test status
Simulation time 4096493923 ps
CPU time 68.15 seconds
Started Jun 02 01:53:34 PM PDT 24
Finished Jun 02 01:54:43 PM PDT 24
Peak memory 248808 kb
Host smart-48b1780c-5955-406b-9219-05ddf0fca661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15322
44293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1532244293
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2865032418
Short name T118
Test name
Test status
Simulation time 973118068 ps
CPU time 53.92 seconds
Started Jun 02 01:53:34 PM PDT 24
Finished Jun 02 01:54:28 PM PDT 24
Peak memory 248680 kb
Host smart-6951958d-7465-4506-9041-1c3fe4c84313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28650
32418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2865032418
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.2408873322
Short name T640
Test name
Test status
Simulation time 2768574604 ps
CPU time 49.23 seconds
Started Jun 02 01:53:35 PM PDT 24
Finished Jun 02 01:54:24 PM PDT 24
Peak memory 248728 kb
Host smart-7a15dce7-b0f1-41bb-a79d-b2214f615b84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24088
73322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2408873322
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.3322105692
Short name T403
Test name
Test status
Simulation time 93993359347 ps
CPU time 2842.12 seconds
Started Jun 02 01:53:39 PM PDT 24
Finished Jun 02 02:41:01 PM PDT 24
Peak memory 289124 kb
Host smart-e14c1676-d348-481c-aade-2ff68e651f6c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322105692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.3322105692
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.496134693
Short name T409
Test name
Test status
Simulation time 31193175282 ps
CPU time 973.26 seconds
Started Jun 02 01:53:40 PM PDT 24
Finished Jun 02 02:09:54 PM PDT 24
Peak memory 270972 kb
Host smart-dde17d9b-263a-4532-989c-2af4edeac721
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496134693 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.496134693
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.339819698
Short name T203
Test name
Test status
Simulation time 203804229 ps
CPU time 5.06 seconds
Started Jun 02 01:53:53 PM PDT 24
Finished Jun 02 01:53:59 PM PDT 24
Peak memory 248884 kb
Host smart-004ea562-d36b-4050-9130-2f5401a73975
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=339819698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.339819698
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.3003032452
Short name T613
Test name
Test status
Simulation time 34035351437 ps
CPU time 1310.92 seconds
Started Jun 02 01:53:44 PM PDT 24
Finished Jun 02 02:15:36 PM PDT 24
Peak memory 289156 kb
Host smart-77772c35-da5d-4230-868b-e7f389317e21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003032452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3003032452
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.2166967077
Short name T697
Test name
Test status
Simulation time 2018748541 ps
CPU time 14 seconds
Started Jun 02 01:53:50 PM PDT 24
Finished Jun 02 01:54:04 PM PDT 24
Peak memory 248724 kb
Host smart-098ed810-e5ef-4d46-b826-1204a8c78a78
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2166967077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2166967077
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1139013589
Short name T447
Test name
Test status
Simulation time 395204556 ps
CPU time 20.57 seconds
Started Jun 02 01:53:46 PM PDT 24
Finished Jun 02 01:54:07 PM PDT 24
Peak memory 256360 kb
Host smart-772e5133-1e79-401e-a201-7e3e72f739a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11390
13589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1139013589
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.491206276
Short name T85
Test name
Test status
Simulation time 65399819 ps
CPU time 6.97 seconds
Started Jun 02 01:53:47 PM PDT 24
Finished Jun 02 01:53:54 PM PDT 24
Peak memory 252904 kb
Host smart-45c8a1e1-8a87-4a69-8de7-6225a2c34a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49120
6276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.491206276
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.209316197
Short name T581
Test name
Test status
Simulation time 39260786120 ps
CPU time 812.59 seconds
Started Jun 02 01:53:48 PM PDT 24
Finished Jun 02 02:07:21 PM PDT 24
Peak memory 272600 kb
Host smart-a2d0047f-9287-4b4b-b2ae-cb37fecb3d6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209316197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.209316197
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2425059881
Short name T292
Test name
Test status
Simulation time 7645148225 ps
CPU time 54.91 seconds
Started Jun 02 01:53:46 PM PDT 24
Finished Jun 02 01:54:41 PM PDT 24
Peak memory 254004 kb
Host smart-2a62d320-abda-4479-9525-7b5e58a1f52d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425059881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2425059881
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.3572069354
Short name T546
Test name
Test status
Simulation time 501562553 ps
CPU time 28.82 seconds
Started Jun 02 01:53:40 PM PDT 24
Finished Jun 02 01:54:09 PM PDT 24
Peak memory 248728 kb
Host smart-22746f22-72b2-4daf-aaed-70cc872ec421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35720
69354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3572069354
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.3150530864
Short name T81
Test name
Test status
Simulation time 194303584 ps
CPU time 5.03 seconds
Started Jun 02 01:53:47 PM PDT 24
Finished Jun 02 01:53:52 PM PDT 24
Peak memory 250996 kb
Host smart-2dac9886-2b6d-4050-b441-4b46fadd41f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31505
30864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3150530864
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.1587136096
Short name T692
Test name
Test status
Simulation time 3148274039 ps
CPU time 48.71 seconds
Started Jun 02 01:53:46 PM PDT 24
Finished Jun 02 01:54:35 PM PDT 24
Peak memory 248740 kb
Host smart-431e3766-eb32-4681-9c34-06aae1ed44e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15871
36096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.1587136096
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.339049857
Short name T629
Test name
Test status
Simulation time 245342407555 ps
CPU time 3684.28 seconds
Started Jun 02 01:53:49 PM PDT 24
Finished Jun 02 02:55:14 PM PDT 24
Peak memory 305412 kb
Host smart-027f75b2-8532-4949-a626-161baf7d5889
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339049857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.339049857
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.3133549787
Short name T204
Test name
Test status
Simulation time 21638822 ps
CPU time 2.3 seconds
Started Jun 02 01:53:57 PM PDT 24
Finished Jun 02 01:54:00 PM PDT 24
Peak memory 248772 kb
Host smart-34e1357b-dd18-4d3f-9eed-582c45d6ceda
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3133549787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.3133549787
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.1203730099
Short name T666
Test name
Test status
Simulation time 13959378960 ps
CPU time 1177.27 seconds
Started Jun 02 01:53:57 PM PDT 24
Finished Jun 02 02:13:35 PM PDT 24
Peak memory 282516 kb
Host smart-66759176-4e78-4568-8bfb-b92fe0fd88d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203730099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1203730099
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3637540612
Short name T582
Test name
Test status
Simulation time 1397304855 ps
CPU time 57.96 seconds
Started Jun 02 01:53:57 PM PDT 24
Finished Jun 02 01:54:55 PM PDT 24
Peak memory 248724 kb
Host smart-c5937899-bddb-46e5-85cd-372d01a4ea9a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3637540612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3637540612
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.3359867348
Short name T375
Test name
Test status
Simulation time 7632328928 ps
CPU time 192.89 seconds
Started Jun 02 01:53:50 PM PDT 24
Finished Jun 02 01:57:04 PM PDT 24
Peak memory 256952 kb
Host smart-c07597f6-5a07-4664-93a5-8f87fc2214b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33598
67348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.3359867348
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3739014193
Short name T83
Test name
Test status
Simulation time 389745760 ps
CPU time 26.36 seconds
Started Jun 02 01:53:50 PM PDT 24
Finished Jun 02 01:54:16 PM PDT 24
Peak memory 248740 kb
Host smart-c2e03a9f-73ab-4184-9aed-b1eb7f02eab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37390
14193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3739014193
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.560605362
Short name T319
Test name
Test status
Simulation time 163057454658 ps
CPU time 2204.92 seconds
Started Jun 02 01:53:57 PM PDT 24
Finished Jun 02 02:30:42 PM PDT 24
Peak memory 271476 kb
Host smart-d2395eec-00a6-421d-abc6-84df21262730
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560605362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.560605362
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.2283781893
Short name T125
Test name
Test status
Simulation time 86945415411 ps
CPU time 1597.82 seconds
Started Jun 02 01:53:55 PM PDT 24
Finished Jun 02 02:20:33 PM PDT 24
Peak memory 271600 kb
Host smart-8c17db4f-7fa4-40a8-9b41-da5ce659f4c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283781893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.2283781893
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2878861348
Short name T619
Test name
Test status
Simulation time 6318730587 ps
CPU time 267.31 seconds
Started Jun 02 01:53:56 PM PDT 24
Finished Jun 02 01:58:23 PM PDT 24
Peak memory 248220 kb
Host smart-bcf6808d-94ce-4ec7-9e72-cc58ed18a720
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878861348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2878861348
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2457919119
Short name T657
Test name
Test status
Simulation time 186212011 ps
CPU time 4.92 seconds
Started Jun 02 01:53:55 PM PDT 24
Finished Jun 02 01:54:01 PM PDT 24
Peak memory 240648 kb
Host smart-aafc295e-8fb4-44b2-950a-c59e69bcbed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24579
19119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2457919119
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.713095910
Short name T111
Test name
Test status
Simulation time 1084893567 ps
CPU time 73.02 seconds
Started Jun 02 01:53:53 PM PDT 24
Finished Jun 02 01:55:06 PM PDT 24
Peak memory 255580 kb
Host smart-6bc40de4-3de5-451c-8326-35d15f9154fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71309
5910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.713095910
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2278429914
Short name T120
Test name
Test status
Simulation time 1183420579 ps
CPU time 23.76 seconds
Started Jun 02 01:53:55 PM PDT 24
Finished Jun 02 01:54:19 PM PDT 24
Peak memory 248844 kb
Host smart-6ad8c6a7-e77a-46e4-9783-52a9d46d6fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22784
29914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2278429914
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.1012096621
Short name T479
Test name
Test status
Simulation time 222029172 ps
CPU time 18.64 seconds
Started Jun 02 01:53:49 PM PDT 24
Finished Jun 02 01:54:08 PM PDT 24
Peak memory 256852 kb
Host smart-a0574370-7e5f-4b63-aae5-12a4f2090111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10120
96621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1012096621
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.3765641843
Short name T202
Test name
Test status
Simulation time 52038938 ps
CPU time 2.72 seconds
Started Jun 02 01:52:56 PM PDT 24
Finished Jun 02 01:52:59 PM PDT 24
Peak memory 248884 kb
Host smart-7fc9f5a5-02d8-4334-b040-40d4738959e8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3765641843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3765641843
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.3030228454
Short name T58
Test name
Test status
Simulation time 190457653727 ps
CPU time 1482.24 seconds
Started Jun 02 01:52:58 PM PDT 24
Finished Jun 02 02:17:40 PM PDT 24
Peak memory 289296 kb
Host smart-6f34f989-e536-426e-bc8e-c1594f4b2096
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030228454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.3030228454
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.561467511
Short name T434
Test name
Test status
Simulation time 789592887 ps
CPU time 36.3 seconds
Started Jun 02 01:52:59 PM PDT 24
Finished Jun 02 01:53:35 PM PDT 24
Peak memory 248748 kb
Host smart-d8312f3b-9167-4138-9d65-9f28ccccd757
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=561467511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.561467511
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.695412884
Short name T492
Test name
Test status
Simulation time 5888063405 ps
CPU time 111.42 seconds
Started Jun 02 01:52:56 PM PDT 24
Finished Jun 02 01:54:47 PM PDT 24
Peak memory 256916 kb
Host smart-66551ef8-4fe9-4dc6-b017-be0fccaa57ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69541
2884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.695412884
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.598026212
Short name T477
Test name
Test status
Simulation time 1310953773 ps
CPU time 22.36 seconds
Started Jun 02 01:52:54 PM PDT 24
Finished Jun 02 01:53:17 PM PDT 24
Peak memory 254868 kb
Host smart-53e9b4ae-0c5e-4e48-a8f1-0c22e066ff1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59802
6212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.598026212
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.918640998
Short name T7
Test name
Test status
Simulation time 48374889534 ps
CPU time 1156.36 seconds
Started Jun 02 01:52:55 PM PDT 24
Finished Jun 02 02:12:12 PM PDT 24
Peak memory 281568 kb
Host smart-989d303b-766a-45d4-82c8-38cfe0019c58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918640998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.918640998
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2972383484
Short name T488
Test name
Test status
Simulation time 25477458631 ps
CPU time 677.1 seconds
Started Jun 02 01:53:00 PM PDT 24
Finished Jun 02 02:04:18 PM PDT 24
Peak memory 273212 kb
Host smart-8b88307c-6fcc-4cac-bde3-aab52363f1ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972383484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2972383484
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2393194133
Short name T311
Test name
Test status
Simulation time 9348354901 ps
CPU time 101.97 seconds
Started Jun 02 01:52:56 PM PDT 24
Finished Jun 02 01:54:39 PM PDT 24
Peak memory 248292 kb
Host smart-554362ef-4732-46c2-a802-41b5626924d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393194133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2393194133
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.4056545473
Short name T681
Test name
Test status
Simulation time 1510087442 ps
CPU time 21.22 seconds
Started Jun 02 01:52:53 PM PDT 24
Finished Jun 02 01:53:15 PM PDT 24
Peak memory 248732 kb
Host smart-5bb6fe17-81ba-4c12-9595-e98d0d53687a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40565
45473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.4056545473
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.869196060
Short name T500
Test name
Test status
Simulation time 1358206954 ps
CPU time 23.83 seconds
Started Jun 02 01:52:54 PM PDT 24
Finished Jun 02 01:53:19 PM PDT 24
Peak memory 248972 kb
Host smart-58550ec8-67fa-4a91-b53e-c56bab4ac1a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86919
6060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.869196060
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.4175166371
Short name T38
Test name
Test status
Simulation time 1398091844 ps
CPU time 21.06 seconds
Started Jun 02 01:52:56 PM PDT 24
Finished Jun 02 01:53:18 PM PDT 24
Peak memory 277596 kb
Host smart-5934571f-5d6d-43c1-95f2-eabcdd000b0d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4175166371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.4175166371
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.2259638814
Short name T694
Test name
Test status
Simulation time 5560223079 ps
CPU time 20.83 seconds
Started Jun 02 01:52:54 PM PDT 24
Finished Jun 02 01:53:15 PM PDT 24
Peak memory 247340 kb
Host smart-0c2724c7-79a1-431c-915f-1ebc0759f379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22596
38814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2259638814
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.247403862
Short name T700
Test name
Test status
Simulation time 223513656 ps
CPU time 7.46 seconds
Started Jun 02 01:52:56 PM PDT 24
Finished Jun 02 01:53:04 PM PDT 24
Peak memory 252904 kb
Host smart-7c576257-e69c-4feb-b9cf-5cf93e5c4800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24740
3862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.247403862
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2096747622
Short name T256
Test name
Test status
Simulation time 51072245820 ps
CPU time 2631.45 seconds
Started Jun 02 01:53:03 PM PDT 24
Finished Jun 02 02:36:55 PM PDT 24
Peak memory 288880 kb
Host smart-c50af982-bedd-4db7-98cb-5472185924d7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096747622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2096747622
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.55923743
Short name T440
Test name
Test status
Simulation time 24048179605 ps
CPU time 964.87 seconds
Started Jun 02 01:53:54 PM PDT 24
Finished Jun 02 02:09:59 PM PDT 24
Peak memory 271648 kb
Host smart-9609674d-1fb6-405a-9d73-db2152f8e927
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55923743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.55923743
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1668962170
Short name T638
Test name
Test status
Simulation time 534689781 ps
CPU time 23.52 seconds
Started Jun 02 01:53:57 PM PDT 24
Finished Jun 02 01:54:21 PM PDT 24
Peak memory 256420 kb
Host smart-7a4ea65d-ee9a-4da7-a9a9-a42adddb2dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16689
62170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1668962170
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.188081464
Short name T372
Test name
Test status
Simulation time 1037209225 ps
CPU time 61.56 seconds
Started Jun 02 01:53:58 PM PDT 24
Finished Jun 02 01:55:00 PM PDT 24
Peak memory 255952 kb
Host smart-e0806731-b5ee-4b30-82e2-2061ce07ea68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18808
1464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.188081464
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.1670126582
Short name T486
Test name
Test status
Simulation time 21509702826 ps
CPU time 1426.38 seconds
Started Jun 02 01:53:57 PM PDT 24
Finished Jun 02 02:17:44 PM PDT 24
Peak memory 268188 kb
Host smart-cd195c23-2bcf-4c47-b54a-cae7739e16b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670126582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.1670126582
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.3303167721
Short name T533
Test name
Test status
Simulation time 30666843207 ps
CPU time 337.88 seconds
Started Jun 02 01:53:55 PM PDT 24
Finished Jun 02 01:59:33 PM PDT 24
Peak memory 247064 kb
Host smart-1112487b-0c56-4a6e-9f74-228915516fbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303167721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3303167721
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1574934530
Short name T48
Test name
Test status
Simulation time 171184704 ps
CPU time 6.36 seconds
Started Jun 02 01:53:55 PM PDT 24
Finished Jun 02 01:54:02 PM PDT 24
Peak memory 240524 kb
Host smart-1de2e3f9-f36f-457e-82d0-cfba55924ab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15749
34530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1574934530
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1168533619
Short name T425
Test name
Test status
Simulation time 49188191 ps
CPU time 2.84 seconds
Started Jun 02 01:53:54 PM PDT 24
Finished Jun 02 01:53:58 PM PDT 24
Peak memory 240528 kb
Host smart-d00400e2-bd00-46ec-b623-625c7053eb8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11685
33619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1168533619
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.63661232
Short name T194
Test name
Test status
Simulation time 81175873 ps
CPU time 4.44 seconds
Started Jun 02 01:53:55 PM PDT 24
Finished Jun 02 01:54:00 PM PDT 24
Peak memory 240528 kb
Host smart-7f466d6f-8437-41e5-9ee3-0ecbd49ee69b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63661
232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.63661232
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1037884288
Short name T705
Test name
Test status
Simulation time 106911429 ps
CPU time 11.88 seconds
Started Jun 02 01:53:53 PM PDT 24
Finished Jun 02 01:54:05 PM PDT 24
Peak memory 254680 kb
Host smart-7274a00a-dedd-4164-916d-e19a48470864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10378
84288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1037884288
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.2427117289
Short name T55
Test name
Test status
Simulation time 8095129555 ps
CPU time 466.05 seconds
Started Jun 02 01:53:56 PM PDT 24
Finished Jun 02 02:01:42 PM PDT 24
Peak memory 273180 kb
Host smart-94e3150b-d804-4b8d-ac43-53450d6a6e6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427117289 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.2427117289
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3137787312
Short name T464
Test name
Test status
Simulation time 119096783283 ps
CPU time 1919.12 seconds
Started Jun 02 01:54:03 PM PDT 24
Finished Jun 02 02:26:02 PM PDT 24
Peak memory 273412 kb
Host smart-391ff1ab-d696-4b3d-aa13-e5757d505a6f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137787312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3137787312
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.4016438937
Short name T232
Test name
Test status
Simulation time 1859146325 ps
CPU time 113.63 seconds
Started Jun 02 01:54:00 PM PDT 24
Finished Jun 02 01:55:54 PM PDT 24
Peak memory 248700 kb
Host smart-6441e798-d774-4cf3-a8ab-1d406ee5d5c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40164
38937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.4016438937
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3396756151
Short name T84
Test name
Test status
Simulation time 360127828 ps
CPU time 21.97 seconds
Started Jun 02 01:54:02 PM PDT 24
Finished Jun 02 01:54:24 PM PDT 24
Peak memory 256860 kb
Host smart-a9af2f62-c825-4627-9e8f-5f54bd72ad9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33967
56151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3396756151
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2111390608
Short name T660
Test name
Test status
Simulation time 59566934898 ps
CPU time 1294.16 seconds
Started Jun 02 01:54:00 PM PDT 24
Finished Jun 02 02:15:35 PM PDT 24
Peak memory 289268 kb
Host smart-d85ea40e-43b1-4a4c-9c68-834f106c0476
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111390608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2111390608
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.1454089482
Short name T554
Test name
Test status
Simulation time 154357821650 ps
CPU time 2217.28 seconds
Started Jun 02 01:54:00 PM PDT 24
Finished Jun 02 02:30:58 PM PDT 24
Peak memory 282520 kb
Host smart-9f35bd78-9284-41f8-a97c-d54716aaeb4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454089482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.1454089482
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3525386479
Short name T297
Test name
Test status
Simulation time 3569909534 ps
CPU time 143.91 seconds
Started Jun 02 01:54:03 PM PDT 24
Finished Jun 02 01:56:27 PM PDT 24
Peak memory 248464 kb
Host smart-68275bdd-b1e5-4589-a9ce-f5515404d54e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525386479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3525386479
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.3791766386
Short name T503
Test name
Test status
Simulation time 512999580 ps
CPU time 13.92 seconds
Started Jun 02 01:53:58 PM PDT 24
Finished Jun 02 01:54:12 PM PDT 24
Peak memory 248744 kb
Host smart-16e3791f-62c3-46d0-87a3-1716b51638dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37917
66386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3791766386
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3418623472
Short name T652
Test name
Test status
Simulation time 1174513297 ps
CPU time 41.86 seconds
Started Jun 02 01:54:02 PM PDT 24
Finished Jun 02 01:54:45 PM PDT 24
Peak memory 254860 kb
Host smart-684e96d3-a953-43aa-916b-74426de9beca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34186
23472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3418623472
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.3103614724
Short name T254
Test name
Test status
Simulation time 1538799490 ps
CPU time 18.73 seconds
Started Jun 02 01:54:01 PM PDT 24
Finished Jun 02 01:54:20 PM PDT 24
Peak memory 255536 kb
Host smart-439efc25-989f-4875-884c-5e7338afcfc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31036
14724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3103614724
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2402115630
Short name T36
Test name
Test status
Simulation time 6432369144 ps
CPU time 57.17 seconds
Started Jun 02 01:53:57 PM PDT 24
Finished Jun 02 01:54:54 PM PDT 24
Peak memory 248852 kb
Host smart-ae3b87d4-4520-40e7-81f8-eb0c964c2e48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24021
15630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2402115630
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3563450782
Short name T108
Test name
Test status
Simulation time 7575308362 ps
CPU time 756.11 seconds
Started Jun 02 01:54:08 PM PDT 24
Finished Jun 02 02:06:44 PM PDT 24
Peak memory 273388 kb
Host smart-03012d40-f42f-4a29-9a54-3ef3302538fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563450782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3563450782
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.1834156540
Short name T478
Test name
Test status
Simulation time 1774238897 ps
CPU time 99.12 seconds
Started Jun 02 01:54:08 PM PDT 24
Finished Jun 02 01:55:47 PM PDT 24
Peak memory 249092 kb
Host smart-1044a6d5-4998-41bc-b98a-164eb17b7bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18341
56540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1834156540
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.1448215239
Short name T606
Test name
Test status
Simulation time 564364100 ps
CPU time 16.9 seconds
Started Jun 02 01:54:02 PM PDT 24
Finished Jun 02 01:54:19 PM PDT 24
Peak memory 248976 kb
Host smart-a6b01865-8146-48da-9c24-4c68be31ff74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14482
15239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.1448215239
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1328713064
Short name T626
Test name
Test status
Simulation time 77489723373 ps
CPU time 2209.73 seconds
Started Jun 02 01:54:09 PM PDT 24
Finished Jun 02 02:30:59 PM PDT 24
Peak memory 273320 kb
Host smart-acacc9be-aa72-4bc1-805c-2b9523542fca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328713064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1328713064
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1045250884
Short name T79
Test name
Test status
Simulation time 47788469505 ps
CPU time 2438.59 seconds
Started Jun 02 01:54:05 PM PDT 24
Finished Jun 02 02:34:45 PM PDT 24
Peak memory 289180 kb
Host smart-079d6735-72e5-47ac-92df-eb875e70cef9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045250884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1045250884
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1551304810
Short name T288
Test name
Test status
Simulation time 10861047123 ps
CPU time 445.86 seconds
Started Jun 02 01:54:07 PM PDT 24
Finished Jun 02 02:01:33 PM PDT 24
Peak memory 248216 kb
Host smart-209fa786-a811-48af-ab16-fbfd9380a35d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551304810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1551304810
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.4026339256
Short name T422
Test name
Test status
Simulation time 596682444 ps
CPU time 38.15 seconds
Started Jun 02 01:54:01 PM PDT 24
Finished Jun 02 01:54:40 PM PDT 24
Peak memory 248784 kb
Host smart-cc322bfb-8ff9-460a-8e04-1400f208da58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40263
39256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.4026339256
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.831747579
Short name T127
Test name
Test status
Simulation time 449238654 ps
CPU time 33.76 seconds
Started Jun 02 01:54:03 PM PDT 24
Finished Jun 02 01:54:37 PM PDT 24
Peak memory 254756 kb
Host smart-655feea4-e3e8-4d42-892e-7f2d3332b8cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83174
7579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.831747579
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.3061179764
Short name T633
Test name
Test status
Simulation time 172314177 ps
CPU time 12.62 seconds
Started Jun 02 01:54:06 PM PDT 24
Finished Jun 02 01:54:19 PM PDT 24
Peak memory 253196 kb
Host smart-10003a4e-bf71-42ac-bd1b-1257f86a4bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30611
79764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3061179764
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.1108470737
Short name T659
Test name
Test status
Simulation time 584353293 ps
CPU time 40.74 seconds
Started Jun 02 01:54:02 PM PDT 24
Finished Jun 02 01:54:44 PM PDT 24
Peak memory 248968 kb
Host smart-c662e7a7-cc87-4f7e-b164-4a370ab1ef34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11084
70737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1108470737
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.4148111786
Short name T50
Test name
Test status
Simulation time 27950875346 ps
CPU time 227.24 seconds
Started Jun 02 01:54:05 PM PDT 24
Finished Jun 02 01:57:53 PM PDT 24
Peak memory 256908 kb
Host smart-1e0307ca-013c-4474-a317-5b6d107b1971
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148111786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.4148111786
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2454577401
Short name T476
Test name
Test status
Simulation time 38566359513 ps
CPU time 2214.26 seconds
Started Jun 02 01:54:11 PM PDT 24
Finished Jun 02 02:31:06 PM PDT 24
Peak memory 282968 kb
Host smart-af0a4e5a-58fb-4e46-85f7-9d58ba987356
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454577401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2454577401
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.2165185715
Short name T617
Test name
Test status
Simulation time 4663180667 ps
CPU time 153.02 seconds
Started Jun 02 01:54:14 PM PDT 24
Finished Jun 02 01:56:47 PM PDT 24
Peak memory 250224 kb
Host smart-07a74690-6e91-4f29-8e43-fe448c79839a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21651
85715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2165185715
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1445883002
Short name T552
Test name
Test status
Simulation time 1145370191 ps
CPU time 17.35 seconds
Started Jun 02 01:54:06 PM PDT 24
Finished Jun 02 01:54:24 PM PDT 24
Peak memory 248744 kb
Host smart-b479f4b4-5cf3-4d0a-aaa2-e6a4d8c53b59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14458
83002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1445883002
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3177214633
Short name T190
Test name
Test status
Simulation time 31493903951 ps
CPU time 1333.47 seconds
Started Jun 02 01:54:14 PM PDT 24
Finished Jun 02 02:16:28 PM PDT 24
Peak memory 281924 kb
Host smart-45b1ea55-1e4a-462a-bc07-155cf003d68d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177214633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3177214633
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.3855078889
Short name T512
Test name
Test status
Simulation time 128382819517 ps
CPU time 1856.44 seconds
Started Jun 02 01:54:14 PM PDT 24
Finished Jun 02 02:25:11 PM PDT 24
Peak memory 286104 kb
Host smart-d25e2b50-06ac-4734-9b8f-041ba27e082f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855078889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3855078889
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3381255437
Short name T9
Test name
Test status
Simulation time 12370057750 ps
CPU time 258.85 seconds
Started Jun 02 01:54:11 PM PDT 24
Finished Jun 02 01:58:31 PM PDT 24
Peak memory 248128 kb
Host smart-2e3b1376-56d7-43ac-9597-ef74ac6bf146
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381255437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3381255437
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3033665254
Short name T603
Test name
Test status
Simulation time 320135845 ps
CPU time 31.12 seconds
Started Jun 02 01:54:06 PM PDT 24
Finished Jun 02 01:54:38 PM PDT 24
Peak memory 248752 kb
Host smart-64cc2b3f-479a-402a-9c5c-80a6f1b3c4eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30336
65254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3033665254
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3467302314
Short name T457
Test name
Test status
Simulation time 149469006 ps
CPU time 7.83 seconds
Started Jun 02 01:54:05 PM PDT 24
Finished Jun 02 01:54:13 PM PDT 24
Peak memory 248716 kb
Host smart-fb9362c3-72fc-4056-ba58-e173880d1ad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34673
02314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3467302314
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.848837714
Short name T453
Test name
Test status
Simulation time 2589091393 ps
CPU time 43.6 seconds
Started Jun 02 01:54:12 PM PDT 24
Finished Jun 02 01:54:56 PM PDT 24
Peak memory 247784 kb
Host smart-2a65b940-27b9-4400-954e-001d866451f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84883
7714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.848837714
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.1744634474
Short name T410
Test name
Test status
Simulation time 551367263 ps
CPU time 21.38 seconds
Started Jun 02 01:54:07 PM PDT 24
Finished Jun 02 01:54:29 PM PDT 24
Peak memory 248736 kb
Host smart-abf48b92-3c9c-453c-a437-f5f87b750e76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17446
34474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.1744634474
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.4048359949
Short name T102
Test name
Test status
Simulation time 143572589469 ps
CPU time 1928.61 seconds
Started Jun 02 01:54:09 PM PDT 24
Finished Jun 02 02:26:18 PM PDT 24
Peak memory 305632 kb
Host smart-b4e0c228-76e8-439c-ae57-9acb2fb115fe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048359949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.4048359949
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.3822476167
Short name T266
Test name
Test status
Simulation time 46441979916 ps
CPU time 2691.31 seconds
Started Jun 02 01:54:11 PM PDT 24
Finished Jun 02 02:39:03 PM PDT 24
Peak memory 288968 kb
Host smart-a3397321-59c0-4aa5-aced-df55a4d4d3d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822476167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3822476167
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.150645190
Short name T585
Test name
Test status
Simulation time 162499527 ps
CPU time 17.59 seconds
Started Jun 02 01:54:13 PM PDT 24
Finished Jun 02 01:54:31 PM PDT 24
Peak memory 256396 kb
Host smart-aebb0497-491e-4820-bb0b-316f12d96dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15064
5190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.150645190
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.3245828470
Short name T708
Test name
Test status
Simulation time 96041175 ps
CPU time 4.75 seconds
Started Jun 02 01:54:11 PM PDT 24
Finished Jun 02 01:54:16 PM PDT 24
Peak memory 248740 kb
Host smart-b8df7cf6-bd3b-4c26-9bd0-ed7adc121a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32458
28470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3245828470
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.3271923787
Short name T371
Test name
Test status
Simulation time 66065774064 ps
CPU time 1273.26 seconds
Started Jun 02 01:54:13 PM PDT 24
Finished Jun 02 02:15:27 PM PDT 24
Peak memory 285916 kb
Host smart-b6b3092f-98c6-40d3-898e-637872fed2f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271923787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3271923787
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.306695041
Short name T678
Test name
Test status
Simulation time 12031466997 ps
CPU time 300.11 seconds
Started Jun 02 01:54:12 PM PDT 24
Finished Jun 02 01:59:12 PM PDT 24
Peak memory 248308 kb
Host smart-d1556500-025c-41dd-af54-1ca9f99bbc31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306695041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.306695041
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1155258781
Short name T594
Test name
Test status
Simulation time 388857551 ps
CPU time 17.29 seconds
Started Jun 02 01:54:11 PM PDT 24
Finished Jun 02 01:54:29 PM PDT 24
Peak memory 248804 kb
Host smart-cb1f31cf-1bc6-47aa-9a44-612590ee83ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11552
58781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1155258781
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2506231919
Short name T90
Test name
Test status
Simulation time 377929886 ps
CPU time 9.02 seconds
Started Jun 02 01:54:15 PM PDT 24
Finished Jun 02 01:54:24 PM PDT 24
Peak memory 251896 kb
Host smart-455cda05-fd50-4192-b717-9c921e295b5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25062
31919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2506231919
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.3738389461
Short name T653
Test name
Test status
Simulation time 154974836 ps
CPU time 12.29 seconds
Started Jun 02 01:54:10 PM PDT 24
Finished Jun 02 01:54:23 PM PDT 24
Peak memory 247384 kb
Host smart-f61d67a5-caa5-491b-8cda-2019d6d6f132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37383
89461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3738389461
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.1227233588
Short name T438
Test name
Test status
Simulation time 3277791644 ps
CPU time 50.43 seconds
Started Jun 02 01:54:12 PM PDT 24
Finished Jun 02 01:55:03 PM PDT 24
Peak memory 248800 kb
Host smart-1f8fa1e1-9f5e-41af-a74f-04c7ce1e0497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12272
33588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.1227233588
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.2730329776
Short name T251
Test name
Test status
Simulation time 6448502753 ps
CPU time 630.14 seconds
Started Jun 02 01:54:13 PM PDT 24
Finished Jun 02 02:04:43 PM PDT 24
Peak memory 273348 kb
Host smart-d979b217-ee02-41c6-a8a4-cb80156e034b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730329776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.2730329776
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.3161150740
Short name T219
Test name
Test status
Simulation time 445553099972 ps
CPU time 7917.6 seconds
Started Jun 02 01:54:12 PM PDT 24
Finished Jun 02 04:06:11 PM PDT 24
Peak memory 333824 kb
Host smart-ba44e5c7-33d3-4412-a279-b1d1e4f8e8a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161150740 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.3161150740
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.465316831
Short name T579
Test name
Test status
Simulation time 60497031953 ps
CPU time 1819.6 seconds
Started Jun 02 01:54:18 PM PDT 24
Finished Jun 02 02:24:38 PM PDT 24
Peak memory 273408 kb
Host smart-49a8d2f1-a384-49bf-be5d-5dcd963d88a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465316831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.465316831
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.2620190801
Short name T373
Test name
Test status
Simulation time 46983753829 ps
CPU time 115.79 seconds
Started Jun 02 01:54:17 PM PDT 24
Finished Jun 02 01:56:14 PM PDT 24
Peak memory 249772 kb
Host smart-96f97021-311d-4da5-bf3a-542d3842ae42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26201
90801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.2620190801
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.1356297497
Short name T462
Test name
Test status
Simulation time 682891751 ps
CPU time 52.87 seconds
Started Jun 02 01:54:17 PM PDT 24
Finished Jun 02 01:55:10 PM PDT 24
Peak memory 256012 kb
Host smart-63ce1def-ff09-479b-ac91-7013256138cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13562
97497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1356297497
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3824752910
Short name T430
Test name
Test status
Simulation time 149656332824 ps
CPU time 1505.23 seconds
Started Jun 02 01:54:16 PM PDT 24
Finished Jun 02 02:19:22 PM PDT 24
Peak memory 289416 kb
Host smart-76a72ce0-c64f-4f69-b2a0-64cbc482540c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824752910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3824752910
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3079468586
Short name T287
Test name
Test status
Simulation time 13415881277 ps
CPU time 288.77 seconds
Started Jun 02 01:54:17 PM PDT 24
Finished Jun 02 01:59:06 PM PDT 24
Peak memory 248232 kb
Host smart-bc975e2e-01b5-4e56-8a63-2208dd11837a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079468586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3079468586
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1519873715
Short name T448
Test name
Test status
Simulation time 10366603810 ps
CPU time 64.59 seconds
Started Jun 02 01:54:16 PM PDT 24
Finished Jun 02 01:55:21 PM PDT 24
Peak memory 248788 kb
Host smart-903cb8ce-e490-4ff0-8e8d-8eadf913ed8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15198
73715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1519873715
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.1677999274
Short name T651
Test name
Test status
Simulation time 315288266 ps
CPU time 29.14 seconds
Started Jun 02 01:54:18 PM PDT 24
Finished Jun 02 01:54:48 PM PDT 24
Peak memory 255532 kb
Host smart-166b7f13-8eb2-4415-9238-7f23302d9790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16779
99274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1677999274
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.3755346354
Short name T398
Test name
Test status
Simulation time 547390504 ps
CPU time 45.81 seconds
Started Jun 02 01:54:19 PM PDT 24
Finished Jun 02 01:55:05 PM PDT 24
Peak memory 247760 kb
Host smart-972fa55c-869e-4014-af63-de8b3232e557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37553
46354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3755346354
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2267976222
Short name T406
Test name
Test status
Simulation time 471840250 ps
CPU time 26.7 seconds
Started Jun 02 01:54:19 PM PDT 24
Finished Jun 02 01:54:46 PM PDT 24
Peak memory 248728 kb
Host smart-b67032cb-d660-4ecf-8448-182d11724cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22679
76222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2267976222
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.3347195786
Short name T514
Test name
Test status
Simulation time 53901939509 ps
CPU time 1443.3 seconds
Started Jun 02 01:54:19 PM PDT 24
Finished Jun 02 02:18:23 PM PDT 24
Peak memory 289760 kb
Host smart-6989da6c-23b2-4315-9888-d9c09ef99870
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347195786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.3347195786
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.684670936
Short name T699
Test name
Test status
Simulation time 79910452072 ps
CPU time 2994.64 seconds
Started Jun 02 01:54:18 PM PDT 24
Finished Jun 02 02:44:13 PM PDT 24
Peak memory 305684 kb
Host smart-6de5af51-e876-4fde-a8f4-1f8800c2dab5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684670936 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.684670936
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.1665990532
Short name T82
Test name
Test status
Simulation time 10380609284 ps
CPU time 728.83 seconds
Started Jun 02 01:54:21 PM PDT 24
Finished Jun 02 02:06:30 PM PDT 24
Peak memory 270824 kb
Host smart-959ad754-2af4-4916-ac4e-44ca8f03b49c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665990532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1665990532
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.1856536437
Short name T505
Test name
Test status
Simulation time 20289642590 ps
CPU time 319.75 seconds
Started Jun 02 01:54:17 PM PDT 24
Finished Jun 02 01:59:37 PM PDT 24
Peak memory 257120 kb
Host smart-6382dca4-ebf3-4738-910e-e593170a0588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18565
36437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.1856536437
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.2036582581
Short name T693
Test name
Test status
Simulation time 557712377 ps
CPU time 9.53 seconds
Started Jun 02 01:54:19 PM PDT 24
Finished Jun 02 01:54:29 PM PDT 24
Peak memory 254116 kb
Host smart-5f07c4c2-cdac-4b9b-9361-2a79c22d063c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20365
82581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.2036582581
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.3886964697
Short name T323
Test name
Test status
Simulation time 76111506447 ps
CPU time 1872.62 seconds
Started Jun 02 01:54:22 PM PDT 24
Finished Jun 02 02:25:36 PM PDT 24
Peak memory 267232 kb
Host smart-135a74b7-8c74-47d7-8420-5666808f671f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886964697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3886964697
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.3801159714
Short name T550
Test name
Test status
Simulation time 75847745456 ps
CPU time 1471.03 seconds
Started Jun 02 01:54:22 PM PDT 24
Finished Jun 02 02:18:54 PM PDT 24
Peak memory 289048 kb
Host smart-1ebc539d-c65f-44f7-ac05-b2ea7c2c26cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801159714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3801159714
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.3580703857
Short name T290
Test name
Test status
Simulation time 57108038298 ps
CPU time 397.18 seconds
Started Jun 02 01:54:23 PM PDT 24
Finished Jun 02 02:01:00 PM PDT 24
Peak memory 254756 kb
Host smart-4cc2a6ca-afde-49e9-96e5-0d6752f937e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580703857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3580703857
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.3339722538
Short name T547
Test name
Test status
Simulation time 708817230 ps
CPU time 52.7 seconds
Started Jun 02 01:54:18 PM PDT 24
Finished Jun 02 01:55:11 PM PDT 24
Peak memory 248700 kb
Host smart-9f589575-6fd0-47e6-8575-de549757cbd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33397
22538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.3339722538
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2834268042
Short name T63
Test name
Test status
Simulation time 6274732069 ps
CPU time 44.96 seconds
Started Jun 02 01:54:17 PM PDT 24
Finished Jun 02 01:55:02 PM PDT 24
Peak memory 255108 kb
Host smart-c92e2c88-09ef-45bf-af5b-800628afd779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28342
68042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2834268042
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.845051470
Short name T23
Test name
Test status
Simulation time 1071929842 ps
CPU time 34.19 seconds
Started Jun 02 01:54:21 PM PDT 24
Finished Jun 02 01:54:56 PM PDT 24
Peak memory 255184 kb
Host smart-f8c7d0bc-3c0a-4d71-a641-75567e2389b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84505
1470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.845051470
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.278601317
Short name T676
Test name
Test status
Simulation time 228737145 ps
CPU time 15.85 seconds
Started Jun 02 01:54:18 PM PDT 24
Finished Jun 02 01:54:34 PM PDT 24
Peak memory 248704 kb
Host smart-c2d37703-7e3f-41c5-9c8b-92d0ab636aa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27860
1317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.278601317
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.1389309374
Short name T26
Test name
Test status
Simulation time 97276714679 ps
CPU time 2289.68 seconds
Started Jun 02 01:54:23 PM PDT 24
Finished Jun 02 02:32:33 PM PDT 24
Peak memory 289164 kb
Host smart-a33cfe6f-8023-458e-8f78-31a363f14c9f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389309374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.1389309374
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.1115761445
Short name T258
Test name
Test status
Simulation time 23460740381 ps
CPU time 2730.21 seconds
Started Jun 02 01:54:22 PM PDT 24
Finished Jun 02 02:39:53 PM PDT 24
Peak memory 314464 kb
Host smart-49783607-fda8-435e-a95c-fd6362589894
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115761445 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.1115761445
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3464063881
Short name T522
Test name
Test status
Simulation time 27482523922 ps
CPU time 1897.45 seconds
Started Jun 02 01:54:23 PM PDT 24
Finished Jun 02 02:26:01 PM PDT 24
Peak memory 285992 kb
Host smart-0dd8b3f0-6d65-4265-8b58-434a37f94bdb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464063881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3464063881
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3661620367
Short name T578
Test name
Test status
Simulation time 1875234179 ps
CPU time 77.54 seconds
Started Jun 02 01:54:22 PM PDT 24
Finished Jun 02 01:55:40 PM PDT 24
Peak memory 256856 kb
Host smart-026ce803-2374-4bee-8a1d-928fb7e5400a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36616
20367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3661620367
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.3798792543
Short name T411
Test name
Test status
Simulation time 175580988 ps
CPU time 8.05 seconds
Started Jun 02 01:54:23 PM PDT 24
Finished Jun 02 01:54:31 PM PDT 24
Peak memory 251728 kb
Host smart-ec609766-06f9-4272-809a-03f1f7104f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37987
92543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.3798792543
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.1307598945
Short name T310
Test name
Test status
Simulation time 42189958562 ps
CPU time 2607.77 seconds
Started Jun 02 01:54:27 PM PDT 24
Finished Jun 02 02:37:56 PM PDT 24
Peak memory 288428 kb
Host smart-442ae34a-cc5d-4e34-b476-bb004cc2d3fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307598945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.1307598945
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.2941133832
Short name T413
Test name
Test status
Simulation time 50285600062 ps
CPU time 1528.43 seconds
Started Jun 02 01:54:27 PM PDT 24
Finished Jun 02 02:19:57 PM PDT 24
Peak memory 273264 kb
Host smart-a467f409-c1ae-493e-bbe9-550895db837a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941133832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.2941133832
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.781530344
Short name T643
Test name
Test status
Simulation time 23280789060 ps
CPU time 249.85 seconds
Started Jun 02 01:54:24 PM PDT 24
Finished Jun 02 01:58:34 PM PDT 24
Peak memory 248780 kb
Host smart-326e964e-32e0-4b40-ba28-ef959854cecb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781530344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.781530344
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.2137582370
Short name T689
Test name
Test status
Simulation time 2058321644 ps
CPU time 32.64 seconds
Started Jun 02 01:54:22 PM PDT 24
Finished Jun 02 01:54:55 PM PDT 24
Peak memory 248688 kb
Host smart-ed15e607-412e-408a-ac3e-3f20425e2557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21375
82370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2137582370
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2677850391
Short name T271
Test name
Test status
Simulation time 6668191756 ps
CPU time 20.31 seconds
Started Jun 02 01:54:22 PM PDT 24
Finished Jun 02 01:54:42 PM PDT 24
Peak memory 248720 kb
Host smart-6f96d637-25e0-4192-b739-94d821144df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26778
50391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2677850391
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3661059378
Short name T315
Test name
Test status
Simulation time 209389846 ps
CPU time 13.6 seconds
Started Jun 02 01:54:23 PM PDT 24
Finished Jun 02 01:54:37 PM PDT 24
Peak memory 252848 kb
Host smart-92ccdd3e-6a8f-4809-b1f5-f0711af05994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36610
59378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3661059378
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3490112109
Short name T445
Test name
Test status
Simulation time 1884017983 ps
CPU time 50.93 seconds
Started Jun 02 01:54:22 PM PDT 24
Finished Jun 02 01:55:13 PM PDT 24
Peak memory 248740 kb
Host smart-b5e545b3-ded6-4688-a5a2-04b2c77df8e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34901
12109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3490112109
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.2652552682
Short name T112
Test name
Test status
Simulation time 30705719749 ps
CPU time 1838.74 seconds
Started Jun 02 01:54:28 PM PDT 24
Finished Jun 02 02:25:08 PM PDT 24
Peak memory 286176 kb
Host smart-b30d911c-4ffc-4364-91d0-13b09c716bef
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652552682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.2652552682
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.389433841
Short name T703
Test name
Test status
Simulation time 112529227334 ps
CPU time 1483.52 seconds
Started Jun 02 01:54:27 PM PDT 24
Finished Jun 02 02:19:12 PM PDT 24
Peak memory 273076 kb
Host smart-be239500-33ee-4cd1-9ca1-a10604a6721b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389433841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.389433841
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2011774264
Short name T382
Test name
Test status
Simulation time 1719248807 ps
CPU time 62.35 seconds
Started Jun 02 01:54:28 PM PDT 24
Finished Jun 02 01:55:31 PM PDT 24
Peak memory 248932 kb
Host smart-a403566f-598a-4d1a-b9d0-01e98f195a84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20117
74264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2011774264
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.188243554
Short name T539
Test name
Test status
Simulation time 800357977 ps
CPU time 41.64 seconds
Started Jun 02 01:54:28 PM PDT 24
Finished Jun 02 01:55:10 PM PDT 24
Peak memory 255992 kb
Host smart-32ce0de9-7c62-4e9d-b240-ae7bf0e2d05f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18824
3554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.188243554
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.759908843
Short name T327
Test name
Test status
Simulation time 16462278132 ps
CPU time 1228.99 seconds
Started Jun 02 01:54:26 PM PDT 24
Finished Jun 02 02:14:56 PM PDT 24
Peak memory 272344 kb
Host smart-9f178a71-e576-474c-b174-429c6fa4c2d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759908843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.759908843
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.1642656131
Short name T106
Test name
Test status
Simulation time 34650652558 ps
CPU time 749.74 seconds
Started Jun 02 01:54:28 PM PDT 24
Finished Jun 02 02:06:58 PM PDT 24
Peak memory 272844 kb
Host smart-dd4764ef-c9e3-4ed3-9fc7-04668148a98f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642656131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1642656131
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2727875295
Short name T295
Test name
Test status
Simulation time 13224696539 ps
CPU time 513.21 seconds
Started Jun 02 01:54:28 PM PDT 24
Finished Jun 02 02:03:02 PM PDT 24
Peak memory 248244 kb
Host smart-7f73893f-27b7-452b-8d5d-4560b90add1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727875295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2727875295
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.14261899
Short name T527
Test name
Test status
Simulation time 26499830 ps
CPU time 5.44 seconds
Started Jun 02 01:54:27 PM PDT 24
Finished Jun 02 01:54:33 PM PDT 24
Peak memory 240648 kb
Host smart-933b93a8-bc46-40c7-8483-b62b34888307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14261
899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.14261899
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.1130387130
Short name T630
Test name
Test status
Simulation time 60972635 ps
CPU time 7.47 seconds
Started Jun 02 01:54:27 PM PDT 24
Finished Jun 02 01:54:36 PM PDT 24
Peak memory 247412 kb
Host smart-6e83502d-dfb9-436b-8b84-f40196b43f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11303
87130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1130387130
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.2013573746
Short name T252
Test name
Test status
Simulation time 80232695 ps
CPU time 9.34 seconds
Started Jun 02 01:54:28 PM PDT 24
Finished Jun 02 01:54:38 PM PDT 24
Peak memory 247420 kb
Host smart-dd19e759-a413-4aa9-9c19-61953e696960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20135
73746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2013573746
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1397654050
Short name T707
Test name
Test status
Simulation time 293617161 ps
CPU time 7.59 seconds
Started Jun 02 01:54:28 PM PDT 24
Finished Jun 02 01:54:36 PM PDT 24
Peak memory 248740 kb
Host smart-7389c1c3-edc9-41a7-87bb-8defd54e439d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13976
54050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1397654050
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.13271239
Short name T683
Test name
Test status
Simulation time 20112579748 ps
CPU time 1615.62 seconds
Started Jun 02 01:54:28 PM PDT 24
Finished Jun 02 02:21:24 PM PDT 24
Peak memory 289532 kb
Host smart-e49342b3-6d18-45f3-ac60-f53d87ac3788
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13271239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_hand
ler_stress_all.13271239
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3733438660
Short name T267
Test name
Test status
Simulation time 53302551254 ps
CPU time 1404.52 seconds
Started Jun 02 01:54:33 PM PDT 24
Finished Jun 02 02:17:58 PM PDT 24
Peak memory 289476 kb
Host smart-c4fee110-7324-436e-96e1-e0bf0b947ab4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733438660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3733438660
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.2740908250
Short name T574
Test name
Test status
Simulation time 1549157265 ps
CPU time 154.88 seconds
Started Jun 02 01:54:34 PM PDT 24
Finished Jun 02 01:57:09 PM PDT 24
Peak memory 250828 kb
Host smart-1fd3b9ae-d48f-458c-a596-d6d99fbd09af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27409
08250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2740908250
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.677778579
Short name T87
Test name
Test status
Simulation time 748030841 ps
CPU time 25.67 seconds
Started Jun 02 01:54:33 PM PDT 24
Finished Jun 02 01:54:59 PM PDT 24
Peak memory 248788 kb
Host smart-1ef1852a-82a1-48e8-b2b4-a2cf755c6c14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67777
8579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.677778579
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1029466074
Short name T680
Test name
Test status
Simulation time 218936512849 ps
CPU time 2749.52 seconds
Started Jun 02 01:54:34 PM PDT 24
Finished Jun 02 02:40:25 PM PDT 24
Peak memory 282336 kb
Host smart-affd5349-46a0-4cc7-a341-b48140a7dc75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029466074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1029466074
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1452475032
Short name T386
Test name
Test status
Simulation time 30907801402 ps
CPU time 1815.99 seconds
Started Jun 02 01:54:35 PM PDT 24
Finished Jun 02 02:24:52 PM PDT 24
Peak memory 289156 kb
Host smart-8010d0d4-60a4-43b5-89d6-dc7b893a99a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452475032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1452475032
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.304117004
Short name T302
Test name
Test status
Simulation time 3839851905 ps
CPU time 161.35 seconds
Started Jun 02 01:54:33 PM PDT 24
Finished Jun 02 01:57:15 PM PDT 24
Peak memory 248176 kb
Host smart-0c03e377-d843-46eb-ad5a-562463789dd5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304117004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.304117004
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1844785503
Short name T401
Test name
Test status
Simulation time 410978425 ps
CPU time 20.45 seconds
Started Jun 02 01:54:27 PM PDT 24
Finished Jun 02 01:54:49 PM PDT 24
Peak memory 248736 kb
Host smart-fe7dd27f-cd1c-48a3-b9b4-8c3056e9e7d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18447
85503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1844785503
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2153926647
Short name T625
Test name
Test status
Simulation time 79009103 ps
CPU time 3.98 seconds
Started Jun 02 01:54:36 PM PDT 24
Finished Jun 02 01:54:40 PM PDT 24
Peak memory 240412 kb
Host smart-5078a27f-8a3f-4e83-bfae-1cdf9738a263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21539
26647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2153926647
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3796512190
Short name T261
Test name
Test status
Simulation time 651893325 ps
CPU time 43.02 seconds
Started Jun 02 01:54:36 PM PDT 24
Finished Jun 02 01:55:19 PM PDT 24
Peak memory 255804 kb
Host smart-6f206c61-4a07-447d-a919-4fea79b65fd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37965
12190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3796512190
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.3926943881
Short name T377
Test name
Test status
Simulation time 4790832091 ps
CPU time 33.48 seconds
Started Jun 02 01:54:26 PM PDT 24
Finished Jun 02 01:55:00 PM PDT 24
Peak memory 248740 kb
Host smart-72d5238c-e2be-4c41-9112-b2b442f4b9ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39269
43881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.3926943881
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.630992532
Short name T275
Test name
Test status
Simulation time 105256570134 ps
CPU time 1737.27 seconds
Started Jun 02 01:54:33 PM PDT 24
Finished Jun 02 02:23:31 PM PDT 24
Peak memory 289500 kb
Host smart-a3a9db51-39db-4fc8-aa04-34ab7d2cd97f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630992532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.630992532
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.4268656349
Short name T207
Test name
Test status
Simulation time 15006399 ps
CPU time 2.58 seconds
Started Jun 02 01:52:54 PM PDT 24
Finished Jun 02 01:52:57 PM PDT 24
Peak memory 248896 kb
Host smart-b600f022-d3cd-4406-980d-b0e365818cb1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4268656349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.4268656349
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1111490234
Short name T429
Test name
Test status
Simulation time 329646838812 ps
CPU time 1637.14 seconds
Started Jun 02 01:52:56 PM PDT 24
Finished Jun 02 02:20:13 PM PDT 24
Peak memory 273372 kb
Host smart-6b72a9cb-9604-4aa2-bf20-82a1001faea6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111490234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1111490234
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.3907769599
Short name T672
Test name
Test status
Simulation time 971811604 ps
CPU time 44.19 seconds
Started Jun 02 01:52:56 PM PDT 24
Finished Jun 02 01:53:41 PM PDT 24
Peak memory 248760 kb
Host smart-e57f8c74-d188-47a8-99b2-f512699f8544
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3907769599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3907769599
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.2474917595
Short name T436
Test name
Test status
Simulation time 275931928 ps
CPU time 5.19 seconds
Started Jun 02 01:52:54 PM PDT 24
Finished Jun 02 01:53:00 PM PDT 24
Peak memory 239188 kb
Host smart-2cb54542-f6e1-4ed0-8fdd-33781c5efaea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24749
17595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2474917595
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2785891356
Short name T449
Test name
Test status
Simulation time 461008608 ps
CPU time 12.42 seconds
Started Jun 02 01:52:56 PM PDT 24
Finished Jun 02 01:53:09 PM PDT 24
Peak memory 255888 kb
Host smart-5b6b9cbc-420a-4670-bad0-61c9eddfbf03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27858
91356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2785891356
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.753070929
Short name T221
Test name
Test status
Simulation time 36517577351 ps
CPU time 1846.24 seconds
Started Jun 02 01:52:56 PM PDT 24
Finished Jun 02 02:23:43 PM PDT 24
Peak memory 273388 kb
Host smart-a165e56f-8f82-40c2-acbe-e746860afd39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753070929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.753070929
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.3103341625
Short name T511
Test name
Test status
Simulation time 16718647143 ps
CPU time 1067.82 seconds
Started Jun 02 01:52:55 PM PDT 24
Finished Jun 02 02:10:44 PM PDT 24
Peak memory 271384 kb
Host smart-1b591bdc-7e3e-478f-bffd-ae69931a1ca0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103341625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.3103341625
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.701422275
Short name T592
Test name
Test status
Simulation time 8309349916 ps
CPU time 88.5 seconds
Started Jun 02 01:52:54 PM PDT 24
Finished Jun 02 01:54:23 PM PDT 24
Peak memory 247096 kb
Host smart-8067f717-366b-4ad9-99ef-c44b0accad54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701422275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.701422275
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.4040106850
Short name T555
Test name
Test status
Simulation time 963797346 ps
CPU time 59.81 seconds
Started Jun 02 01:52:57 PM PDT 24
Finished Jun 02 01:53:57 PM PDT 24
Peak memory 256868 kb
Host smart-31435139-dc58-49c7-99b8-8d17865de370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40401
06850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.4040106850
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.305441745
Short name T553
Test name
Test status
Simulation time 812277795 ps
CPU time 53.84 seconds
Started Jun 02 01:52:53 PM PDT 24
Finished Jun 02 01:53:48 PM PDT 24
Peak memory 248500 kb
Host smart-7a2c4ff7-dafa-4afe-a382-dddbd38dd454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30544
1745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.305441745
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.594776113
Short name T14
Test name
Test status
Simulation time 470017515 ps
CPU time 25.43 seconds
Started Jun 02 01:52:53 PM PDT 24
Finished Jun 02 01:53:19 PM PDT 24
Peak memory 270348 kb
Host smart-4540e182-00d1-4fee-8774-4a452ff3784d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=594776113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.594776113
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2184613747
Short name T253
Test name
Test status
Simulation time 1004632117 ps
CPU time 27.71 seconds
Started Jun 02 01:53:03 PM PDT 24
Finished Jun 02 01:53:31 PM PDT 24
Peak memory 247144 kb
Host smart-9dc37faf-b06b-4999-89ab-a0c536160218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21846
13747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2184613747
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3704299320
Short name T496
Test name
Test status
Simulation time 550553912 ps
CPU time 33.06 seconds
Started Jun 02 01:53:00 PM PDT 24
Finished Jun 02 01:53:34 PM PDT 24
Peak memory 248716 kb
Host smart-59aa27a0-923b-4d3b-858e-8b3beaa83dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37042
99320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3704299320
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3323108160
Short name T591
Test name
Test status
Simulation time 67516140108 ps
CPU time 3371.89 seconds
Started Jun 02 01:54:39 PM PDT 24
Finished Jun 02 02:50:52 PM PDT 24
Peak memory 288920 kb
Host smart-0746b84c-3cb3-41d8-83ae-85e4eb3a6b55
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323108160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3323108160
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.4158040683
Short name T710
Test name
Test status
Simulation time 3520103590 ps
CPU time 120.6 seconds
Started Jun 02 01:54:33 PM PDT 24
Finished Jun 02 01:56:34 PM PDT 24
Peak memory 256948 kb
Host smart-76c9558e-d4f6-41eb-885a-d56131550a1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41580
40683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.4158040683
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3299705696
Short name T369
Test name
Test status
Simulation time 389642030 ps
CPU time 18.62 seconds
Started Jun 02 01:54:33 PM PDT 24
Finished Jun 02 01:54:52 PM PDT 24
Peak memory 255956 kb
Host smart-3d4e19b9-97f8-442f-b359-34b121bae224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32997
05696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3299705696
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.3467227118
Short name T688
Test name
Test status
Simulation time 38529822796 ps
CPU time 2290.06 seconds
Started Jun 02 01:54:41 PM PDT 24
Finished Jun 02 02:32:51 PM PDT 24
Peak memory 287816 kb
Host smart-7373e7e4-3dc2-4262-92d0-520bcaec3f62
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467227118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.3467227118
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.565596773
Short name T423
Test name
Test status
Simulation time 8258738342 ps
CPU time 954.6 seconds
Started Jun 02 01:54:38 PM PDT 24
Finished Jun 02 02:10:33 PM PDT 24
Peak memory 273352 kb
Host smart-8b65a77c-d596-47a0-94f1-0eea2bc8fe23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565596773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.565596773
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2286074095
Short name T283
Test name
Test status
Simulation time 12100569459 ps
CPU time 508 seconds
Started Jun 02 01:54:39 PM PDT 24
Finished Jun 02 02:03:07 PM PDT 24
Peak memory 247096 kb
Host smart-b252b68d-1eb5-4f2b-bb44-26f7075765dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286074095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2286074095
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.2689186291
Short name T361
Test name
Test status
Simulation time 647658151 ps
CPU time 32.42 seconds
Started Jun 02 01:54:33 PM PDT 24
Finished Jun 02 01:55:06 PM PDT 24
Peak memory 255900 kb
Host smart-9d0a0de8-1a91-4d28-b0d5-536ced13bbfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26891
86291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2689186291
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2521123650
Short name T711
Test name
Test status
Simulation time 716683973 ps
CPU time 31.65 seconds
Started Jun 02 01:54:32 PM PDT 24
Finished Jun 02 01:55:05 PM PDT 24
Peak memory 255440 kb
Host smart-dec39886-a536-476b-a290-1843fb4f1d7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25211
23650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2521123650
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.566176383
Short name T698
Test name
Test status
Simulation time 6010205796 ps
CPU time 26.32 seconds
Started Jun 02 01:54:35 PM PDT 24
Finished Jun 02 01:55:02 PM PDT 24
Peak memory 247676 kb
Host smart-1a10fab8-3c10-47a7-8b2a-5a5fb80d7421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56617
6383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.566176383
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.1442802541
Short name T76
Test name
Test status
Simulation time 306386262 ps
CPU time 32.98 seconds
Started Jun 02 01:54:33 PM PDT 24
Finished Jun 02 01:55:06 PM PDT 24
Peak memory 248728 kb
Host smart-367a821f-8cac-4963-bb5a-4231e0698670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14428
02541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.1442802541
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.1900825253
Short name T454
Test name
Test status
Simulation time 28653530 ps
CPU time 4.77 seconds
Started Jun 02 01:54:38 PM PDT 24
Finished Jun 02 01:54:44 PM PDT 24
Peak memory 252076 kb
Host smart-bd56d62f-f2a4-42e3-b570-55dcc23c74ee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900825253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1900825253
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2862576163
Short name T611
Test name
Test status
Simulation time 25739477374 ps
CPU time 811.64 seconds
Started Jun 02 01:54:46 PM PDT 24
Finished Jun 02 02:08:18 PM PDT 24
Peak memory 273316 kb
Host smart-7531c4b9-a5e7-4660-900f-cead07cfcddb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862576163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2862576163
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.69201710
Short name T117
Test name
Test status
Simulation time 3607794513 ps
CPU time 226.35 seconds
Started Jun 02 01:54:40 PM PDT 24
Finished Jun 02 01:58:27 PM PDT 24
Peak memory 250564 kb
Host smart-f343c2dd-47ef-41e4-a9f6-7d1f49547de1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69201
710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.69201710
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1500489378
Short name T589
Test name
Test status
Simulation time 2641348953 ps
CPU time 49.72 seconds
Started Jun 02 01:54:38 PM PDT 24
Finished Jun 02 01:55:29 PM PDT 24
Peak memory 248788 kb
Host smart-eda99726-e5a3-41f0-91d9-401c84138b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15004
89378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1500489378
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.2016864014
Short name T501
Test name
Test status
Simulation time 14959366150 ps
CPU time 692.56 seconds
Started Jun 02 01:54:47 PM PDT 24
Finished Jun 02 02:06:20 PM PDT 24
Peak memory 265144 kb
Host smart-16b5afa8-dcca-475f-83e1-2d6e262127d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016864014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.2016864014
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1758869437
Short name T682
Test name
Test status
Simulation time 33629703494 ps
CPU time 474.48 seconds
Started Jun 02 01:54:45 PM PDT 24
Finished Jun 02 02:02:40 PM PDT 24
Peak memory 265476 kb
Host smart-0aa45a83-86cc-44bf-a0f3-bf636728658e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758869437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1758869437
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.3878338771
Short name T561
Test name
Test status
Simulation time 23139009204 ps
CPU time 224.84 seconds
Started Jun 02 01:54:45 PM PDT 24
Finished Jun 02 01:58:30 PM PDT 24
Peak memory 255000 kb
Host smart-85636e9a-1c45-4b72-883f-f5a39d92c307
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878338771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.3878338771
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2286777880
Short name T272
Test name
Test status
Simulation time 1098325130 ps
CPU time 31.39 seconds
Started Jun 02 01:54:40 PM PDT 24
Finished Jun 02 01:55:12 PM PDT 24
Peak memory 248840 kb
Host smart-9c7d6a19-31db-4075-a795-f573f75c75e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22867
77880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2286777880
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.2436922469
Short name T487
Test name
Test status
Simulation time 664262007 ps
CPU time 40.05 seconds
Started Jun 02 01:54:43 PM PDT 24
Finished Jun 02 01:55:23 PM PDT 24
Peak memory 247560 kb
Host smart-ae9717a8-db3b-41b6-a239-035015ea16fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24369
22469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2436922469
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.449717815
Short name T257
Test name
Test status
Simulation time 4168092727 ps
CPU time 59.79 seconds
Started Jun 02 01:54:46 PM PDT 24
Finished Jun 02 01:55:47 PM PDT 24
Peak memory 248740 kb
Host smart-b7130e63-8c66-4c0b-885d-b414d80d9f01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44971
7815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.449717815
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2224233548
Short name T355
Test name
Test status
Simulation time 582605173 ps
CPU time 35.1 seconds
Started Jun 02 01:54:38 PM PDT 24
Finished Jun 02 01:55:14 PM PDT 24
Peak memory 248768 kb
Host smart-7e297075-a9ba-4d4a-a573-ffe497f8caff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22242
33548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2224233548
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.3338855434
Short name T521
Test name
Test status
Simulation time 3534725280 ps
CPU time 203.84 seconds
Started Jun 02 01:54:46 PM PDT 24
Finished Jun 02 01:58:10 PM PDT 24
Peak memory 256968 kb
Host smart-6dcf4cd9-7500-4e89-af5d-593a9fe5ca84
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338855434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.3338855434
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.766793901
Short name T665
Test name
Test status
Simulation time 48669560552 ps
CPU time 1234.86 seconds
Started Jun 02 01:54:46 PM PDT 24
Finished Jun 02 02:15:22 PM PDT 24
Peak memory 288976 kb
Host smart-ac5947cd-0eb9-490e-9316-4cf7c8cf4bdc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766793901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.766793901
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.197126632
Short name T122
Test name
Test status
Simulation time 431857552 ps
CPU time 44.36 seconds
Started Jun 02 01:54:45 PM PDT 24
Finished Jun 02 01:55:30 PM PDT 24
Peak memory 256848 kb
Host smart-4006aacf-4359-407d-aea1-05bf5728c1ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19712
6632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.197126632
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.959309727
Short name T461
Test name
Test status
Simulation time 3810250486 ps
CPU time 56.08 seconds
Started Jun 02 01:54:49 PM PDT 24
Finished Jun 02 01:55:46 PM PDT 24
Peak memory 249016 kb
Host smart-2f93020f-a74a-42d6-ad27-1917f9e6318a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95930
9727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.959309727
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3355042480
Short name T306
Test name
Test status
Simulation time 9479087210 ps
CPU time 794.4 seconds
Started Jun 02 01:54:52 PM PDT 24
Finished Jun 02 02:08:07 PM PDT 24
Peak memory 272648 kb
Host smart-a0a34f1f-e5a3-4733-be80-bb54e248931f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355042480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3355042480
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.3818310985
Short name T450
Test name
Test status
Simulation time 161532557418 ps
CPU time 2343.45 seconds
Started Jun 02 01:54:52 PM PDT 24
Finished Jun 02 02:33:56 PM PDT 24
Peak memory 283692 kb
Host smart-5941df3a-a388-4614-b2da-1c1f6e0cb519
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818310985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3818310985
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.2506471973
Short name T299
Test name
Test status
Simulation time 92929011240 ps
CPU time 683.28 seconds
Started Jun 02 01:54:44 PM PDT 24
Finished Jun 02 02:06:08 PM PDT 24
Peak memory 247992 kb
Host smart-f17a33d0-cf1b-42d7-816a-03e457d8b08e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506471973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.2506471973
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.3655118767
Short name T509
Test name
Test status
Simulation time 1128435676 ps
CPU time 33.65 seconds
Started Jun 02 01:54:45 PM PDT 24
Finished Jun 02 01:55:19 PM PDT 24
Peak memory 255976 kb
Host smart-3bd73b20-7749-485c-9189-01c9e367652e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36551
18767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3655118767
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.1462266403
Short name T388
Test name
Test status
Simulation time 465232947 ps
CPU time 9.63 seconds
Started Jun 02 01:54:46 PM PDT 24
Finished Jun 02 01:54:56 PM PDT 24
Peak memory 251300 kb
Host smart-a0b10587-61d8-404a-8eb8-c399a133e5ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14622
66403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.1462266403
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.615278250
Short name T558
Test name
Test status
Simulation time 2695463654 ps
CPU time 50.26 seconds
Started Jun 02 01:54:47 PM PDT 24
Finished Jun 02 01:55:37 PM PDT 24
Peak memory 255484 kb
Host smart-f18391cc-cf8b-489d-bd62-66aa917410ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61527
8250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.615278250
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2133493881
Short name T516
Test name
Test status
Simulation time 253442799 ps
CPU time 12.46 seconds
Started Jun 02 01:54:49 PM PDT 24
Finished Jun 02 01:55:02 PM PDT 24
Peak memory 248724 kb
Host smart-e4f268a2-5142-41ec-b647-3b96fd6d292b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21334
93881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2133493881
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.1793807661
Short name T274
Test name
Test status
Simulation time 179247478516 ps
CPU time 2628.81 seconds
Started Jun 02 01:54:51 PM PDT 24
Finished Jun 02 02:38:40 PM PDT 24
Peak memory 285712 kb
Host smart-75d0e1c5-db48-4985-a01a-2381209e88a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793807661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.1793807661
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.2465382165
Short name T686
Test name
Test status
Simulation time 756107774 ps
CPU time 71.14 seconds
Started Jun 02 01:54:52 PM PDT 24
Finished Jun 02 01:56:04 PM PDT 24
Peak memory 256816 kb
Host smart-19302c06-820a-452a-8e5f-004909e26e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24653
82165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.2465382165
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3307153854
Short name T573
Test name
Test status
Simulation time 3298057251 ps
CPU time 29.45 seconds
Started Jun 02 01:54:53 PM PDT 24
Finished Jun 02 01:55:23 PM PDT 24
Peak memory 248812 kb
Host smart-e545cd0a-0c7f-48ca-882a-2fe3c82c4087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33071
53854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3307153854
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.127251977
Short name T498
Test name
Test status
Simulation time 22464733577 ps
CPU time 946.19 seconds
Started Jun 02 01:54:51 PM PDT 24
Finished Jun 02 02:10:38 PM PDT 24
Peak memory 273384 kb
Host smart-1d3fe3df-ed1d-4c29-a198-90cc52d791af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127251977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.127251977
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.3351720388
Short name T32
Test name
Test status
Simulation time 9584392790 ps
CPU time 1036.76 seconds
Started Jun 02 01:55:00 PM PDT 24
Finished Jun 02 02:12:17 PM PDT 24
Peak memory 270796 kb
Host smart-3833409c-5c27-49ac-96c1-1313b8c5dc9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351720388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3351720388
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.219420584
Short name T518
Test name
Test status
Simulation time 257978238 ps
CPU time 20.68 seconds
Started Jun 02 01:54:52 PM PDT 24
Finished Jun 02 01:55:14 PM PDT 24
Peak memory 248732 kb
Host smart-a3664bed-fb83-4c96-b9b7-cba9b96bb6a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21942
0584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.219420584
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.1849954156
Short name T704
Test name
Test status
Simulation time 416075258 ps
CPU time 34.95 seconds
Started Jun 02 01:54:52 PM PDT 24
Finished Jun 02 01:55:28 PM PDT 24
Peak memory 255496 kb
Host smart-1f9fcc90-69aa-4181-af5a-08811be19060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18499
54156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1849954156
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.3880210271
Short name T442
Test name
Test status
Simulation time 1837703947 ps
CPU time 51.55 seconds
Started Jun 02 01:54:52 PM PDT 24
Finished Jun 02 01:55:44 PM PDT 24
Peak memory 248972 kb
Host smart-54b44f33-fe3e-4ec0-bce8-9cb4cfd7bd13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38802
10271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3880210271
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2174468035
Short name T568
Test name
Test status
Simulation time 103710803562 ps
CPU time 2756.81 seconds
Started Jun 02 01:54:59 PM PDT 24
Finished Jun 02 02:40:56 PM PDT 24
Peak memory 289708 kb
Host smart-c477046a-9f1f-4faf-97bc-59e459cea814
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174468035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2174468035
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.3410845876
Short name T226
Test name
Test status
Simulation time 100446277312 ps
CPU time 3155.46 seconds
Started Jun 02 01:54:58 PM PDT 24
Finished Jun 02 02:47:34 PM PDT 24
Peak memory 305756 kb
Host smart-b92fb440-d699-4041-b43b-6f5035114089
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410845876 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.3410845876
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.3864692628
Short name T628
Test name
Test status
Simulation time 10258598436 ps
CPU time 1080.73 seconds
Started Jun 02 01:55:03 PM PDT 24
Finished Jun 02 02:13:04 PM PDT 24
Peak memory 273360 kb
Host smart-1da84ba0-8c43-4aa5-86fd-fbcb4fbb86e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864692628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3864692628
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.470089276
Short name T366
Test name
Test status
Simulation time 217443872 ps
CPU time 11.14 seconds
Started Jun 02 01:55:03 PM PDT 24
Finished Jun 02 01:55:14 PM PDT 24
Peak memory 255008 kb
Host smart-64b1bf6d-4ea6-4dab-9bf3-2dbe03f1f304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47008
9276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.470089276
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1351901879
Short name T21
Test name
Test status
Simulation time 697251111 ps
CPU time 22.66 seconds
Started Jun 02 01:54:59 PM PDT 24
Finished Jun 02 01:55:22 PM PDT 24
Peak memory 249016 kb
Host smart-0a7e6768-c3c4-4c93-b5c9-2f3c9d3f2435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13519
01879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1351901879
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3542946285
Short name T524
Test name
Test status
Simulation time 114083109314 ps
CPU time 1724.74 seconds
Started Jun 02 01:54:58 PM PDT 24
Finished Jun 02 02:23:43 PM PDT 24
Peak memory 273000 kb
Host smart-d95a7656-069a-4802-a782-31a23782935c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542946285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3542946285
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1115411979
Short name T68
Test name
Test status
Simulation time 112110068323 ps
CPU time 3372 seconds
Started Jun 02 01:55:02 PM PDT 24
Finished Jun 02 02:51:15 PM PDT 24
Peak memory 289568 kb
Host smart-1d6b6693-53fd-483e-b405-e71ef41f2168
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115411979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1115411979
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.507052282
Short name T301
Test name
Test status
Simulation time 26386262650 ps
CPU time 548.27 seconds
Started Jun 02 01:54:58 PM PDT 24
Finished Jun 02 02:04:06 PM PDT 24
Peak memory 248268 kb
Host smart-165e5a3c-1d28-4eba-aac9-5b0b2ffe91aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507052282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.507052282
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.4084941941
Short name T408
Test name
Test status
Simulation time 1670806645 ps
CPU time 50.29 seconds
Started Jun 02 01:54:58 PM PDT 24
Finished Jun 02 01:55:49 PM PDT 24
Peak memory 248648 kb
Host smart-f868de53-b706-4155-931e-2793ef4e9085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40849
41941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.4084941941
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.664720560
Short name T635
Test name
Test status
Simulation time 263655980 ps
CPU time 19.02 seconds
Started Jun 02 01:54:58 PM PDT 24
Finished Jun 02 01:55:17 PM PDT 24
Peak memory 255236 kb
Host smart-f3085e5c-d129-4ce6-995b-d1ce8c2a9440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66472
0560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.664720560
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.3068758908
Short name T223
Test name
Test status
Simulation time 440268872 ps
CPU time 17.23 seconds
Started Jun 02 01:54:57 PM PDT 24
Finished Jun 02 01:55:15 PM PDT 24
Peak memory 247412 kb
Host smart-40ff17db-f18e-4d77-b791-ed05897c335d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30687
58908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.3068758908
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.4178769440
Short name T46
Test name
Test status
Simulation time 670464197 ps
CPU time 43.86 seconds
Started Jun 02 01:55:03 PM PDT 24
Finished Jun 02 01:55:47 PM PDT 24
Peak memory 248740 kb
Host smart-942ebad7-6164-483a-bb4a-47250043c77f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41787
69440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.4178769440
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.3082355609
Short name T241
Test name
Test status
Simulation time 30154943691 ps
CPU time 1434.55 seconds
Started Jun 02 01:54:59 PM PDT 24
Finished Jun 02 02:18:55 PM PDT 24
Peak memory 289736 kb
Host smart-abb4e0dd-6ae1-4b5b-b86a-a57b4530f293
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082355609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.3082355609
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.2149343042
Short name T123
Test name
Test status
Simulation time 51118145226 ps
CPU time 5231.66 seconds
Started Jun 02 01:54:59 PM PDT 24
Finished Jun 02 03:22:12 PM PDT 24
Peak memory 338964 kb
Host smart-6b7c09c7-de3e-45f9-8c86-9568b3a3790a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149343042 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.2149343042
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2896499540
Short name T499
Test name
Test status
Simulation time 219214387674 ps
CPU time 3331.31 seconds
Started Jun 02 01:55:04 PM PDT 24
Finished Jun 02 02:50:36 PM PDT 24
Peak memory 289576 kb
Host smart-dfea9919-b8cf-46cf-be48-8cebd50675f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896499540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2896499540
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.2831471732
Short name T20
Test name
Test status
Simulation time 8377663913 ps
CPU time 161.29 seconds
Started Jun 02 01:55:06 PM PDT 24
Finished Jun 02 01:57:47 PM PDT 24
Peak memory 250872 kb
Host smart-8822e13f-a205-4475-8b3e-32dd9ccaea1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28314
71732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2831471732
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.833448200
Short name T534
Test name
Test status
Simulation time 66211806 ps
CPU time 10.33 seconds
Started Jun 02 01:55:05 PM PDT 24
Finished Jun 02 01:55:16 PM PDT 24
Peak memory 249104 kb
Host smart-70196404-2732-4ded-85d9-0f00e0f3adbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83344
8200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.833448200
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2498280879
Short name T322
Test name
Test status
Simulation time 38700280886 ps
CPU time 2480.77 seconds
Started Jun 02 01:55:10 PM PDT 24
Finished Jun 02 02:36:32 PM PDT 24
Peak memory 285216 kb
Host smart-946fcca2-8f7c-43d9-b5b2-9a336359e74b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498280879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2498280879
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1668917824
Short name T43
Test name
Test status
Simulation time 183132472760 ps
CPU time 2856.67 seconds
Started Jun 02 01:55:11 PM PDT 24
Finished Jun 02 02:42:49 PM PDT 24
Peak memory 289692 kb
Host smart-80673976-c1f3-459c-a7cb-34af58cc7061
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668917824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1668917824
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1449399983
Short name T313
Test name
Test status
Simulation time 152990381943 ps
CPU time 412.53 seconds
Started Jun 02 01:55:04 PM PDT 24
Finished Jun 02 02:01:57 PM PDT 24
Peak memory 248156 kb
Host smart-c42917a8-4a69-4078-bd4e-3d68dd75c707
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449399983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1449399983
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.357928570
Short name T443
Test name
Test status
Simulation time 8034222068 ps
CPU time 62.96 seconds
Started Jun 02 01:55:04 PM PDT 24
Finished Jun 02 01:56:07 PM PDT 24
Peak memory 256104 kb
Host smart-b962c07c-c28a-4736-994a-6e8904fbe3d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35792
8570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.357928570
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.213066681
Short name T54
Test name
Test status
Simulation time 194609891 ps
CPU time 19.91 seconds
Started Jun 02 01:55:04 PM PDT 24
Finished Jun 02 01:55:24 PM PDT 24
Peak memory 248788 kb
Host smart-4de74b52-ed37-4bd7-bc74-05cc8929a6a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21306
6681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.213066681
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.550453388
Short name T468
Test name
Test status
Simulation time 1226882611 ps
CPU time 39.12 seconds
Started Jun 02 01:55:06 PM PDT 24
Finished Jun 02 01:55:45 PM PDT 24
Peak memory 255380 kb
Host smart-7020bec9-33fb-4bd8-91f5-16b281dfb180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55045
3388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.550453388
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.176318657
Short name T494
Test name
Test status
Simulation time 147214805 ps
CPU time 3.75 seconds
Started Jun 02 01:55:05 PM PDT 24
Finished Jun 02 01:55:09 PM PDT 24
Peak memory 250868 kb
Host smart-6b61aea6-3698-41eb-8eec-6675c171ccce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17631
8657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.176318657
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2399165107
Short name T504
Test name
Test status
Simulation time 43651775032 ps
CPU time 444.75 seconds
Started Jun 02 01:55:11 PM PDT 24
Finished Jun 02 02:02:36 PM PDT 24
Peak memory 256940 kb
Host smart-e84a26a7-7391-4499-8fea-2414d286fc63
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399165107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2399165107
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.3753346261
Short name T229
Test name
Test status
Simulation time 78856055300 ps
CPU time 2557.17 seconds
Started Jun 02 01:55:11 PM PDT 24
Finished Jun 02 02:37:49 PM PDT 24
Peak memory 289448 kb
Host smart-5d7eff8c-6f73-4bec-97a2-cde147a3b1d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753346261 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.3753346261
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.448832504
Short name T264
Test name
Test status
Simulation time 9499672458 ps
CPU time 1049.35 seconds
Started Jun 02 01:55:13 PM PDT 24
Finished Jun 02 02:12:43 PM PDT 24
Peak memory 282524 kb
Host smart-02f7d58f-c07c-4185-8ca5-598c3b3acf38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448832504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.448832504
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.565976482
Short name T363
Test name
Test status
Simulation time 1185045112 ps
CPU time 81.94 seconds
Started Jun 02 01:55:12 PM PDT 24
Finished Jun 02 01:56:34 PM PDT 24
Peak memory 248736 kb
Host smart-28631865-36f4-4a72-9ba8-a088f2efb125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56597
6482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.565976482
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.586541284
Short name T535
Test name
Test status
Simulation time 816690981 ps
CPU time 24.67 seconds
Started Jun 02 01:55:12 PM PDT 24
Finished Jun 02 01:55:37 PM PDT 24
Peak memory 256064 kb
Host smart-eb1a3645-8873-4ec8-851c-65abc87a08de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58654
1284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.586541284
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.2867705059
Short name T281
Test name
Test status
Simulation time 29459205961 ps
CPU time 1546.38 seconds
Started Jun 02 01:55:10 PM PDT 24
Finished Jun 02 02:20:57 PM PDT 24
Peak memory 289088 kb
Host smart-f1d0cc46-57a3-4e3c-a2af-242d4cf0865b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867705059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.2867705059
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2291920489
Short name T17
Test name
Test status
Simulation time 5777305906 ps
CPU time 975.51 seconds
Started Jun 02 01:55:12 PM PDT 24
Finished Jun 02 02:11:28 PM PDT 24
Peak memory 273408 kb
Host smart-aea8d76b-68e4-425a-a9e4-e038e3cfa297
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291920489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2291920489
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.1161114377
Short name T312
Test name
Test status
Simulation time 29607951183 ps
CPU time 311.39 seconds
Started Jun 02 01:55:11 PM PDT 24
Finished Jun 02 02:00:23 PM PDT 24
Peak memory 248212 kb
Host smart-17a9cd5a-cf18-4fed-a533-d9bb5305961d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161114377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1161114377
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.790423373
Short name T473
Test name
Test status
Simulation time 550066094 ps
CPU time 16.53 seconds
Started Jun 02 01:55:10 PM PDT 24
Finished Jun 02 01:55:27 PM PDT 24
Peak memory 248748 kb
Host smart-caf34d9f-4258-49fa-8f98-84ba9267ff40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79042
3373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.790423373
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.4204334112
Short name T706
Test name
Test status
Simulation time 140599125 ps
CPU time 9.75 seconds
Started Jun 02 01:55:11 PM PDT 24
Finished Jun 02 01:55:21 PM PDT 24
Peak memory 251484 kb
Host smart-374bd109-e9cc-424a-a125-87d55c59c3c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42043
34112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.4204334112
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.3572002213
Short name T78
Test name
Test status
Simulation time 71259750 ps
CPU time 5.89 seconds
Started Jun 02 01:55:14 PM PDT 24
Finished Jun 02 01:55:20 PM PDT 24
Peak memory 252668 kb
Host smart-1cbf6c7e-d093-49e3-8921-c42bd54dcca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35720
02213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3572002213
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.66920751
Short name T451
Test name
Test status
Simulation time 1800400919 ps
CPU time 29.52 seconds
Started Jun 02 01:55:12 PM PDT 24
Finished Jun 02 01:55:42 PM PDT 24
Peak memory 248736 kb
Host smart-67ea3661-fc5c-4083-a991-537cce808121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66920
751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.66920751
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.4137342868
Short name T119
Test name
Test status
Simulation time 54880301046 ps
CPU time 1667.79 seconds
Started Jun 02 01:55:12 PM PDT 24
Finished Jun 02 02:23:01 PM PDT 24
Peak memory 273308 kb
Host smart-26250203-dbe6-4089-81c3-a44748202964
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137342868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.4137342868
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.2854559305
Short name T230
Test name
Test status
Simulation time 311012412267 ps
CPU time 5022.29 seconds
Started Jun 02 01:55:12 PM PDT 24
Finished Jun 02 03:18:56 PM PDT 24
Peak memory 306272 kb
Host smart-2ff866c7-44f5-42cb-a741-006ce571b48b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854559305 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.2854559305
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2947135856
Short name T542
Test name
Test status
Simulation time 51169663239 ps
CPU time 1578.68 seconds
Started Jun 02 01:55:15 PM PDT 24
Finished Jun 02 02:21:35 PM PDT 24
Peak memory 272116 kb
Host smart-29ee3775-aa35-4bb8-b157-20766b51438d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947135856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2947135856
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1528803257
Short name T538
Test name
Test status
Simulation time 12499193104 ps
CPU time 256.3 seconds
Started Jun 02 01:55:18 PM PDT 24
Finished Jun 02 01:59:34 PM PDT 24
Peak memory 256916 kb
Host smart-d4ab6e63-4257-4785-af8a-6fed21442391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15288
03257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1528803257
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.921796110
Short name T595
Test name
Test status
Simulation time 77461798 ps
CPU time 3.76 seconds
Started Jun 02 01:55:16 PM PDT 24
Finished Jun 02 01:55:20 PM PDT 24
Peak memory 239152 kb
Host smart-e306ea5f-4f0f-43de-a52d-6bdb86114bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92179
6110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.921796110
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.1313745033
Short name T616
Test name
Test status
Simulation time 7835314953 ps
CPU time 711.5 seconds
Started Jun 02 01:55:16 PM PDT 24
Finished Jun 02 02:07:08 PM PDT 24
Peak memory 271028 kb
Host smart-6bc9b833-7249-4818-8bac-1e21d6021f22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313745033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1313745033
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.4049052708
Short name T384
Test name
Test status
Simulation time 6323484899 ps
CPU time 691.56 seconds
Started Jun 02 01:55:17 PM PDT 24
Finished Jun 02 02:06:49 PM PDT 24
Peak memory 273352 kb
Host smart-6eb7b62f-d19e-417d-b809-c581b4b950eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049052708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.4049052708
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.1636572084
Short name T284
Test name
Test status
Simulation time 19459988452 ps
CPU time 430.07 seconds
Started Jun 02 01:55:15 PM PDT 24
Finished Jun 02 02:02:26 PM PDT 24
Peak memory 256272 kb
Host smart-0210b82c-aba2-447b-912e-93c46cbad83d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636572084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1636572084
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2044566052
Short name T634
Test name
Test status
Simulation time 3806915075 ps
CPU time 45.76 seconds
Started Jun 02 01:55:18 PM PDT 24
Finished Jun 02 01:56:05 PM PDT 24
Peak memory 248776 kb
Host smart-98ae76be-6421-42b9-9781-e7b483feb6f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20445
66052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2044566052
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.847090703
Short name T624
Test name
Test status
Simulation time 732543330 ps
CPU time 13.13 seconds
Started Jun 02 01:55:17 PM PDT 24
Finished Jun 02 01:55:30 PM PDT 24
Peak memory 251956 kb
Host smart-35d73fe6-a0dd-48fd-abe8-6d36f44dfddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84709
0703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.847090703
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.2267383087
Short name T259
Test name
Test status
Simulation time 121184067 ps
CPU time 5.85 seconds
Started Jun 02 01:55:16 PM PDT 24
Finished Jun 02 01:55:22 PM PDT 24
Peak memory 239168 kb
Host smart-48ecfc55-195e-4b4b-ad7f-801ea91323f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22673
83087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.2267383087
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.446303286
Short name T586
Test name
Test status
Simulation time 1392295972 ps
CPU time 24.13 seconds
Started Jun 02 01:55:11 PM PDT 24
Finished Jun 02 01:55:35 PM PDT 24
Peak memory 248648 kb
Host smart-648b84fc-dd26-4d42-a7b6-acfae4d693c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44630
3286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.446303286
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.584401368
Short name T480
Test name
Test status
Simulation time 29627954090 ps
CPU time 936.91 seconds
Started Jun 02 01:55:16 PM PDT 24
Finished Jun 02 02:10:54 PM PDT 24
Peak memory 289272 kb
Host smart-4013bafa-3a1b-475c-ae6b-688013bb4cd4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584401368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_han
dler_stress_all.584401368
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3295425753
Short name T407
Test name
Test status
Simulation time 6838482561 ps
CPU time 886.43 seconds
Started Jun 02 01:55:25 PM PDT 24
Finished Jun 02 02:10:12 PM PDT 24
Peak memory 268456 kb
Host smart-e1b42b88-9e8b-42f7-9254-7f3d95600fbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295425753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3295425753
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.174868542
Short name T40
Test name
Test status
Simulation time 3919911079 ps
CPU time 210.68 seconds
Started Jun 02 01:55:25 PM PDT 24
Finished Jun 02 01:58:56 PM PDT 24
Peak memory 256160 kb
Host smart-64475792-6b79-45a2-9602-9e521414a3e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17486
8542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.174868542
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.460567743
Short name T67
Test name
Test status
Simulation time 2585997283 ps
CPU time 39.4 seconds
Started Jun 02 01:55:23 PM PDT 24
Finished Jun 02 01:56:03 PM PDT 24
Peak memory 248892 kb
Host smart-1d36697d-75e1-4857-87ca-913673b224e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46056
7743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.460567743
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1033090954
Short name T562
Test name
Test status
Simulation time 19272693097 ps
CPU time 1208.96 seconds
Started Jun 02 01:55:24 PM PDT 24
Finished Jun 02 02:15:33 PM PDT 24
Peak memory 283660 kb
Host smart-0fcaab86-a474-4717-88a9-f08b150fd765
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033090954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1033090954
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1588053096
Short name T424
Test name
Test status
Simulation time 26242287360 ps
CPU time 1492.46 seconds
Started Jun 02 01:55:26 PM PDT 24
Finished Jun 02 02:20:19 PM PDT 24
Peak memory 265192 kb
Host smart-84c4fa40-d122-46d4-81f4-7a0f96b1f3e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588053096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1588053096
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.711350765
Short name T675
Test name
Test status
Simulation time 177952164837 ps
CPU time 641.59 seconds
Started Jun 02 01:55:24 PM PDT 24
Finished Jun 02 02:06:05 PM PDT 24
Peak memory 247916 kb
Host smart-33c188c8-d043-478d-92e1-dcaa9efece43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711350765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.711350765
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1329084498
Short name T623
Test name
Test status
Simulation time 376938711 ps
CPU time 8.3 seconds
Started Jun 02 01:55:17 PM PDT 24
Finished Jun 02 01:55:26 PM PDT 24
Peak memory 248732 kb
Host smart-0ebf6847-b1b3-4e80-8b75-332ca4a0d227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13290
84498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1329084498
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.1949795771
Short name T109
Test name
Test status
Simulation time 689269070 ps
CPU time 48.46 seconds
Started Jun 02 01:55:25 PM PDT 24
Finished Jun 02 01:56:14 PM PDT 24
Peak memory 255512 kb
Host smart-fcbe0297-2b48-407d-bdfc-494d64f986dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19497
95771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1949795771
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.428880511
Short name T89
Test name
Test status
Simulation time 591897228 ps
CPU time 16.78 seconds
Started Jun 02 01:55:25 PM PDT 24
Finished Jun 02 01:55:42 PM PDT 24
Peak memory 255416 kb
Host smart-62630a09-17c3-410a-8e8a-ab4063a263d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42888
0511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.428880511
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.1936323901
Short name T472
Test name
Test status
Simulation time 1179556056 ps
CPU time 34.66 seconds
Started Jun 02 01:55:20 PM PDT 24
Finished Jun 02 01:55:55 PM PDT 24
Peak memory 256016 kb
Host smart-139d6307-7925-423e-aad8-a92b839d2714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19363
23901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.1936323901
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.2302226889
Short name T551
Test name
Test status
Simulation time 148647525904 ps
CPU time 2641.74 seconds
Started Jun 02 01:55:32 PM PDT 24
Finished Jun 02 02:39:34 PM PDT 24
Peak memory 289392 kb
Host smart-ed8b85aa-142a-4db4-983e-55533de62e0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302226889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2302226889
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.3388690314
Short name T30
Test name
Test status
Simulation time 2912096868 ps
CPU time 172.75 seconds
Started Jun 02 01:55:32 PM PDT 24
Finished Jun 02 01:58:26 PM PDT 24
Peak memory 249872 kb
Host smart-d3fdaff9-14b3-424e-8d78-752ba14c9cfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33886
90314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.3388690314
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.2757234094
Short name T510
Test name
Test status
Simulation time 1126999110 ps
CPU time 27.65 seconds
Started Jun 02 01:55:31 PM PDT 24
Finished Jun 02 01:55:59 PM PDT 24
Peak memory 248692 kb
Host smart-f174fbd5-5552-40ad-866b-21b5e6b61dd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27572
34094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.2757234094
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3569318745
Short name T325
Test name
Test status
Simulation time 18592296435 ps
CPU time 1111.8 seconds
Started Jun 02 01:55:34 PM PDT 24
Finished Jun 02 02:14:06 PM PDT 24
Peak memory 271724 kb
Host smart-24412446-b933-43ee-98e2-fc73847a5b35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569318745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3569318745
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.33233893
Short name T121
Test name
Test status
Simulation time 12612693462 ps
CPU time 1305.14 seconds
Started Jun 02 01:55:40 PM PDT 24
Finished Jun 02 02:17:26 PM PDT 24
Peak memory 289544 kb
Host smart-1b0c51f8-aa3a-4ae9-8d73-fc5396c63f68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33233893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.33233893
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.2651355251
Short name T307
Test name
Test status
Simulation time 18708512390 ps
CPU time 206.03 seconds
Started Jun 02 01:55:31 PM PDT 24
Finished Jun 02 01:58:58 PM PDT 24
Peak memory 248276 kb
Host smart-7f630bc6-e168-43bd-b7c2-4d152cfe7edc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651355251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.2651355251
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.4168278413
Short name T620
Test name
Test status
Simulation time 757317926 ps
CPU time 46.53 seconds
Started Jun 02 01:55:31 PM PDT 24
Finished Jun 02 01:56:18 PM PDT 24
Peak memory 248724 kb
Host smart-e03c65e1-bd86-4e01-b872-5e380f6474bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41682
78413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.4168278413
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.3286198703
Short name T639
Test name
Test status
Simulation time 2004917928 ps
CPU time 44.55 seconds
Started Jun 02 01:55:32 PM PDT 24
Finished Jun 02 01:56:17 PM PDT 24
Peak memory 256528 kb
Host smart-dd0b63d9-99aa-4097-935d-b2d4e9c8af3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32861
98703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.3286198703
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3368918291
Short name T94
Test name
Test status
Simulation time 296358268 ps
CPU time 3.8 seconds
Started Jun 02 01:55:32 PM PDT 24
Finished Jun 02 01:55:36 PM PDT 24
Peak memory 240504 kb
Host smart-a5cfc659-33d4-47e6-b58a-d34f9955adf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33689
18291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3368918291
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.1391927329
Short name T71
Test name
Test status
Simulation time 214113214 ps
CPU time 13.14 seconds
Started Jun 02 01:55:26 PM PDT 24
Finished Jun 02 01:55:39 PM PDT 24
Peak memory 249088 kb
Host smart-6fd4be11-50f8-4e4d-baf8-062a362a3551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13919
27329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.1391927329
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.129837039
Short name T210
Test name
Test status
Simulation time 33717651 ps
CPU time 3.1 seconds
Started Jun 02 01:53:01 PM PDT 24
Finished Jun 02 01:53:04 PM PDT 24
Peak memory 248892 kb
Host smart-0f1063e8-f613-4600-b234-518ac15085c6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=129837039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.129837039
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.3968560591
Short name T530
Test name
Test status
Simulation time 32479819765 ps
CPU time 1646.83 seconds
Started Jun 02 01:53:03 PM PDT 24
Finished Jun 02 02:20:30 PM PDT 24
Peak memory 289388 kb
Host smart-7918aab0-716b-45c1-9b3c-e550e822f7c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968560591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.3968560591
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2430010232
Short name T95
Test name
Test status
Simulation time 3095092761 ps
CPU time 36.02 seconds
Started Jun 02 01:53:03 PM PDT 24
Finished Jun 02 01:53:40 PM PDT 24
Peak memory 240576 kb
Host smart-f7232f23-5326-46c2-97d3-b5258dbe2515
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2430010232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2430010232
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2778356408
Short name T662
Test name
Test status
Simulation time 1771073149 ps
CPU time 81.35 seconds
Started Jun 02 01:53:02 PM PDT 24
Finished Jun 02 01:54:23 PM PDT 24
Peak memory 248544 kb
Host smart-0977ccf4-11e6-4613-b76e-766b5f1b91c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27783
56408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2778356408
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1720824155
Short name T96
Test name
Test status
Simulation time 940504440 ps
CPU time 43.27 seconds
Started Jun 02 01:53:03 PM PDT 24
Finished Jun 02 01:53:47 PM PDT 24
Peak memory 255780 kb
Host smart-756969b7-b306-4efb-abf9-e93b031f5ebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17208
24155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1720824155
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.3774608699
Short name T543
Test name
Test status
Simulation time 7153495546 ps
CPU time 657.96 seconds
Started Jun 02 01:53:02 PM PDT 24
Finished Jun 02 02:04:00 PM PDT 24
Peak memory 272804 kb
Host smart-b60a3c7a-f149-4dbf-8c8f-c7715a16a185
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774608699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3774608699
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.41013598
Short name T353
Test name
Test status
Simulation time 106870990249 ps
CPU time 2780.33 seconds
Started Jun 02 01:53:03 PM PDT 24
Finished Jun 02 02:39:24 PM PDT 24
Peak memory 288744 kb
Host smart-ab4246f0-c734-42fa-b69d-3f7e141f8b9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41013598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.41013598
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.826938451
Short name T304
Test name
Test status
Simulation time 9879449018 ps
CPU time 400.18 seconds
Started Jun 02 01:53:04 PM PDT 24
Finished Jun 02 01:59:45 PM PDT 24
Peak memory 247052 kb
Host smart-8d9bf764-b4b7-405a-af45-610096432aa1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826938451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.826938451
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3743518214
Short name T459
Test name
Test status
Simulation time 1557149398 ps
CPU time 53.91 seconds
Started Jun 02 01:53:01 PM PDT 24
Finished Jun 02 01:53:55 PM PDT 24
Peak memory 248732 kb
Host smart-6e6c7197-859e-4f63-a2d4-75e38690ff5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37435
18214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3743518214
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.2132911898
Short name T446
Test name
Test status
Simulation time 708727803 ps
CPU time 24.96 seconds
Started Jun 02 01:53:04 PM PDT 24
Finished Jun 02 01:53:29 PM PDT 24
Peak memory 248864 kb
Host smart-887e4298-4b29-4408-8ca3-9b548148d7f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21329
11898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2132911898
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.2588476855
Short name T12
Test name
Test status
Simulation time 1114488557 ps
CPU time 47.97 seconds
Started Jun 02 01:53:01 PM PDT 24
Finished Jun 02 01:53:50 PM PDT 24
Peak memory 277524 kb
Host smart-d252a4fa-4224-4330-a33a-14c345490200
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2588476855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2588476855
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.110410921
Short name T244
Test name
Test status
Simulation time 2540443732 ps
CPU time 40.69 seconds
Started Jun 02 01:53:02 PM PDT 24
Finished Jun 02 01:53:43 PM PDT 24
Peak memory 254920 kb
Host smart-6e994237-63ab-4a47-a662-ccb524f79cbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11041
0921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.110410921
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1087264193
Short name T685
Test name
Test status
Simulation time 326133204 ps
CPU time 12.12 seconds
Started Jun 02 01:53:01 PM PDT 24
Finished Jun 02 01:53:13 PM PDT 24
Peak memory 248732 kb
Host smart-a6e10935-9550-48f2-8cda-4c9eb0f28c48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10872
64193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1087264193
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.2203128318
Short name T598
Test name
Test status
Simulation time 384261164 ps
CPU time 15.85 seconds
Started Jun 02 01:53:00 PM PDT 24
Finished Jun 02 01:53:17 PM PDT 24
Peak memory 248704 kb
Host smart-038a58dc-1b8a-4a2c-a0bf-73c068772946
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203128318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.2203128318
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.3764161799
Short name T563
Test name
Test status
Simulation time 10019885917 ps
CPU time 940.96 seconds
Started Jun 02 01:53:02 PM PDT 24
Finished Jun 02 02:08:44 PM PDT 24
Peak memory 273484 kb
Host smart-c55735cc-e8f6-4b7c-8e7b-fce8bcbaaeac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764161799 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.3764161799
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.4233737289
Short name T637
Test name
Test status
Simulation time 100965302838 ps
CPU time 1583.66 seconds
Started Jun 02 01:55:38 PM PDT 24
Finished Jun 02 02:22:02 PM PDT 24
Peak memory 273592 kb
Host smart-353585d8-14d2-4235-9a49-410dd36c244b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233737289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.4233737289
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.1431129805
Short name T664
Test name
Test status
Simulation time 5567709290 ps
CPU time 307.23 seconds
Started Jun 02 01:55:39 PM PDT 24
Finished Jun 02 02:00:47 PM PDT 24
Peak memory 251368 kb
Host smart-46009d4a-4b76-4343-aa0d-d9c432cc5627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14311
29805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1431129805
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.500276547
Short name T467
Test name
Test status
Simulation time 284211952 ps
CPU time 16.61 seconds
Started Jun 02 01:55:39 PM PDT 24
Finished Jun 02 01:55:56 PM PDT 24
Peak memory 254728 kb
Host smart-9a57a79c-aa68-4981-9086-4315c3dbdbd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50027
6547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.500276547
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.644293499
Short name T483
Test name
Test status
Simulation time 117497689086 ps
CPU time 1905.87 seconds
Started Jun 02 01:55:38 PM PDT 24
Finished Jun 02 02:27:24 PM PDT 24
Peak memory 271388 kb
Host smart-382547df-4e6f-4e46-8215-9dfa81e3a03b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644293499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.644293499
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.2188168509
Short name T463
Test name
Test status
Simulation time 18850792776 ps
CPU time 1282.31 seconds
Started Jun 02 01:55:39 PM PDT 24
Finished Jun 02 02:17:02 PM PDT 24
Peak memory 284844 kb
Host smart-f68ddef9-fa4a-4d25-b3db-400a2374ef1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188168509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2188168509
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.4097530714
Short name T618
Test name
Test status
Simulation time 7172720933 ps
CPU time 153.64 seconds
Started Jun 02 01:55:38 PM PDT 24
Finished Jun 02 01:58:12 PM PDT 24
Peak memory 247036 kb
Host smart-8a2f4d8f-6c5a-44bd-a49f-8089f8ac6542
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097530714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.4097530714
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.2749248857
Short name T608
Test name
Test status
Simulation time 622399517 ps
CPU time 10.66 seconds
Started Jun 02 01:55:38 PM PDT 24
Finished Jun 02 01:55:49 PM PDT 24
Peak memory 248688 kb
Host smart-3541426a-8be1-412b-a60c-3dcdd0a9519b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27492
48857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.2749248857
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3511980939
Short name T466
Test name
Test status
Simulation time 179965614 ps
CPU time 19.03 seconds
Started Jun 02 01:55:40 PM PDT 24
Finished Jun 02 01:55:59 PM PDT 24
Peak memory 247368 kb
Host smart-2caa188b-3431-4f5b-8ce3-c035fb6e68be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35119
80939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3511980939
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.2513401439
Short name T433
Test name
Test status
Simulation time 508441797 ps
CPU time 30.84 seconds
Started Jun 02 01:55:39 PM PDT 24
Finished Jun 02 01:56:10 PM PDT 24
Peak memory 256260 kb
Host smart-6ac9a853-1bbf-4ac6-8e15-7b9c4733dc82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25134
01439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2513401439
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2324956854
Short name T348
Test name
Test status
Simulation time 1059297633 ps
CPU time 30.16 seconds
Started Jun 02 01:55:42 PM PDT 24
Finished Jun 02 01:56:12 PM PDT 24
Peak memory 248808 kb
Host smart-d965783d-5841-44d4-988a-9f18d881fe58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23249
56854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2324956854
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.366964670
Short name T56
Test name
Test status
Simulation time 63262697109 ps
CPU time 1455.05 seconds
Started Jun 02 01:55:39 PM PDT 24
Finished Jun 02 02:19:55 PM PDT 24
Peak memory 289448 kb
Host smart-21e09803-f1b7-4a72-945c-5cca228902a4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366964670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.366964670
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.396290396
Short name T92
Test name
Test status
Simulation time 30993540620 ps
CPU time 1023.11 seconds
Started Jun 02 01:55:41 PM PDT 24
Finished Jun 02 02:12:44 PM PDT 24
Peak memory 273492 kb
Host smart-fb055542-e339-4030-b2e6-c09ba8dfa340
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396290396 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.396290396
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3823100640
Short name T577
Test name
Test status
Simulation time 26516049163 ps
CPU time 1065.89 seconds
Started Jun 02 01:55:45 PM PDT 24
Finished Jun 02 02:13:31 PM PDT 24
Peak memory 281592 kb
Host smart-7ad7cb2b-7c7d-491b-897a-3c642bfb1b16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823100640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3823100640
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.73637449
Short name T196
Test name
Test status
Simulation time 6920352311 ps
CPU time 212.79 seconds
Started Jun 02 01:55:42 PM PDT 24
Finished Jun 02 01:59:15 PM PDT 24
Peak memory 256984 kb
Host smart-289b8c8a-9d6c-4492-a773-ac14ad161c46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73637
449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.73637449
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.727297945
Short name T432
Test name
Test status
Simulation time 1049021255 ps
CPU time 21.99 seconds
Started Jun 02 01:55:39 PM PDT 24
Finished Jun 02 01:56:02 PM PDT 24
Peak memory 255924 kb
Host smart-ae441b09-4ddf-40ae-8e7b-f5867037a4de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72729
7945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.727297945
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.1417059021
Short name T321
Test name
Test status
Simulation time 365365807690 ps
CPU time 2167.38 seconds
Started Jun 02 01:55:47 PM PDT 24
Finished Jun 02 02:31:55 PM PDT 24
Peak memory 285524 kb
Host smart-f8fe2eb2-05f5-4a7e-ae78-9891c1452825
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417059021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.1417059021
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2332636273
Short name T437
Test name
Test status
Simulation time 183343408227 ps
CPU time 2994.27 seconds
Started Jun 02 01:55:44 PM PDT 24
Finished Jun 02 02:45:39 PM PDT 24
Peak memory 281548 kb
Host smart-be5368e4-6c0f-476e-b8e6-f800b01df46b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332636273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2332636273
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2303501289
Short name T309
Test name
Test status
Simulation time 25583321447 ps
CPU time 229.25 seconds
Started Jun 02 01:55:45 PM PDT 24
Finished Jun 02 01:59:35 PM PDT 24
Peak memory 248196 kb
Host smart-259b9bc3-429e-4686-8493-50287b37e628
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303501289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2303501289
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.2324050115
Short name T444
Test name
Test status
Simulation time 682405008 ps
CPU time 29.9 seconds
Started Jun 02 01:55:38 PM PDT 24
Finished Jun 02 01:56:08 PM PDT 24
Peak memory 248716 kb
Host smart-089a4abe-581d-423a-84ea-3a159b5f5857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23240
50115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.2324050115
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.1119222173
Short name T392
Test name
Test status
Simulation time 3957185816 ps
CPU time 60.37 seconds
Started Jun 02 01:55:38 PM PDT 24
Finished Jun 02 01:56:39 PM PDT 24
Peak memory 248708 kb
Host smart-dc387d33-dc4c-4b93-bf9b-f57fba0a186a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11192
22173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1119222173
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.410481496
Short name T661
Test name
Test status
Simulation time 128287775 ps
CPU time 11.4 seconds
Started Jun 02 01:55:47 PM PDT 24
Finished Jun 02 01:55:59 PM PDT 24
Peak memory 248732 kb
Host smart-ff5c21cf-d65d-442a-913d-b7f991c48211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41048
1496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.410481496
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1221857510
Short name T364
Test name
Test status
Simulation time 2225310513 ps
CPU time 28.72 seconds
Started Jun 02 01:55:40 PM PDT 24
Finished Jun 02 01:56:09 PM PDT 24
Peak memory 248968 kb
Host smart-7c8ea6a2-fd55-4796-937d-737d9fde3089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12218
57510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1221857510
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.972278046
Short name T197
Test name
Test status
Simulation time 35688866808 ps
CPU time 3499.61 seconds
Started Jun 02 01:55:47 PM PDT 24
Finished Jun 02 02:54:07 PM PDT 24
Peak memory 334400 kb
Host smart-ff19d676-3b19-4dda-b4a0-53d19212ca8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972278046 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.972278046
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.2279822743
Short name T690
Test name
Test status
Simulation time 84784706501 ps
CPU time 1541.13 seconds
Started Jun 02 01:55:54 PM PDT 24
Finished Jun 02 02:21:36 PM PDT 24
Peak memory 272932 kb
Host smart-b988298a-78e5-4c18-8478-c2aed86fab98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279822743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.2279822743
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.3544125274
Short name T506
Test name
Test status
Simulation time 7631260559 ps
CPU time 262.75 seconds
Started Jun 02 01:55:53 PM PDT 24
Finished Jun 02 02:00:16 PM PDT 24
Peak memory 256924 kb
Host smart-f205bca5-67d4-4120-8748-a39c67c63aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35441
25274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3544125274
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3216734607
Short name T485
Test name
Test status
Simulation time 1220988684 ps
CPU time 20.16 seconds
Started Jun 02 01:55:44 PM PDT 24
Finished Jun 02 01:56:05 PM PDT 24
Peak memory 255904 kb
Host smart-36a1e080-65be-41c8-8734-33c96608e136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32167
34607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3216734607
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.822932831
Short name T318
Test name
Test status
Simulation time 22611441363 ps
CPU time 1664.64 seconds
Started Jun 02 01:55:55 PM PDT 24
Finished Jun 02 02:23:40 PM PDT 24
Peak memory 289084 kb
Host smart-656985a8-aebf-42c4-b051-3b509b4a84a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822932831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.822932831
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2083960159
Short name T570
Test name
Test status
Simulation time 3219738819 ps
CPU time 125.25 seconds
Started Jun 02 01:55:52 PM PDT 24
Finished Jun 02 01:57:58 PM PDT 24
Peak memory 248176 kb
Host smart-0283620e-66a7-4201-9370-cef25649f461
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083960159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2083960159
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.2889546715
Short name T233
Test name
Test status
Simulation time 65814016 ps
CPU time 3.84 seconds
Started Jun 02 01:55:45 PM PDT 24
Finished Jun 02 01:55:49 PM PDT 24
Peak memory 240508 kb
Host smart-8ab3686b-f055-411b-a1b6-72d1d4c83d93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28895
46715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2889546715
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.1225644262
Short name T571
Test name
Test status
Simulation time 400690227 ps
CPU time 12.18 seconds
Started Jun 02 01:55:46 PM PDT 24
Finished Jun 02 01:55:58 PM PDT 24
Peak memory 253744 kb
Host smart-db108dde-ac1d-4ab7-9402-c1f3b887f032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12256
44262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.1225644262
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3223696645
Short name T44
Test name
Test status
Simulation time 1122680611 ps
CPU time 73.09 seconds
Started Jun 02 01:55:53 PM PDT 24
Finished Jun 02 01:57:06 PM PDT 24
Peak memory 255828 kb
Host smart-c5b9e5ab-719b-495d-a634-5c4b8e36f6a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32236
96645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3223696645
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1738731222
Short name T69
Test name
Test status
Simulation time 39253316 ps
CPU time 4.34 seconds
Started Jun 02 01:55:45 PM PDT 24
Finished Jun 02 01:55:50 PM PDT 24
Peak memory 240544 kb
Host smart-3bfe2139-d8da-4a4c-be24-771cea378d99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17387
31222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1738731222
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.3698296213
Short name T677
Test name
Test status
Simulation time 42949509846 ps
CPU time 273.78 seconds
Started Jun 02 01:55:55 PM PDT 24
Finished Jun 02 02:00:29 PM PDT 24
Peak memory 256924 kb
Host smart-c4465fc6-62db-4211-b00e-8a7ee632f99d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698296213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.3698296213
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.748064222
Short name T64
Test name
Test status
Simulation time 77249144508 ps
CPU time 7599.66 seconds
Started Jun 02 01:55:51 PM PDT 24
Finished Jun 02 04:02:32 PM PDT 24
Peak memory 348700 kb
Host smart-045aae75-6991-4c79-b4e5-c2f0237fad92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748064222 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.748064222
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.1415529172
Short name T588
Test name
Test status
Simulation time 5372273933 ps
CPU time 108.31 seconds
Started Jun 02 01:55:54 PM PDT 24
Finished Jun 02 01:57:42 PM PDT 24
Peak memory 249816 kb
Host smart-8db60cf2-2fc5-4df0-b2be-98d461ca3f92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14155
29172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.1415529172
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.1435395597
Short name T481
Test name
Test status
Simulation time 208956068 ps
CPU time 6.37 seconds
Started Jun 02 01:55:52 PM PDT 24
Finished Jun 02 01:55:59 PM PDT 24
Peak memory 252972 kb
Host smart-9f5c4dc8-f6ec-4c02-b37a-20f2a2bfc8c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14353
95597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.1435395597
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.2221731725
Short name T329
Test name
Test status
Simulation time 268539716720 ps
CPU time 3224.57 seconds
Started Jun 02 01:55:59 PM PDT 24
Finished Jun 02 02:49:44 PM PDT 24
Peak memory 288980 kb
Host smart-61c4aac8-78a6-43ee-8595-6181a5b18b85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221731725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.2221731725
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.398211489
Short name T684
Test name
Test status
Simulation time 231077327972 ps
CPU time 2831.33 seconds
Started Jun 02 01:55:59 PM PDT 24
Finished Jun 02 02:43:11 PM PDT 24
Peak memory 289212 kb
Host smart-5f8f4c66-3a49-402b-88fb-1de89e0ed5e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398211489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.398211489
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.317350361
Short name T604
Test name
Test status
Simulation time 17434122238 ps
CPU time 194.49 seconds
Started Jun 02 01:55:58 PM PDT 24
Finished Jun 02 01:59:13 PM PDT 24
Peak memory 247844 kb
Host smart-45dec05a-1442-47ab-bcb9-67141a6f5415
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317350361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.317350361
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.1565103581
Short name T393
Test name
Test status
Simulation time 221716919 ps
CPU time 17.26 seconds
Started Jun 02 01:55:54 PM PDT 24
Finished Jun 02 01:56:11 PM PDT 24
Peak memory 248748 kb
Host smart-69238342-0d42-4f1e-8eb7-0bfcb627a7bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15651
03581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.1565103581
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2062434938
Short name T5
Test name
Test status
Simulation time 143771071 ps
CPU time 10.36 seconds
Started Jun 02 01:55:54 PM PDT 24
Finished Jun 02 01:56:05 PM PDT 24
Peak memory 248732 kb
Host smart-addac623-049b-4014-9967-1d3be2d47c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20624
34938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2062434938
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3792574538
Short name T560
Test name
Test status
Simulation time 4213936419 ps
CPU time 41.65 seconds
Started Jun 02 01:55:52 PM PDT 24
Finished Jun 02 01:56:34 PM PDT 24
Peak memory 254376 kb
Host smart-d09e73b0-608c-4005-8a6a-f9345f650494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37925
74538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3792574538
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2415817349
Short name T91
Test name
Test status
Simulation time 248589333 ps
CPU time 19.3 seconds
Started Jun 02 01:55:53 PM PDT 24
Finished Jun 02 01:56:12 PM PDT 24
Peak memory 248728 kb
Host smart-a007a79c-9977-488e-bb7e-9d05235c4ff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24158
17349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2415817349
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1826884560
Short name T247
Test name
Test status
Simulation time 584912654221 ps
CPU time 2730.23 seconds
Started Jun 02 01:56:01 PM PDT 24
Finished Jun 02 02:41:32 PM PDT 24
Peak memory 288664 kb
Host smart-3e1f24d2-c13d-440b-a341-191c3fd3e8a0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826884560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1826884560
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.611516484
Short name T98
Test name
Test status
Simulation time 602561619353 ps
CPU time 1981.55 seconds
Started Jun 02 01:55:59 PM PDT 24
Finished Jun 02 02:29:01 PM PDT 24
Peak memory 287136 kb
Host smart-11a8bf96-80be-4e53-b474-ca53c0a9e2e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611516484 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.611516484
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3782601841
Short name T427
Test name
Test status
Simulation time 30125667560 ps
CPU time 1288.57 seconds
Started Jun 02 01:55:59 PM PDT 24
Finished Jun 02 02:17:28 PM PDT 24
Peak memory 289196 kb
Host smart-18ab4ce6-34b0-4163-92fe-c6489705b3ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782601841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3782601841
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3432357533
Short name T695
Test name
Test status
Simulation time 1388879834 ps
CPU time 118.06 seconds
Started Jun 02 01:55:59 PM PDT 24
Finished Jun 02 01:57:57 PM PDT 24
Peak memory 256912 kb
Host smart-497e8589-c037-4756-bd53-b888ba6e9a3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34323
57533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3432357533
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3149722050
Short name T2
Test name
Test status
Simulation time 642783107 ps
CPU time 27.59 seconds
Started Jun 02 01:55:58 PM PDT 24
Finished Jun 02 01:56:25 PM PDT 24
Peak memory 255864 kb
Host smart-958f19e4-b4e5-4339-b4ab-7263691b8704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31497
22050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3149722050
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1865773045
Short name T702
Test name
Test status
Simulation time 140444814352 ps
CPU time 2034.13 seconds
Started Jun 02 01:56:00 PM PDT 24
Finished Jun 02 02:29:55 PM PDT 24
Peak memory 283436 kb
Host smart-3f92db9d-ff7a-45bb-ac0e-c49531fcbf11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865773045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1865773045
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.2857418906
Short name T596
Test name
Test status
Simulation time 115966042149 ps
CPU time 1066.77 seconds
Started Jun 02 01:55:58 PM PDT 24
Finished Jun 02 02:13:45 PM PDT 24
Peak memory 281620 kb
Host smart-935581e1-8e24-443a-863b-5233195729a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857418906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2857418906
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.2482068354
Short name T286
Test name
Test status
Simulation time 20868352357 ps
CPU time 446.23 seconds
Started Jun 02 01:55:59 PM PDT 24
Finished Jun 02 02:03:25 PM PDT 24
Peak memory 248068 kb
Host smart-a8c9eb17-8d7b-40da-bc6b-179b9ab22443
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482068354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.2482068354
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.2402078588
Short name T362
Test name
Test status
Simulation time 50133215 ps
CPU time 3.4 seconds
Started Jun 02 01:55:59 PM PDT 24
Finished Jun 02 01:56:02 PM PDT 24
Peak memory 240532 kb
Host smart-714005f8-46d9-43e2-b36c-b24a2789d14c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24020
78588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2402078588
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.960712305
Short name T47
Test name
Test status
Simulation time 741253926 ps
CPU time 38.8 seconds
Started Jun 02 01:56:01 PM PDT 24
Finished Jun 02 01:56:40 PM PDT 24
Peak memory 255996 kb
Host smart-be1ec56e-7ae2-4b0d-81e6-5e1c89746edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96071
2305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.960712305
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.2357564847
Short name T674
Test name
Test status
Simulation time 116678271 ps
CPU time 9.67 seconds
Started Jun 02 01:55:59 PM PDT 24
Finished Jun 02 01:56:09 PM PDT 24
Peak memory 254288 kb
Host smart-bb35e339-1f6e-4493-84c6-971225b95f3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23575
64847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2357564847
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3494946122
Short name T217
Test name
Test status
Simulation time 3595044896 ps
CPU time 46.76 seconds
Started Jun 02 01:55:58 PM PDT 24
Finished Jun 02 01:56:45 PM PDT 24
Peak memory 248800 kb
Host smart-3e97d50d-52de-438d-84df-019752dfe819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34949
46122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3494946122
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2147182809
Short name T104
Test name
Test status
Simulation time 48774623648 ps
CPU time 1508.73 seconds
Started Jun 02 01:56:00 PM PDT 24
Finished Jun 02 02:21:09 PM PDT 24
Peak memory 273300 kb
Host smart-990b5b63-44ba-4800-ae0c-92791acdda75
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147182809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2147182809
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.95074236
Short name T575
Test name
Test status
Simulation time 42230018588 ps
CPU time 1375.75 seconds
Started Jun 02 01:56:12 PM PDT 24
Finished Jun 02 02:19:08 PM PDT 24
Peak memory 289460 kb
Host smart-a78243dc-6a38-4282-b4e6-2e9f75cbc58b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95074236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.95074236
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1680082570
Short name T673
Test name
Test status
Simulation time 24198976362 ps
CPU time 169.89 seconds
Started Jun 02 01:56:06 PM PDT 24
Finished Jun 02 01:58:56 PM PDT 24
Peak memory 256344 kb
Host smart-3251c2ae-982f-4007-83f8-966ee1f9445f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16800
82570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1680082570
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.140654564
Short name T222
Test name
Test status
Simulation time 12641007801 ps
CPU time 1110.92 seconds
Started Jun 02 01:56:11 PM PDT 24
Finished Jun 02 02:14:43 PM PDT 24
Peak memory 271332 kb
Host smart-4eb47d41-5e32-47c2-838e-d9df9d14db94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140654564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.140654564
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3427188792
Short name T374
Test name
Test status
Simulation time 4307908893 ps
CPU time 67.05 seconds
Started Jun 02 01:56:05 PM PDT 24
Finished Jun 02 01:57:12 PM PDT 24
Peak memory 248788 kb
Host smart-8ed9d894-8102-4336-add1-eb16054b8d99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34271
88792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3427188792
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1903818599
Short name T360
Test name
Test status
Simulation time 2162725619 ps
CPU time 41.77 seconds
Started Jun 02 01:56:04 PM PDT 24
Finished Jun 02 01:56:46 PM PDT 24
Peak memory 254868 kb
Host smart-47ac6949-386e-493c-aabe-145b530145f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19038
18599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1903818599
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1218380351
Short name T370
Test name
Test status
Simulation time 611619684 ps
CPU time 40.47 seconds
Started Jun 02 01:56:06 PM PDT 24
Finished Jun 02 01:56:47 PM PDT 24
Peak memory 248732 kb
Host smart-b2ca55cd-7fc0-4b4c-9194-a6627d8e3f60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12183
80351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1218380351
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2211254248
Short name T356
Test name
Test status
Simulation time 37377350065 ps
CPU time 1873.65 seconds
Started Jun 02 01:56:15 PM PDT 24
Finished Jun 02 02:27:29 PM PDT 24
Peak memory 284684 kb
Host smart-3be0fd7b-9907-4d91-b0c1-c2568b5d6789
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211254248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2211254248
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.2062520916
Short name T548
Test name
Test status
Simulation time 55879775341 ps
CPU time 1690.68 seconds
Started Jun 02 01:56:16 PM PDT 24
Finished Jun 02 02:24:27 PM PDT 24
Peak memory 272924 kb
Host smart-a7edfebb-af38-4bf4-bbd0-e8a5957d479f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062520916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.2062520916
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.3271134471
Short name T234
Test name
Test status
Simulation time 3950896130 ps
CPU time 69.55 seconds
Started Jun 02 01:56:17 PM PDT 24
Finished Jun 02 01:57:27 PM PDT 24
Peak memory 256932 kb
Host smart-093011b0-184c-473d-b6fa-64a56e06a752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32711
34471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3271134471
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.3587203069
Short name T559
Test name
Test status
Simulation time 70000526 ps
CPU time 8.19 seconds
Started Jun 02 01:56:19 PM PDT 24
Finished Jun 02 01:56:28 PM PDT 24
Peak memory 252996 kb
Host smart-16930b8d-0c1b-4cfd-9c88-99269dea2545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35872
03069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3587203069
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.4182478690
Short name T328
Test name
Test status
Simulation time 12604033358 ps
CPU time 1191.22 seconds
Started Jun 02 01:56:18 PM PDT 24
Finished Jun 02 02:16:09 PM PDT 24
Peak memory 288812 kb
Host smart-76f99096-f2cf-4bb2-86d8-86fb98096167
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182478690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.4182478690
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.814467037
Short name T508
Test name
Test status
Simulation time 740372298281 ps
CPU time 2889.3 seconds
Started Jun 02 01:56:16 PM PDT 24
Finished Jun 02 02:44:26 PM PDT 24
Peak memory 288988 kb
Host smart-92928024-a0f1-492b-89a6-794b01f5cb23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814467037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.814467037
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.201661663
Short name T627
Test name
Test status
Simulation time 10611609822 ps
CPU time 404.03 seconds
Started Jun 02 01:56:18 PM PDT 24
Finished Jun 02 02:03:03 PM PDT 24
Peak memory 247964 kb
Host smart-5524233b-196f-44a0-8450-d65db74f0e39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201661663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.201661663
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.4109636165
Short name T357
Test name
Test status
Simulation time 2280628259 ps
CPU time 41.81 seconds
Started Jun 02 01:56:18 PM PDT 24
Finished Jun 02 01:57:00 PM PDT 24
Peak memory 248764 kb
Host smart-862d5f80-4e14-4a40-ba45-a96dac9f73d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41096
36165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.4109636165
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3006246611
Short name T61
Test name
Test status
Simulation time 45362700 ps
CPU time 6.63 seconds
Started Jun 02 01:56:19 PM PDT 24
Finished Jun 02 01:56:26 PM PDT 24
Peak memory 248728 kb
Host smart-2a2951af-b2b7-430a-8827-43a88ceb0763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30062
46611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3006246611
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3862922351
Short name T489
Test name
Test status
Simulation time 2254876851 ps
CPU time 69.53 seconds
Started Jun 02 01:56:17 PM PDT 24
Finished Jun 02 01:57:27 PM PDT 24
Peak memory 256384 kb
Host smart-9943c0a2-d119-40c0-9855-db36a21909a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38629
22351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3862922351
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.627454256
Short name T526
Test name
Test status
Simulation time 350103143 ps
CPU time 34.9 seconds
Started Jun 02 01:56:12 PM PDT 24
Finished Jun 02 01:56:48 PM PDT 24
Peak memory 248748 kb
Host smart-3b71c74a-591d-46af-8ed8-8c9af7401fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62745
4256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.627454256
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3276801341
Short name T416
Test name
Test status
Simulation time 43863954380 ps
CPU time 2866.22 seconds
Started Jun 02 01:56:23 PM PDT 24
Finished Jun 02 02:44:09 PM PDT 24
Peak memory 289756 kb
Host smart-e1389593-8e93-4ba0-ba25-4fcd356031f3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276801341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3276801341
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2854429016
Short name T29
Test name
Test status
Simulation time 187878238056 ps
CPU time 2852.47 seconds
Started Jun 02 01:56:24 PM PDT 24
Finished Jun 02 02:43:57 PM PDT 24
Peak memory 281584 kb
Host smart-71bb7574-a2b1-4781-a404-0d937ba209fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854429016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2854429016
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3884157208
Short name T540
Test name
Test status
Simulation time 9126418640 ps
CPU time 244.81 seconds
Started Jun 02 01:56:23 PM PDT 24
Finished Jun 02 02:00:28 PM PDT 24
Peak memory 250000 kb
Host smart-0ecefffc-d464-489a-acd9-744a3e4ba091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38841
57208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3884157208
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3387160137
Short name T531
Test name
Test status
Simulation time 309291091 ps
CPU time 26.74 seconds
Started Jun 02 01:56:24 PM PDT 24
Finished Jun 02 01:56:51 PM PDT 24
Peak memory 256484 kb
Host smart-020ebc1f-c2e4-481a-abc7-cc442fd68bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33871
60137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3387160137
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.1533297220
Short name T317
Test name
Test status
Simulation time 76178447098 ps
CPU time 1912.28 seconds
Started Jun 02 01:56:24 PM PDT 24
Finished Jun 02 02:28:16 PM PDT 24
Peak memory 272452 kb
Host smart-d2665a09-988b-4383-826b-2d9a86fe6f43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533297220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.1533297220
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.1939261146
Short name T350
Test name
Test status
Simulation time 18708858127 ps
CPU time 1094.58 seconds
Started Jun 02 01:56:23 PM PDT 24
Finished Jun 02 02:14:38 PM PDT 24
Peak memory 281052 kb
Host smart-7fb64a29-d2b2-4145-b00d-9a1967d6054c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939261146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.1939261146
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2904537062
Short name T394
Test name
Test status
Simulation time 4009706185 ps
CPU time 36.4 seconds
Started Jun 02 01:56:22 PM PDT 24
Finished Jun 02 01:56:59 PM PDT 24
Peak memory 248780 kb
Host smart-0b75c4d6-b1a0-46ff-b662-b320486799bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29045
37062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2904537062
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2064443706
Short name T376
Test name
Test status
Simulation time 499962011 ps
CPU time 31.37 seconds
Started Jun 02 01:56:24 PM PDT 24
Finished Jun 02 01:56:56 PM PDT 24
Peak memory 248736 kb
Host smart-eff459ad-b99a-4631-b1bf-eee35e75d3cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20644
43706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2064443706
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3560638649
Short name T696
Test name
Test status
Simulation time 2056859627 ps
CPU time 17.08 seconds
Started Jun 02 01:56:23 PM PDT 24
Finished Jun 02 01:56:40 PM PDT 24
Peak memory 248944 kb
Host smart-b36b4296-e630-4534-96fa-64bebedc1249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35606
38649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3560638649
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.1098277190
Short name T523
Test name
Test status
Simulation time 785868096 ps
CPU time 20 seconds
Started Jun 02 01:56:24 PM PDT 24
Finished Jun 02 01:56:44 PM PDT 24
Peak memory 248736 kb
Host smart-822339bd-05df-4bbb-a272-97402307279d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10982
77190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1098277190
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.3897781407
Short name T113
Test name
Test status
Simulation time 26223415226 ps
CPU time 1744.21 seconds
Started Jun 02 01:56:23 PM PDT 24
Finished Jun 02 02:25:27 PM PDT 24
Peak memory 282928 kb
Host smart-6645923c-c9c5-44ac-86c4-3901450b8165
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897781407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.3897781407
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.351017197
Short name T474
Test name
Test status
Simulation time 53290470305 ps
CPU time 1242.15 seconds
Started Jun 02 01:56:35 PM PDT 24
Finished Jun 02 02:17:18 PM PDT 24
Peak memory 289280 kb
Host smart-a48c1ab3-8f4e-4c9d-be4f-fb4d9794d69a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351017197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.351017197
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3027345482
Short name T649
Test name
Test status
Simulation time 3145117816 ps
CPU time 65.52 seconds
Started Jun 02 01:56:33 PM PDT 24
Finished Jun 02 01:57:39 PM PDT 24
Peak memory 256952 kb
Host smart-e233ac4e-4eb3-4f57-b403-48bd1b58461d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30273
45482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3027345482
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.994952748
Short name T359
Test name
Test status
Simulation time 546824354 ps
CPU time 14.1 seconds
Started Jun 02 01:56:37 PM PDT 24
Finished Jun 02 01:56:51 PM PDT 24
Peak memory 248740 kb
Host smart-319140fb-877c-4f6e-8d20-bddfd364eea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99495
2748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.994952748
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.1999216908
Short name T33
Test name
Test status
Simulation time 18636167953 ps
CPU time 1265.91 seconds
Started Jun 02 01:56:34 PM PDT 24
Finished Jun 02 02:17:41 PM PDT 24
Peak memory 289028 kb
Host smart-2a0ad7bb-97de-47de-8594-2fe065460bb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999216908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1999216908
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.1704086695
Short name T291
Test name
Test status
Simulation time 21948463044 ps
CPU time 306.7 seconds
Started Jun 02 01:56:36 PM PDT 24
Finished Jun 02 02:01:43 PM PDT 24
Peak memory 247996 kb
Host smart-70299da6-5763-496e-b67a-9a2f3b39e061
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704086695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1704086695
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1070977534
Short name T269
Test name
Test status
Simulation time 2215393344 ps
CPU time 30.4 seconds
Started Jun 02 01:56:28 PM PDT 24
Finished Jun 02 01:56:59 PM PDT 24
Peak memory 248776 kb
Host smart-6067a981-d122-47fe-b7fd-acf1c60dd423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10709
77534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1070977534
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.418404328
Short name T52
Test name
Test status
Simulation time 2886812857 ps
CPU time 57.73 seconds
Started Jun 02 01:56:28 PM PDT 24
Finished Jun 02 01:57:26 PM PDT 24
Peak memory 248760 kb
Host smart-55f739a6-c822-4e16-af66-878c63085182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41840
4328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.418404328
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1114389479
Short name T404
Test name
Test status
Simulation time 111516643 ps
CPU time 12.57 seconds
Started Jun 02 01:56:36 PM PDT 24
Finished Jun 02 01:56:48 PM PDT 24
Peak memory 255428 kb
Host smart-a2b0ef03-723b-4d98-82af-4d8074d51911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11143
89479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1114389479
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.1847373982
Short name T465
Test name
Test status
Simulation time 474521490 ps
CPU time 24.65 seconds
Started Jun 02 01:56:27 PM PDT 24
Finished Jun 02 01:56:53 PM PDT 24
Peak memory 248884 kb
Host smart-1bb041cd-6e08-4817-a5c3-462763742adc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18473
73982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.1847373982
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.4236447977
Short name T57
Test name
Test status
Simulation time 125040807446 ps
CPU time 1684.53 seconds
Started Jun 02 01:56:35 PM PDT 24
Finished Jun 02 02:24:40 PM PDT 24
Peak memory 289736 kb
Host smart-ebf178c6-a39e-4cff-bf80-55f66ee54989
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236447977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.4236447977
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.3808797521
Short name T282
Test name
Test status
Simulation time 62911079140 ps
CPU time 1882.85 seconds
Started Jun 02 01:56:39 PM PDT 24
Finished Jun 02 02:28:02 PM PDT 24
Peak memory 272860 kb
Host smart-6e5597f6-519f-4058-bc19-b69cf9b46b82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808797521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.3808797521
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3371425246
Short name T565
Test name
Test status
Simulation time 9649338301 ps
CPU time 185.77 seconds
Started Jun 02 01:56:40 PM PDT 24
Finished Jun 02 01:59:47 PM PDT 24
Peak memory 249800 kb
Host smart-c014ab5b-1576-4e86-8218-6275a668298a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33714
25246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3371425246
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.1661022022
Short name T671
Test name
Test status
Simulation time 187363267 ps
CPU time 17.42 seconds
Started Jun 02 01:56:40 PM PDT 24
Finished Jun 02 01:56:58 PM PDT 24
Peak memory 249204 kb
Host smart-ebfbd0a5-74a7-48be-948f-325e824a2be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16610
22022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.1661022022
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2473284208
Short name T116
Test name
Test status
Simulation time 10701489016 ps
CPU time 989.04 seconds
Started Jun 02 01:56:37 PM PDT 24
Finished Jun 02 02:13:07 PM PDT 24
Peak memory 273412 kb
Host smart-732d6e8e-0460-49a9-98c3-bc77617307a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473284208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2473284208
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.3419146109
Short name T642
Test name
Test status
Simulation time 185407074565 ps
CPU time 503.45 seconds
Started Jun 02 01:56:41 PM PDT 24
Finished Jun 02 02:05:05 PM PDT 24
Peak memory 248300 kb
Host smart-1f920ff3-e64d-45d6-b004-6fcdc16f5718
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419146109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3419146109
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.280719088
Short name T235
Test name
Test status
Simulation time 50039579 ps
CPU time 2.72 seconds
Started Jun 02 01:56:32 PM PDT 24
Finished Jun 02 01:56:35 PM PDT 24
Peak memory 240492 kb
Host smart-fb656f41-7e76-4799-bdf1-534f1e8b8a0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28071
9088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.280719088
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.2890560611
Short name T126
Test name
Test status
Simulation time 555980766 ps
CPU time 32.74 seconds
Started Jun 02 01:56:40 PM PDT 24
Finished Jun 02 01:57:13 PM PDT 24
Peak memory 247460 kb
Host smart-9127d3f9-cf6d-49ef-aa9c-b27285096e9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28905
60611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2890560611
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3519665742
Short name T541
Test name
Test status
Simulation time 174050510 ps
CPU time 29.12 seconds
Started Jun 02 01:56:39 PM PDT 24
Finished Jun 02 01:57:09 PM PDT 24
Peak memory 247384 kb
Host smart-5cc2bc72-e7e8-44fd-9150-5e20af6c2632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35196
65742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3519665742
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.437545843
Short name T583
Test name
Test status
Simulation time 213485915 ps
CPU time 17.49 seconds
Started Jun 02 01:56:34 PM PDT 24
Finished Jun 02 01:56:51 PM PDT 24
Peak memory 256440 kb
Host smart-6eb1de9f-df6f-4510-80cb-405ac8ec1529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43754
5843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.437545843
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1085773430
Short name T115
Test name
Test status
Simulation time 33083210617 ps
CPU time 2410.22 seconds
Started Jun 02 01:56:40 PM PDT 24
Finished Jun 02 02:36:51 PM PDT 24
Peak memory 289300 kb
Host smart-9c393433-8d21-4a62-82a4-b44a9d076d9e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085773430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1085773430
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.2037043032
Short name T60
Test name
Test status
Simulation time 293112004623 ps
CPU time 4340.42 seconds
Started Jun 02 01:56:41 PM PDT 24
Finished Jun 02 03:09:02 PM PDT 24
Peak memory 321988 kb
Host smart-928c2b87-4bc4-4c1e-aaf5-513b9c779a3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037043032 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.2037043032
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2580959673
Short name T200
Test name
Test status
Simulation time 34999375 ps
CPU time 2.58 seconds
Started Jun 02 01:53:03 PM PDT 24
Finished Jun 02 01:53:06 PM PDT 24
Peak memory 248860 kb
Host smart-4ad3e5c8-dc5d-4d54-b695-106ce68c4247
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2580959673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2580959673
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1649113973
Short name T220
Test name
Test status
Simulation time 7154470196 ps
CPU time 813.28 seconds
Started Jun 02 01:53:01 PM PDT 24
Finished Jun 02 02:06:35 PM PDT 24
Peak memory 273352 kb
Host smart-b6d2139b-87a9-43ca-b14e-46f8556d5210
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649113973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1649113973
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1804961333
Short name T645
Test name
Test status
Simulation time 170956522 ps
CPU time 9.97 seconds
Started Jun 02 01:53:00 PM PDT 24
Finished Jun 02 01:53:11 PM PDT 24
Peak memory 248752 kb
Host smart-e989b4ab-fafb-4301-8fed-66fc9d7a9502
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1804961333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1804961333
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3728853141
Short name T564
Test name
Test status
Simulation time 1617870916 ps
CPU time 90.32 seconds
Started Jun 02 01:53:03 PM PDT 24
Finished Jun 02 01:54:34 PM PDT 24
Peak memory 256812 kb
Host smart-9e86d668-f846-4935-a409-ed4965d894bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37288
53141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3728853141
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2940805047
Short name T390
Test name
Test status
Simulation time 671628312 ps
CPU time 17.43 seconds
Started Jun 02 01:53:00 PM PDT 24
Finished Jun 02 01:53:18 PM PDT 24
Peak memory 255916 kb
Host smart-d5be6c0d-a481-450f-9e15-127cf776a7bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29408
05047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2940805047
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2518378920
Short name T3
Test name
Test status
Simulation time 19647032947 ps
CPU time 1026.96 seconds
Started Jun 02 01:53:04 PM PDT 24
Finished Jun 02 02:10:12 PM PDT 24
Peak memory 273344 kb
Host smart-5aab2a86-eb2b-41e6-8d9e-15bd53db3ff1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518378920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2518378920
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2689152152
Short name T507
Test name
Test status
Simulation time 55004008638 ps
CPU time 1338.32 seconds
Started Jun 02 01:53:02 PM PDT 24
Finished Jun 02 02:15:21 PM PDT 24
Peak memory 288808 kb
Host smart-4ce605bf-944d-470f-8457-953bd807781f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689152152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2689152152
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.3312651777
Short name T293
Test name
Test status
Simulation time 16805940508 ps
CPU time 324.32 seconds
Started Jun 02 01:53:01 PM PDT 24
Finished Jun 02 01:58:26 PM PDT 24
Peak memory 247056 kb
Host smart-b27202d9-a387-43d9-80f9-b44c396c5d7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312651777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3312651777
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1396961245
Short name T469
Test name
Test status
Simulation time 2341085460 ps
CPU time 41.56 seconds
Started Jun 02 01:53:02 PM PDT 24
Finished Jun 02 01:53:44 PM PDT 24
Peak memory 248804 kb
Host smart-9025adb2-1e34-469b-b185-a7a8a006638a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13969
61245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1396961245
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.1902491860
Short name T600
Test name
Test status
Simulation time 1505692868 ps
CPU time 30.05 seconds
Started Jun 02 01:53:01 PM PDT 24
Finished Jun 02 01:53:31 PM PDT 24
Peak memory 249044 kb
Host smart-04479c08-6470-4c48-b2a2-cd9cd67bec3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19024
91860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1902491860
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.775277643
Short name T268
Test name
Test status
Simulation time 542826469 ps
CPU time 27.93 seconds
Started Jun 02 01:53:00 PM PDT 24
Finished Jun 02 01:53:28 PM PDT 24
Peak memory 256660 kb
Host smart-e770831a-e93e-4c0f-83da-11d144dc5ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77527
7643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.775277643
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2889452947
Short name T349
Test name
Test status
Simulation time 721234346 ps
CPU time 49.18 seconds
Started Jun 02 01:53:02 PM PDT 24
Finished Jun 02 01:53:52 PM PDT 24
Peak memory 255792 kb
Host smart-087699ac-3526-4381-b91f-0e3cb6187fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28894
52947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2889452947
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.4063176907
Short name T278
Test name
Test status
Simulation time 16633802190 ps
CPU time 1601.47 seconds
Started Jun 02 01:53:02 PM PDT 24
Finished Jun 02 02:19:44 PM PDT 24
Peak memory 300004 kb
Host smart-629a944d-80c6-4ffe-87bb-d4f5da5cc0fc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063176907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.4063176907
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.3189145960
Short name T66
Test name
Test status
Simulation time 22804170515 ps
CPU time 1365.26 seconds
Started Jun 02 01:53:04 PM PDT 24
Finished Jun 02 02:15:50 PM PDT 24
Peak memory 284380 kb
Host smart-4fe1a6e2-8b0d-4e0c-b902-a3d529cf8f12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189145960 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.3189145960
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.3431068429
Short name T206
Test name
Test status
Simulation time 14337927 ps
CPU time 2.98 seconds
Started Jun 02 01:53:05 PM PDT 24
Finished Jun 02 01:53:09 PM PDT 24
Peak memory 248868 kb
Host smart-e24d2639-969e-412e-b60f-99d6205046ea
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3431068429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3431068429
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.3294114094
Short name T609
Test name
Test status
Simulation time 83405384489 ps
CPU time 1543.61 seconds
Started Jun 02 01:53:07 PM PDT 24
Finished Jun 02 02:18:51 PM PDT 24
Peak memory 269572 kb
Host smart-acec586b-c487-4cc4-bf95-84147c63207c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294114094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3294114094
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.785573290
Short name T572
Test name
Test status
Simulation time 828967528 ps
CPU time 12.59 seconds
Started Jun 02 01:53:06 PM PDT 24
Finished Jun 02 01:53:18 PM PDT 24
Peak memory 248720 kb
Host smart-13ff6806-634f-41c9-8341-6e238ce8d7d2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=785573290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.785573290
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.3316272730
Short name T415
Test name
Test status
Simulation time 14597254325 ps
CPU time 243.21 seconds
Started Jun 02 01:53:12 PM PDT 24
Finished Jun 02 01:57:16 PM PDT 24
Peak memory 250236 kb
Host smart-0a75eaf7-b9be-46fb-a951-8dcd4310bc44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33162
72730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3316272730
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.3129412630
Short name T460
Test name
Test status
Simulation time 346387709 ps
CPU time 24.47 seconds
Started Jun 02 01:53:06 PM PDT 24
Finished Jun 02 01:53:31 PM PDT 24
Peak memory 253920 kb
Host smart-39d9b72f-dd55-4154-9edd-cca84f252e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31294
12630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3129412630
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2031380706
Short name T324
Test name
Test status
Simulation time 61125516908 ps
CPU time 3436.25 seconds
Started Jun 02 01:53:10 PM PDT 24
Finished Jun 02 02:50:27 PM PDT 24
Peak memory 288512 kb
Host smart-57fff9ce-24a8-4c0b-a303-cb1a59061773
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031380706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2031380706
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.737633284
Short name T35
Test name
Test status
Simulation time 91354258061 ps
CPU time 1443.48 seconds
Started Jun 02 01:53:06 PM PDT 24
Finished Jun 02 02:17:10 PM PDT 24
Peak memory 273336 kb
Host smart-18dd7d19-5b14-40a6-bd8a-f1cf55cc557c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737633284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.737633284
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1575178657
Short name T648
Test name
Test status
Simulation time 17706718506 ps
CPU time 192.41 seconds
Started Jun 02 01:53:04 PM PDT 24
Finished Jun 02 01:56:16 PM PDT 24
Peak memory 247792 kb
Host smart-89de66d5-d07c-4b07-ba22-b37cf93feab5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575178657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1575178657
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3342965139
Short name T192
Test name
Test status
Simulation time 510255999 ps
CPU time 15.79 seconds
Started Jun 02 01:53:08 PM PDT 24
Finished Jun 02 01:53:24 PM PDT 24
Peak memory 248744 kb
Host smart-df22f989-eacf-485b-a535-9742e54f160e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33429
65139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3342965139
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1789098806
Short name T529
Test name
Test status
Simulation time 304930582 ps
CPU time 25.99 seconds
Started Jun 02 01:53:07 PM PDT 24
Finished Jun 02 01:53:34 PM PDT 24
Peak memory 254860 kb
Host smart-52e5d602-d88e-4ef0-9769-2f93fbf1ccf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17890
98806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1789098806
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.3080670030
Short name T114
Test name
Test status
Simulation time 1438823438 ps
CPU time 49.67 seconds
Started Jun 02 01:53:08 PM PDT 24
Finished Jun 02 01:53:58 PM PDT 24
Peak memory 248700 kb
Host smart-38029484-a52a-4e1f-8e46-2dfe8b5766ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30806
70030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.3080670030
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.2514584185
Short name T236
Test name
Test status
Simulation time 632662461 ps
CPU time 38.19 seconds
Started Jun 02 01:53:01 PM PDT 24
Finished Jun 02 01:53:40 PM PDT 24
Peak memory 248816 kb
Host smart-22574893-2a72-4f74-91cd-3fd2f81be650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25145
84185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2514584185
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2066397751
Short name T242
Test name
Test status
Simulation time 41146558465 ps
CPU time 597.1 seconds
Started Jun 02 01:53:10 PM PDT 24
Finished Jun 02 02:03:07 PM PDT 24
Peak memory 256332 kb
Host smart-74c20f86-57e9-4603-8bc6-ab3eb815b792
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066397751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.2066397751
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.204946074
Short name T419
Test name
Test status
Simulation time 214055588212 ps
CPU time 9485.87 seconds
Started Jun 02 01:53:07 PM PDT 24
Finished Jun 02 04:31:14 PM PDT 24
Peak memory 354392 kb
Host smart-00a4bd25-ed05-486b-9524-17c1f8b748d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204946074 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.204946074
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.2213442848
Short name T216
Test name
Test status
Simulation time 130293080 ps
CPU time 3.28 seconds
Started Jun 02 01:53:12 PM PDT 24
Finished Jun 02 01:53:15 PM PDT 24
Peak memory 248900 kb
Host smart-dcaab456-5f39-41fd-9b72-68476498f2b2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2213442848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2213442848
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1032546704
Short name T605
Test name
Test status
Simulation time 9838895223 ps
CPU time 899.9 seconds
Started Jun 02 01:53:07 PM PDT 24
Finished Jun 02 02:08:07 PM PDT 24
Peak memory 272884 kb
Host smart-417e1d5f-d39d-43ed-b0cf-5ee519c7e373
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032546704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1032546704
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2979598023
Short name T644
Test name
Test status
Simulation time 430382116 ps
CPU time 8.08 seconds
Started Jun 02 01:53:11 PM PDT 24
Finished Jun 02 01:53:19 PM PDT 24
Peak memory 248748 kb
Host smart-e6e70d6d-f062-455a-bd2e-1e9732636b27
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2979598023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2979598023
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.1151866469
Short name T536
Test name
Test status
Simulation time 1948213030 ps
CPU time 71.24 seconds
Started Jun 02 01:53:09 PM PDT 24
Finished Jun 02 01:54:20 PM PDT 24
Peak memory 248688 kb
Host smart-a94d0b84-c667-4e15-8c36-6355ef6b50ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11518
66469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1151866469
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.1677983564
Short name T400
Test name
Test status
Simulation time 33257747 ps
CPU time 4.8 seconds
Started Jun 02 01:53:09 PM PDT 24
Finished Jun 02 01:53:14 PM PDT 24
Peak memory 240564 kb
Host smart-db2b90dc-981e-4d7e-8211-c2856c401a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16779
83564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.1677983564
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3807966200
Short name T303
Test name
Test status
Simulation time 66541445150 ps
CPU time 1548.66 seconds
Started Jun 02 01:53:06 PM PDT 24
Finished Jun 02 02:18:55 PM PDT 24
Peak memory 273344 kb
Host smart-6a77431a-28da-4060-9305-5c7c98e48317
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807966200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3807966200
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.697841483
Short name T4
Test name
Test status
Simulation time 44945599579 ps
CPU time 1317.29 seconds
Started Jun 02 01:53:15 PM PDT 24
Finished Jun 02 02:15:13 PM PDT 24
Peak memory 272672 kb
Host smart-c2ad24f9-a473-4b53-b408-8cb396b57f35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697841483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.697841483
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.3865433385
Short name T495
Test name
Test status
Simulation time 38597819910 ps
CPU time 331.93 seconds
Started Jun 02 01:53:07 PM PDT 24
Finished Jun 02 01:58:39 PM PDT 24
Peak memory 256500 kb
Host smart-0715ca68-acbf-4c32-a9fe-27dc2bdd9420
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865433385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3865433385
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3007287372
Short name T471
Test name
Test status
Simulation time 579410679 ps
CPU time 19.4 seconds
Started Jun 02 01:53:05 PM PDT 24
Finished Jun 02 01:53:25 PM PDT 24
Peak memory 256008 kb
Host smart-b277ea3d-c57a-41a8-acfb-2f7b2e41efb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30072
87372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3007287372
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3940408988
Short name T277
Test name
Test status
Simulation time 937884423 ps
CPU time 55.85 seconds
Started Jun 02 01:53:06 PM PDT 24
Finished Jun 02 01:54:03 PM PDT 24
Peak memory 247732 kb
Host smart-1de8c574-76b9-4c31-945e-5d7f2f66ad24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39404
08988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3940408988
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.680555225
Short name T654
Test name
Test status
Simulation time 1081105268 ps
CPU time 19.67 seconds
Started Jun 02 01:53:09 PM PDT 24
Finished Jun 02 01:53:28 PM PDT 24
Peak memory 255064 kb
Host smart-5f9684bb-800f-4da9-bfb7-90334ff68d52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68055
5225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.680555225
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.3127846921
Short name T418
Test name
Test status
Simulation time 411042108 ps
CPU time 47.2 seconds
Started Jun 02 01:53:06 PM PDT 24
Finished Jun 02 01:53:53 PM PDT 24
Peak memory 256680 kb
Host smart-07c62573-3198-4422-8028-c2e6c3130601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31278
46921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3127846921
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1741394455
Short name T387
Test name
Test status
Simulation time 11869064577 ps
CPU time 514.42 seconds
Started Jun 02 01:53:10 PM PDT 24
Finished Jun 02 02:01:45 PM PDT 24
Peak memory 256928 kb
Host smart-9548f001-8388-41d6-9a3e-5853eb8a8dd8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741394455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1741394455
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.1478777901
Short name T53
Test name
Test status
Simulation time 274280242673 ps
CPU time 6250.47 seconds
Started Jun 02 01:53:12 PM PDT 24
Finished Jun 02 03:37:24 PM PDT 24
Peak memory 352756 kb
Host smart-787a703f-35ae-494a-b408-b74c85f50d03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478777901 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.1478777901
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1944024564
Short name T209
Test name
Test status
Simulation time 66168202 ps
CPU time 3.5 seconds
Started Jun 02 01:53:11 PM PDT 24
Finished Jun 02 01:53:15 PM PDT 24
Peak memory 248872 kb
Host smart-7acde426-7434-426c-b0b6-7f25e16e6147
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1944024564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1944024564
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2740405101
Short name T668
Test name
Test status
Simulation time 200628814311 ps
CPU time 3160.43 seconds
Started Jun 02 01:53:14 PM PDT 24
Finished Jun 02 02:45:55 PM PDT 24
Peak memory 288432 kb
Host smart-0f741d18-7814-4dc4-8df1-8b6e79ef2188
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740405101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2740405101
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.3227706486
Short name T482
Test name
Test status
Simulation time 674093165 ps
CPU time 27.9 seconds
Started Jun 02 01:53:14 PM PDT 24
Finished Jun 02 01:53:42 PM PDT 24
Peak memory 240548 kb
Host smart-978a0b04-5271-4f8b-85f3-e15aaa9ecfb9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3227706486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3227706486
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.106397465
Short name T188
Test name
Test status
Simulation time 541975764 ps
CPU time 28.73 seconds
Started Jun 02 01:53:10 PM PDT 24
Finished Jun 02 01:53:39 PM PDT 24
Peak memory 248720 kb
Host smart-9edfe772-97a7-42e0-9be1-3172a93c2289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10639
7465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.106397465
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.542982798
Short name T243
Test name
Test status
Simulation time 821906874 ps
CPU time 10.28 seconds
Started Jun 02 01:53:12 PM PDT 24
Finished Jun 02 01:53:22 PM PDT 24
Peak memory 253668 kb
Host smart-b5f752ec-6841-4a25-95ac-1af94f9f4e9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54298
2798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.542982798
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1838547476
Short name T396
Test name
Test status
Simulation time 77458510253 ps
CPU time 1265.94 seconds
Started Jun 02 01:53:12 PM PDT 24
Finished Jun 02 02:14:19 PM PDT 24
Peak memory 273356 kb
Host smart-6afe3834-7cbd-427f-99aa-e9f02e98803f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838547476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1838547476
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1348909000
Short name T298
Test name
Test status
Simulation time 6720637640 ps
CPU time 288.32 seconds
Started Jun 02 01:53:14 PM PDT 24
Finished Jun 02 01:58:03 PM PDT 24
Peak memory 248220 kb
Host smart-9b1aa661-45bb-45b7-a1d9-389c5930f068
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348909000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1348909000
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.2618351743
Short name T93
Test name
Test status
Simulation time 3487260408 ps
CPU time 46.36 seconds
Started Jun 02 01:53:11 PM PDT 24
Finished Jun 02 01:53:58 PM PDT 24
Peak memory 248784 kb
Host smart-50573bb4-2df3-4e64-a329-7a0d1c24735f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26183
51743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2618351743
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2506183631
Short name T490
Test name
Test status
Simulation time 432507569 ps
CPU time 23.73 seconds
Started Jun 02 01:53:14 PM PDT 24
Finished Jun 02 01:53:38 PM PDT 24
Peak memory 247412 kb
Host smart-26920cdc-6e48-43e5-bcd8-021fe8e1a7af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25061
83631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2506183631
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.303383000
Short name T646
Test name
Test status
Simulation time 965850453 ps
CPU time 59.97 seconds
Started Jun 02 01:53:12 PM PDT 24
Finished Jun 02 01:54:12 PM PDT 24
Peak memory 248836 kb
Host smart-6b2f64bb-5e4b-47aa-b292-bf9ebc601e35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30338
3000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.303383000
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.282558631
Short name T431
Test name
Test status
Simulation time 2582840193 ps
CPU time 37.2 seconds
Started Jun 02 01:53:11 PM PDT 24
Finished Jun 02 01:53:48 PM PDT 24
Peak memory 248848 kb
Host smart-d7984a06-93bd-46a4-bc3d-0cd4acc80856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28255
8631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.282558631
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.1864315373
Short name T658
Test name
Test status
Simulation time 342001692468 ps
CPU time 8387.48 seconds
Started Jun 02 01:53:12 PM PDT 24
Finished Jun 02 04:13:01 PM PDT 24
Peak memory 355248 kb
Host smart-fafb387c-cd8b-4b2e-a7ae-6fce696574b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864315373 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.1864315373
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.4186712196
Short name T22
Test name
Test status
Simulation time 17944229 ps
CPU time 2.74 seconds
Started Jun 02 01:53:18 PM PDT 24
Finished Jun 02 01:53:22 PM PDT 24
Peak memory 248884 kb
Host smart-f3619faa-3f14-4f50-8e6f-b31186a45edd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4186712196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.4186712196
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1694349558
Short name T73
Test name
Test status
Simulation time 34204384941 ps
CPU time 2207 seconds
Started Jun 02 01:53:12 PM PDT 24
Finished Jun 02 02:29:59 PM PDT 24
Peak memory 288420 kb
Host smart-24e8f190-b7df-4756-b7be-97ad06da9478
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694349558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1694349558
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.3185531776
Short name T491
Test name
Test status
Simulation time 593590623 ps
CPU time 9.56 seconds
Started Jun 02 01:53:21 PM PDT 24
Finished Jun 02 01:53:31 PM PDT 24
Peak memory 240556 kb
Host smart-d54cf861-af69-43e6-96e2-de2fa0a54cd3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3185531776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3185531776
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3057635435
Short name T687
Test name
Test status
Simulation time 1440527955 ps
CPU time 61.78 seconds
Started Jun 02 01:53:14 PM PDT 24
Finished Jun 02 01:54:16 PM PDT 24
Peak memory 256868 kb
Host smart-73038318-0ca7-4447-9da9-15d39c9927b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30576
35435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3057635435
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.653817863
Short name T385
Test name
Test status
Simulation time 3066360570 ps
CPU time 52.71 seconds
Started Jun 02 01:53:11 PM PDT 24
Finished Jun 02 01:54:05 PM PDT 24
Peak memory 248800 kb
Host smart-c81111b1-70a8-401a-be26-854c8336201a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65381
7863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.653817863
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3164723609
Short name T607
Test name
Test status
Simulation time 144254847594 ps
CPU time 1989.77 seconds
Started Jun 02 01:53:12 PM PDT 24
Finished Jun 02 02:26:23 PM PDT 24
Peak memory 273368 kb
Host smart-a8492067-82b0-43d3-87a6-4011b47c8edf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164723609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3164723609
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.2360176672
Short name T601
Test name
Test status
Simulation time 10894581787 ps
CPU time 422.1 seconds
Started Jun 02 01:53:13 PM PDT 24
Finished Jun 02 02:00:15 PM PDT 24
Peak memory 248180 kb
Host smart-2ca4dfdb-906d-497a-81f4-d6bf71db1a36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360176672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.2360176672
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3643238371
Short name T515
Test name
Test status
Simulation time 1015643246 ps
CPU time 29.03 seconds
Started Jun 02 01:53:13 PM PDT 24
Finished Jun 02 01:53:43 PM PDT 24
Peak memory 248688 kb
Host smart-eb46c78f-dd21-4968-bb81-30a6071e967e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36432
38371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3643238371
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.36298995
Short name T631
Test name
Test status
Simulation time 281798546 ps
CPU time 21.21 seconds
Started Jun 02 01:53:14 PM PDT 24
Finished Jun 02 01:53:36 PM PDT 24
Peak memory 253108 kb
Host smart-f2a0efd0-f97e-4a58-9a2b-7bb3e94b3257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36298
995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.36298995
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.2147396402
Short name T569
Test name
Test status
Simulation time 3785661639 ps
CPU time 54.29 seconds
Started Jun 02 01:53:12 PM PDT 24
Finished Jun 02 01:54:07 PM PDT 24
Peak memory 249224 kb
Host smart-ef4f15e6-3ec5-4b4a-b4a4-2e72a2eea33b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21473
96402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2147396402
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.3919570604
Short name T380
Test name
Test status
Simulation time 52746150 ps
CPU time 5.5 seconds
Started Jun 02 01:53:13 PM PDT 24
Finished Jun 02 01:53:19 PM PDT 24
Peak memory 248728 kb
Host smart-fae3c737-6bdd-4309-8f4b-b11ef821f58a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39195
70604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3919570604
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1023739632
Short name T255
Test name
Test status
Simulation time 23703435447 ps
CPU time 1952.16 seconds
Started Jun 02 01:53:20 PM PDT 24
Finished Jun 02 02:25:52 PM PDT 24
Peak memory 305472 kb
Host smart-5150097e-edd2-4789-8fe0-faeec8d93093
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023739632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1023739632
Directory /workspace/9.alert_handler_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%