Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	68793972	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

33463198

1

T1

2333

T2

283973

T3

4002

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	15330395	1			T1	899		T2	108190		T3	1728
values[0x0]	42214727	1			T1	3304		T2	324197		T3	5550
values[0x1]	44712048	1			T1	3072		T2	388711		T3	5578

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	58554664	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

43702506

1

T1

2942

T2

389421

T3

5048

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	581729	1			T1	29		T2	3170		T3	50
valid_sources[0x01]	320748	1			T1	23		T2	3326		T3	49
valid_sources[0x02]	310689	1			T1	30		T2	3318		T3	40
valid_sources[0x03]	318323	1			T1	36		T2	3177		T3	42
valid_sources[0x04]	326675	1			T1	25		T2	3444		T3	58
valid_sources[0x05]	313093	1			T1	31		T2	3149		T3	68
valid_sources[0x06]	316304	1			T1	38		T2	3404		T3	54
valid_sources[0x07]	309625	1			T1	25		T2	3165		T3	39
valid_sources[0x08]	315028	1			T1	32		T2	3317		T3	50
valid_sources[0x09]	314303	1			T1	28		T2	3248		T3	48
valid_sources[0x0a]	314998	1			T1	32		T2	3289		T3	38
valid_sources[0x0b]	310328	1			T1	37		T2	3215		T3	48
valid_sources[0x0c]	309507	1			T1	44		T2	3177		T3	42
valid_sources[0x0d]	793435	1			T1	28		T2	2979		T3	55
valid_sources[0x0e]	311305	1			T1	32		T2	3026		T3	36
valid_sources[0x0f]	310944	1			T1	32		T2	3141		T3	49
valid_sources[0x10]	304647	1			T1	29		T2	3160		T3	48
valid_sources[0x11]	948111	1			T1	42		T2	3086		T3	42
valid_sources[0x12]	312751	1			T1	23		T2	3075		T3	64
valid_sources[0x13]	738780	1			T1	38		T2	3195		T3	54
valid_sources[0x14]	323918	1			T1	21		T2	3219		T3	38
valid_sources[0x15]	316776	1			T1	36		T2	3264		T3	36
valid_sources[0x16]	320832	1			T1	34		T2	3380		T3	51
valid_sources[0x17]	964925	1			T1	23		T2	3144		T3	43
valid_sources[0x18]	311561	1			T1	37		T2	3232		T3	45
valid_sources[0x19]	329419	1			T1	24		T2	3029		T3	50
valid_sources[0x1a]	310381	1			T1	21		T2	3513		T3	55
valid_sources[0x1b]	1186425	1			T1	37		T2	3238		T3	51
valid_sources[0x1c]	310021	1			T1	32		T2	3188		T3	64
valid_sources[0x1d]	324478	1			T1	22		T2	3264		T3	61
valid_sources[0x1e]	318875	1			T1	29		T2	3176		T3	40
valid_sources[0x1f]	315220	1			T1	27		T2	3151		T3	54
valid_sources[0x20]	651207	1			T1	35		T2	3326		T3	54
valid_sources[0x21]	312105	1			T1	32		T2	3016		T3	55
valid_sources[0x22]	319267	1			T1	23		T2	3051		T3	46
valid_sources[0x23]	313327	1			T1	36		T2	3223		T3	50
valid_sources[0x24]	315428	1			T1	18		T2	3051		T3	48
valid_sources[0x25]	305398	1			T1	38		T2	3000		T3	51
valid_sources[0x26]	325454	1			T1	34		T2	3161		T3	44
valid_sources[0x27]	305091	1			T1	30		T2	3424		T3	55
valid_sources[0x28]	326697	1			T1	33		T2	3315		T3	43
valid_sources[0x29]	313176	1			T1	34		T2	3066		T3	62
valid_sources[0x2a]	506248	1			T1	26		T2	3447		T3	53
valid_sources[0x2b]	317711	1			T1	27		T2	3389		T3	46
valid_sources[0x2c]	335976	1			T1	42		T2	3280		T3	50
valid_sources[0x2d]	671349	1			T1	22		T2	3301		T3	54
valid_sources[0x2e]	309040	1			T1	28		T2	3231		T3	54
valid_sources[0x2f]	315324	1			T1	35		T2	3395		T3	51
valid_sources[0x30]	319430	1			T1	25		T2	3309		T3	57
valid_sources[0x31]	577602	1			T1	22		T2	3342		T3	51
valid_sources[0x32]	322480	1			T1	25		T2	3331		T3	52
valid_sources[0x33]	320638	1			T1	23		T2	3054		T3	43
valid_sources[0x34]	726665	1			T1	23		T2	3261		T3	61
valid_sources[0x35]	342377	1			T1	24		T2	3226		T3	50
valid_sources[0x36]	326430	1			T1	25		T2	3146		T3	47
valid_sources[0x37]	312064	1			T1	21		T2	3107		T3	34
valid_sources[0x38]	323630	1			T1	22		T2	3328		T3	44
valid_sources[0x39]	316650	1			T1	24		T2	3180		T3	48
valid_sources[0x3a]	327971	1			T1	35		T2	3384		T3	44
valid_sources[0x3b]	326637	1			T1	29		T2	3131		T3	50
valid_sources[0x3c]	313753	1			T1	20		T2	2992		T3	56
valid_sources[0x3d]	308996	1			T1	23		T2	3152		T3	50
valid_sources[0x3e]	321814	1			T1	31		T2	3145		T3	52
valid_sources[0x3f]	312916	1			T1	27		T2	2990		T3	46
valid_sources[0x40]	321641	1			T1	27		T2	3600		T3	36
valid_sources[0x41]	613995	1			T1	32		T2	3301		T3	36
valid_sources[0x42]	312532	1			T1	28		T2	3135		T3	63
valid_sources[0x43]	314089	1			T1	26		T2	3295		T3	53
valid_sources[0x44]	321778	1			T1	28		T2	2996		T3	59
valid_sources[0x45]	315478	1			T1	28		T2	3298		T3	51
valid_sources[0x46]	630972	1			T1	29		T2	3326		T3	54
valid_sources[0x47]	317418	1			T1	29		T2	3155		T3	37
valid_sources[0x48]	312942	1			T1	38		T2	3013		T3	48
valid_sources[0x49]	315444	1			T1	26		T2	3003		T3	54
valid_sources[0x4a]	315261	1			T1	30		T2	3306		T3	37
valid_sources[0x4b]	324447	1			T1	28		T2	3224		T3	48
valid_sources[0x4c]	317951	1			T1	24		T2	3131		T3	55
valid_sources[0x4d]	318453	1			T1	30		T2	3219		T3	48
valid_sources[0x4e]	317011	1			T1	26		T2	2934		T3	42
valid_sources[0x4f]	320543	1			T1	21		T2	3385		T3	55
valid_sources[0x50]	326626	1			T1	26		T2	3096		T3	52
valid_sources[0x51]	731466	1			T1	21		T2	3180		T3	43
valid_sources[0x52]	710910	1			T1	30		T2	3352		T3	48
valid_sources[0x53]	324327	1			T1	30		T2	3027		T3	67
valid_sources[0x54]	318902	1			T1	33		T2	3045		T3	50
valid_sources[0x55]	312878	1			T1	29		T2	3222		T3	49
valid_sources[0x56]	307566	1			T1	35		T2	3146		T3	49
valid_sources[0x57]	314207	1			T1	39		T2	3144		T3	50
valid_sources[0x58]	310742	1			T1	28		T2	3143		T3	47
valid_sources[0x59]	318845	1			T1	31		T2	3192		T3	65
valid_sources[0x5a]	739670	1			T1	29		T2	3148		T3	47
valid_sources[0x5b]	316661	1			T1	29		T2	3056		T3	48
valid_sources[0x5c]	314638	1			T1	21		T2	3052		T3	51
valid_sources[0x5d]	311883	1			T1	19		T2	2995		T3	68
valid_sources[0x5e]	307934	1			T1	37		T2	3261		T3	54
valid_sources[0x5f]	786880	1			T1	21		T2	3124		T3	48
valid_sources[0x60]	323879	1			T1	32		T2	3147		T3	53
valid_sources[0x61]	320642	1			T1	29		T2	3062		T3	57
valid_sources[0x62]	327671	1			T1	25		T2	3274		T3	44
valid_sources[0x63]	312513	1			T1	25		T2	3208		T3	44
valid_sources[0x64]	313241	1			T1	20		T2	3324		T3	39
valid_sources[0x65]	1180883	1			T1	40		T2	3227		T3	45
valid_sources[0x66]	318233	1			T1	36		T2	3442		T3	34
valid_sources[0x67]	313514	1			T1	34		T2	3327		T3	46
valid_sources[0x68]	729811	1			T1	14		T2	3187		T3	51
valid_sources[0x69]	312253	1			T1	33		T2	3225		T3	34
valid_sources[0x6a]	308482	1			T1	38		T2	2917		T3	62
valid_sources[0x6b]	315019	1			T1	27		T2	3102		T3	51
valid_sources[0x6c]	316453	1			T1	21		T2	3326		T3	50
valid_sources[0x6d]	680912	1			T1	27		T2	3279		T3	49
valid_sources[0x6e]	326205	1			T1	23		T2	3265		T3	45
valid_sources[0x6f]	318936	1			T1	32		T2	3255		T3	50
valid_sources[0x70]	324698	1			T1	25		T2	3296		T3	56
valid_sources[0x71]	315621	1			T1	29		T2	3216		T3	48
valid_sources[0x72]	321657	1			T1	32		T2	3345		T3	50
valid_sources[0x73]	694001	1			T1	31		T2	3303		T3	43
valid_sources[0x74]	313874	1			T1	19		T2	3280		T3	47
valid_sources[0x75]	321818	1			T1	33		T2	3275		T3	34
valid_sources[0x76]	312623	1			T1	31		T2	3223		T3	60
valid_sources[0x77]	318343	1			T1	19		T2	3200		T3	48
valid_sources[0x78]	320250	1			T1	28		T2	3112		T3	43
valid_sources[0x79]	313510	1			T1	27		T2	3192		T3	47
valid_sources[0x7a]	306955	1			T1	34		T2	3213		T3	52
valid_sources[0x7b]	323509	1			T1	19		T2	3186		T3	70
valid_sources[0x7c]	307776	1			T1	32		T2	3281		T3	48
valid_sources[0x7d]	550157	1			T1	35		T2	3240		T3	53
valid_sources[0x7e]	316831	1			T1	23		T2	3043		T3	47
valid_sources[0x7f]	790601	1			T1	20		T2	3297		T3	41
valid_sources[0x80]	316467	1			T1	30		T2	3183		T3	44

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7677928

1

T1

421

T2

61711

T3

852

values[0x0]

all_enables

biggest_size

16244858

1

T1

1252

T2

135553

T3

2025

values[0x1]

all_enables

biggest_size

9540412

1

T1

660

T2

86709

T3

1125