Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T41,T67
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	15376	0	0
DisabledNoTrigBkwd_A	2147483647	826097	0	0
DisabledNoTrigFwd_A	2147483647	1708925392	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15376	0	0
T8	795526	0	0	0
T12	383750	0	0	0
T13	151770	0	0	0
T14	369395	0	0	0
T15	0	303	0	0
T24	191752	0	0	0
T41	2819	644	0	0
T42	58167	0	0	0
T43	23895	0	0	0
T44	67731	0	0	0
T45	492771	0	0	0
T67	1148	321	0	0
T196	0	269	0	0
T197	0	848	0	0
T198	0	1086	0	0
T199	0	555	0	0
T200	0	346	0	0
T201	3601	1190	0	0
T202	3873	1254	0	0
T203	0	171	0	0
T204	0	552	0	0
T205	0	920	0	0
T206	0	1531	0	0
T207	0	718	0	0
T208	0	1446	0	0
T209	0	1135	0	0
T210	0	987	0	0
T211	0	492	0	0
T212	0	608	0	0
T213	754047	0	0	0
T214	32139	0	0	0
T215	69675	0	0	0
T216	538240	0	0	0
T217	26534	0	0	0
T218	75857	0	0	0
T219	39801	0	0	0
T220	190064	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	826097	0	0
T2	1351772	6819	0	0
T3	3766260	8	0	0
T4	2183888	0	0	0
T5	639820	4247	0	0
T6	1071240	1	0	0
T7	555248	2008	0	0
T12	0	9592	0	0
T13	0	5924	0	0
T15	14392	2	0	0
T16	24600	0	0	0
T17	1626828	380	0	0
T18	281784	586	0	0
T24	0	42	0	0
T27	0	1264	0	0
T41	0	2	0	0
T42	0	69	0	0
T43	0	111	0	0
T44	0	42	0	0
T45	0	5283	0	0
T46	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1708925392	0	0
T1	353548	342227	0	0
T2	1351772	734415	0	0
T3	3766260	1116228	0	0
T4	2183888	1092962	0	0
T5	639820	324256	0	0
T6	1071240	843035	0	0
T7	555248	464460	0	0
T15	14392	12779	0	0
T16	24600	20894	0	0
T17	1626828	865521	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T7,T16

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T201,T210,T211
1	1	Covered	T2,T7,T16

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T18

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	734617330	2669	0	0
DisabledNoTrigBkwd_A	734617330	277869	0	0
DisabledNoTrigFwd_A	734617330	377037703	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	2669	0	0
T201	3601	1190	0	0
T202	3873	0	0	0
T210	0	987	0	0
T211	0	492	0	0
T213	754047	0	0	0
T214	32139	0	0	0
T215	69675	0	0	0
T216	538240	0	0	0
T217	26534	0	0	0
T218	75857	0	0	0
T219	39801	0	0	0
T220	190064	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	277869	0	0
T2	337943	2643	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	4	0	0
T12	0	21	0	0
T13	0	2298	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	3	0	0
T24	0	19	0	0
T42	0	69	0	0
T43	0	111	0	0
T44	0	31	0	0
T45	0	4568	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	377037703	0	0
T1	88387	77342	0	0
T2	337943	101058	0	0
T3	941565	62830	0	0
T4	545972	543089	0	0
T5	159955	159945	0	0
T6	267810	267217	0	0
T7	138812	128619	0	0
T15	3598	3174	0	0
T16	6150	2717	0	0
T17	406707	406637	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T7,T16
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T41,T197,T198
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	734617330	8037	0	0
DisabledNoTrigBkwd_A	734617330	197175	0	0
DisabledNoTrigFwd_A	734617330	435307453	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	8037	0	0
T8	795526	0	0	0
T12	383750	0	0	0
T13	151770	0	0	0
T14	369395	0	0	0
T24	191752	0	0	0
T41	2819	644	0	0
T42	58167	0	0	0
T43	23895	0	0	0
T44	67731	0	0	0
T45	492771	0	0	0
T197	0	848	0	0
T198	0	1086	0	0
T199	0	555	0	0
T200	0	346	0	0
T202	0	1254	0	0
T203	0	171	0	0
T204	0	552	0	0
T208	0	1446	0	0
T209	0	1135	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	197175	0	0
T2	337943	12	0	0
T3	941565	1	0	0
T4	545972	0	0	0
T5	159955	2117	0	0
T6	267810	1	0	0
T7	138812	11	0	0
T12	0	1959	0	0
T13	0	1166	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	187	0	0
T18	70446	548	0	0
T41	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	435307453	0	0
T1	88387	88295	0	0
T2	337943	333453	0	0
T3	941565	74569	0	0
T4	545972	586	0	0
T5	159955	586	0	0
T6	267810	262800	0	0
T7	138812	127249	0	0
T15	3598	3188	0	0
T16	6150	6059	0	0
T17	406707	46094	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T7
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T67,T207
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	734617330	1039	0	0
DisabledNoTrigBkwd_A	734617330	175079	0	0
DisabledNoTrigFwd_A	734617330	450760982	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	1039	0	0
T47	202078	0	0	0
T67	1148	321	0	0
T68	367327	0	0	0
T69	111636	0	0	0
T70	354883	0	0	0
T71	426501	0	0	0
T72	88028	0	0	0
T79	110212	0	0	0
T196	1097	0	0	0
T207	0	718	0	0
T221	394683	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	175079	0	0
T2	337943	2265	0	0
T3	941565	7	0	0
T4	545972	0	0	0
T5	159955	2130	0	0
T6	267810	0	0	0
T7	138812	1976	0	0
T12	0	1808	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	21	0	0
T24	0	22	0	0
T27	0	1264	0	0
T45	0	53	0	0
T46	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	450760982	0	0
T1	88387	88295	0	0
T2	337943	145023	0	0
T3	941565	172930	0	0
T4	545972	3394	0	0
T5	159955	3780	0	0
T6	267810	267237	0	0
T7	138812	83088	0	0
T15	3598	3203	0	0
T16	6150	6059	0	0
T17	406707	406637	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T7

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T196,T205
1	1	Covered	T2,T3,T7

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T15

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	734617330	3631	0	0
DisabledNoTrigBkwd_A	734617330	175974	0	0
DisabledNoTrigFwd_A	734617330	445819254	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	3631	0	0
T6	267810	0	0	0
T8	795526	0	0	0
T12	383750	0	0	0
T15	3598	303	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	0	0	0
T41	2819	0	0	0
T42	58167	0	0	0
T43	23895	0	0	0
T196	0	269	0	0
T205	0	920	0	0
T206	0	1531	0	0
T212	0	608	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	175974	0	0
T2	337943	1899	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	17	0	0
T12	0	5804	0	0
T13	0	2460	0	0
T15	3598	2	0	0
T16	6150	0	0	0
T17	406707	193	0	0
T18	70446	14	0	0
T24	0	1	0	0
T44	0	11	0	0
T45	0	662	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	445819254	0	0
T1	88387	88295	0	0
T2	337943	154881	0	0
T3	941565	805899	0	0
T4	545972	545893	0	0
T5	159955	159945	0	0
T6	267810	45781	0	0
T7	138812	125504	0	0
T15	3598	3214	0	0
T16	6150	6059	0	0
T17	406707	6153	0	0