Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.56	100.00	97.78		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.56	100.00	97.78		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.63	100.00	97.78	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T19,T20
1	1	1	Covered	T2,T3,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T16
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T1,T2,T7
1	1	1	Covered	T2,T7,T16

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T16
0	1	Covered	T2,T7,T16
1	0	Covered	T2,T18,T21

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T16
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T18,T21

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T16
1	0	Covered	T13,T22
1	1	Covered	T2,T7,T16

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T2,T7,T17

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T2,T7,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T2,T3,T7

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T2,T3,T7

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T7

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T7
Phase1St	198	Covered	T2,T3,T7
Phase2St	215	Covered	T2,T3,T7
Phase3St	233	Covered	T2,T3,T7
TerminalSt	249	Covered	T2,T3,T7
TimeoutSt	159	Covered	T2,T7,T16

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T2,T3,T7
IdleSt->TimeoutSt	159	Covered	T2,T7,T16
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T2,T13,T23
Phase0St->Phase1St	198	Covered	T2,T3,T7
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T5,T24,T25
Phase1St->Phase2St	215	Covered	T2,T3,T7
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T5,T26,T21
Phase2St->Phase3St	233	Covered	T2,T3,T7
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T16,T17,T27
Phase3St->TerminalSt	249	Covered	T2,T3,T7
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T2,T3,T7
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T2,T7,T18
TimeoutSt->Phase0St	172	Covered	T2,T7,T16

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T16
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T16
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T16
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T23,T28,T29
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T24,T25
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T26,T21
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T17,T27
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	770	0	0
CheckAccumTrig0_A	2147483647	2593	0	0
CheckAccumTrig1_A	2147483647	117	0	0
CheckClr_A	2147483647	1228	0	0
CheckEn_A	2147483647	1317910514	0	0
CheckPhase0_A	2147483647	2904	0	0
CheckPhase1_A	2147483647	2839	0	0
CheckPhase2_A	2147483647	2781	0	0
CheckPhase3_A	2147483647	2733	0	0
CheckTimeout0_A	2147483647	3303	0	0
CheckTimeoutSt1_A	2147483647	386026	0	0
CheckTimeoutSt2_A	2147483647	2941	0	0
CheckTimeoutStTrig_A	2147483647	243	0	0
ErrorStAllEscAsserted_A	2147483647	4220	0	0
ErrorStIsTerminal_A	2147483647	3500	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	770	0	0
T9	90584	137	0	0
T10	0	259	0	0
T11	0	132	0	0
T30	0	136	0	0
T31	0	106	0	0
T32	63508	0	0	0
T33	374088	0	0	0
T34	462588	0	0	0
T35	220768	0	0	0
T36	46428	0	0	0
T37	3745940	0	0	0
T38	382772	0	0	0
T39	235768	0	0	0
T40	189680	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2593	0	0
T2	1351772	22	0	0
T3	3766260	2	0	0
T4	2183888	0	0	0
T5	639820	8	0	0
T6	1071240	1	0	0
T7	555248	8	0	0
T12	0	4	0	0
T13	0	11	0	0
T15	14392	1	0	0
T16	24600	0	0	0
T17	1626828	3	0	0
T18	281784	6	0	0
T24	0	8	0	0
T27	0	4	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	5	0	0
T45	0	9	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	117	0	0
T2	1013829	2	0	0
T3	2824695	0	0	0
T4	1637916	0	0	0
T5	479865	0	0	0
T6	803430	0	0	0
T7	416436	0	0	0
T15	10794	0	0	0
T16	18450	0	0	0
T17	1220121	0	0	0
T18	211338	1	0	0
T19	0	1	0	0
T21	331179	4	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T54	0	2	0	0
T55	0	4	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	3	0	0
T63	0	1	0	0
T64	36409	0	0	0
T65	220143	0	0	0
T66	11492	0	0	0
T67	1148	0	0	0
T68	367327	0	0	0
T69	111636	0	0	0
T70	354883	0	0	0
T71	426501	0	0	0
T72	88028	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1228	0	0
T2	1351772	8	0	0
T3	3766260	1	0	0
T4	2183888	0	0	0
T5	639820	6	0	0
T6	1071240	0	0	0
T7	555248	2	0	0
T12	0	1	0	0
T15	14392	0	0	0
T16	24600	1	0	0
T17	1626828	1	0	0
T18	281784	5	0	0
T21	0	4	0	0
T24	0	5	0	0
T26	0	2	0	0
T44	0	2	0	0
T45	0	1	0	0
T68	0	5	0	0
T73	0	2	0	0
T74	0	3	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1317910514	0	0
T1	353548	342223	0	0
T2	1351772	1543149	0	0
T3	3766260	1116227	0	0
T4	2183888	1092960	0	0
T5	639820	324256	0	0
T6	1071240	616049	0	0
T7	555248	403686	0	0
T15	14392	12779	0	0
T16	24600	20891	0	0
T17	1626828	855304	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2904	0	0
T2	1351772	24	0	0
T3	3766260	2	0	0
T4	2183888	0	0	0
T5	639820	8	0	0
T6	1071240	1	0	0
T7	555248	11	0	0
T12	0	4	0	0
T13	0	10	0	0
T15	14392	1	0	0
T16	24600	1	0	0
T17	1626828	3	0	0
T18	281784	8	0	0
T24	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	5	0	0
T45	0	10	0	0
T73	0	3	0	0
T80	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2839	0	0
T2	1351772	23	0	0
T3	3766260	2	0	0
T4	2183888	0	0	0
T5	639820	7	0	0
T6	1071240	1	0	0
T7	555248	11	0	0
T12	0	4	0	0
T13	0	10	0	0
T15	14392	1	0	0
T16	24600	1	0	0
T17	1626828	3	0	0
T18	281784	8	0	0
T24	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	5	0	0
T45	0	10	0	0
T73	0	3	0	0
T80	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2781	0	0
T2	1351772	23	0	0
T3	3766260	2	0	0
T4	2183888	0	0	0
T5	639820	6	0	0
T6	1071240	1	0	0
T7	555248	11	0	0
T12	0	4	0	0
T13	0	10	0	0
T15	14392	1	0	0
T16	24600	1	0	0
T17	1626828	3	0	0
T18	281784	8	0	0
T24	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	5	0	0
T45	0	10	0	0
T73	0	3	0	0
T80	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2733	0	0
T2	1351772	23	0	0
T3	3766260	2	0	0
T4	2183888	0	0	0
T5	639820	6	0	0
T6	1071240	1	0	0
T7	555248	11	0	0
T12	0	4	0	0
T13	0	10	0	0
T15	14392	1	0	0
T16	24600	0	0	0
T17	1626828	2	0	0
T18	281784	8	0	0
T24	0	8	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	5	0	0
T45	0	10	0	0
T73	0	3	0	0
T80	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3303	0	0
T2	1351772	13	0	0
T3	3766260	0	0	0
T4	2183888	0	0	0
T5	639820	0	0	0
T6	1071240	0	0	0
T7	555248	52	0	0
T13	0	35	0	0
T15	14392	0	0	0
T16	24600	1	0	0
T17	1626828	0	0	0
T18	281784	5	0	0
T21	0	3	0	0
T24	0	10	0	0
T26	0	1	0	0
T27	0	4	0	0
T45	0	77	0	0
T46	0	1	0	0
T73	0	4	0	0
T75	0	9	0	0
T76	0	12	0	0
T78	0	1	0	0
T80	0	3	0	0
T81	0	4	0	0
T82	0	2	0	0
T83	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	386026	0	0
T2	1351772	801	0	0
T3	3766260	0	0	0
T4	2183888	0	0	0
T5	639820	0	0	0
T6	1071240	0	0	0
T7	555248	7620	0	0
T13	0	1907	0	0
T15	14392	0	0	0
T16	24600	140	0	0
T17	1626828	0	0	0
T18	281784	949	0	0
T21	0	614	0	0
T24	0	1976	0	0
T26	0	109	0	0
T27	0	959	0	0
T45	0	5203	0	0
T46	0	76	0	0
T68	0	10145	0	0
T73	0	878	0	0
T75	0	1427	0	0
T76	0	2011	0	0
T78	0	26	0	0
T80	0	676	0	0
T81	0	435	0	0
T82	0	98	0	0
T83	0	60	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2941	0	0
T2	1013829	8	0	0
T3	2824695	0	0	0
T4	1637916	0	0	0
T5	639820	0	0	0
T6	1071240	0	0	0
T7	555248	49	0	0
T12	383750	0	0	0
T13	0	34	0	0
T15	14392	0	0	0
T16	24600	0	0	0
T17	1626828	0	0	0
T18	281784	3	0	0
T21	0	2	0	0
T24	0	9	0	0
T26	0	1	0	0
T27	0	4	0	0
T41	2819	0	0	0
T42	58167	0	0	0
T45	0	76	0	0
T46	0	1	0	0
T47	0	1	0	0
T68	0	58	0	0
T69	0	1	0	0
T73	0	1	0	0
T75	0	7	0	0
T76	0	11	0	0
T78	0	1	0	0
T80	0	1	0	0
T81	0	4	0	0
T82	0	3	0	0
T83	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	243	0	0
T2	337943	2	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	479865	0	0	0
T6	1071240	0	0	0
T7	416436	2	0	0
T8	795526	0	0	0
T12	1151250	0	0	0
T13	151770	1	0	0
T15	10794	0	0	0
T16	24600	1	0	0
T17	1626828	0	0	0
T18	281784	1	0	0
T23	0	4	0	0
T24	0	1	0	0
T25	0	2	0	0
T38	0	3	0	0
T41	8457	0	0	0
T42	174501	0	0	0
T43	23895	0	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T68	0	2	0	0
T73	0	3	0	0
T75	0	2	0	0
T76	0	2	0	0
T80	0	2	0	0
T84	0	6	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4220	0	0
T9	90584	697	0	0
T10	0	1399	0	0
T11	0	661	0	0
T30	0	782	0	0
T31	0	681	0	0
T32	63508	0	0	0
T33	374088	0	0	0
T34	462588	0	0	0
T35	220768	0	0	0
T36	46428	0	0	0
T37	3745940	0	0	0
T38	382772	0	0	0
T39	235768	0	0	0
T40	189680	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3500	0	0
T9	90584	577	0	0
T10	0	1159	0	0
T11	0	541	0	0
T30	0	662	0	0
T31	0	561	0	0
T32	63508	0	0	0
T33	374088	0	0	0
T34	462588	0	0	0
T35	220768	0	0	0
T36	46428	0	0	0
T37	3745940	0	0	0
T38	382772	0	0	0
T39	235768	0	0	0
T40	189680	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	353548	353180	0	0
T2	1351772	1351636	0	0
T3	3766260	3766004	0	0
T4	2183888	2183572	0	0
T5	639820	639780	0	0
T6	1071240	1071208	0	0
T7	555248	555044	0	0
T15	14392	14096	0	0
T16	24600	24236	0	0
T17	1626828	1626548	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	353548	353180	0	0
T2	1351772	1351636	0	0
T3	3766260	3766004	0	0
T4	2183888	2183572	0	0
T5	639820	639780	0	0
T6	1071240	1071208	0	0
T7	555248	555044	0	0
T15	14392	14096	0	0
T16	24600	24236	0	0
T17	1626828	1626548	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T7,T16
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T16

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T18

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T16
1	0	1	Covered	T2,T7,T13
1	1	0	Covered	T1,T2,T7
1	1	1	Covered	T2,T7,T16

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T16
0	1	Covered	T16,T18,T45
1	0	Covered	T2,T21,T47

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T7,T16
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T21,T47

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T16
1	0	Not Covered
1	1	Covered	T16,T18,T45

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T16
1	Covered	T2,T18,T43

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T16
1	Covered	T2,T13,T44

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T18,T42
1	Covered	T2,T7,T16

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T16
1	Covered	T42,T13,T45

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T7,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T7,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T18,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T7,T16

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T7,T16
Phase1St	198	Covered	T2,T7,T16
Phase2St	215	Covered	T2,T7,T16
Phase3St	233	Covered	T2,T7,T16
TerminalSt	249	Covered	T2,T7,T18
TimeoutSt	159	Covered	T2,T7,T16

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T2,T7,T18
IdleSt->TimeoutSt	159	Covered	T2,T7,T16
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T2,T13,T29
Phase0St->Phase1St	198	Covered	T2,T7,T16
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T24,T25,T28
Phase1St->Phase2St	215	Covered	T2,T7,T16
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T26,T21,T88
Phase2St->Phase3St	233	Covered	T2,T7,T16
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T16,T27,T32
Phase3St->TerminalSt	249	Covered	T2,T7,T18
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T7,T18
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T7,T18
TimeoutSt->Phase0St	172	Covered	T2,T16,T18

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T18
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T16
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T16,T18
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T16
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T29,T89,T90
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T7,T16
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T7,T16
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T24,T25,T28
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T7,T16
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T7,T16
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T26,T21,T88
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T7,T16
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T7,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T27,T32
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T7,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T7,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T7,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T7,T18
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	734617330	175	0	0
CheckAccumTrig0_A	734617330	1007	0	0
CheckAccumTrig1_A	734617330	42	0	0
CheckClr_A	734617330	515	0	0
CheckEn_A	734491542	286710030	0	0
CheckPhase0_A	734617330	1097	0	0
CheckPhase1_A	734617330	1065	0	0
CheckPhase2_A	734617330	1042	0	0
CheckPhase3_A	734617330	1020	0	0
CheckTimeout0_A	734617330	1025	0	0
CheckTimeoutSt1_A	734617330	115609	0	0
CheckTimeoutSt2_A	734617330	914	0	0
CheckTimeoutStTrig_A	734617330	68	0	0
ErrorStAllEscAsserted_A	734617330	1014	0	0
ErrorStIsTerminal_A	734617330	834	0	0
EscStateOut_A	734489636	734414656	0	0
u_state_regs_A	734617330	734466055	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	175	0	0
T9	22646	38	0	0
T10	0	45	0	0
T11	0	32	0	0
T30	0	40	0	0
T31	0	20	0	0
T32	15877	0	0	0
T33	93522	0	0	0
T34	115647	0	0	0
T35	55192	0	0	0
T36	11607	0	0	0
T37	936485	0	0	0
T38	95693	0	0	0
T39	58942	0	0	0
T40	47420	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	1007	0	0
T2	337943	9	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	2	0	0
T12	0	1	0	0
T13	0	4	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	1	0	0
T24	0	6	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	3	0	0
T45	0	6	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	42	0	0
T2	337943	1	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	0	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	0	0	0
T21	0	1	0	0
T47	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	515	0	0
T2	337943	3	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	1	0	0
T12	0	1	0	0
T15	3598	0	0	0
T16	6150	1	0	0
T17	406707	0	0	0
T18	70446	2	0	0
T24	0	3	0	0
T26	0	2	0	0
T44	0	2	0	0
T45	0	1	0	0
T74	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734491542	286710030	0	0
T1	88387	77341	0	0
T2	337943	992721	0	0
T3	941565	62830	0	0
T4	545972	543088	0	0
T5	159955	159945	0	0
T6	267810	267217	0	0
T7	138812	110366	0	0
T15	3598	3174	0	0
T16	6150	2717	0	0
T17	406707	406636	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	1097	0	0
T2	337943	7	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	2	0	0
T12	0	1	0	0
T13	0	3	0	0
T15	3598	0	0	0
T16	6150	1	0	0
T17	406707	0	0	0
T18	70446	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	3	0	0
T45	0	7	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	1065	0	0
T2	337943	7	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	2	0	0
T12	0	1	0	0
T13	0	3	0	0
T15	3598	0	0	0
T16	6150	1	0	0
T17	406707	0	0	0
T18	70446	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	3	0	0
T45	0	7	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	1042	0	0
T2	337943	7	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	2	0	0
T12	0	1	0	0
T13	0	3	0	0
T15	3598	0	0	0
T16	6150	1	0	0
T17	406707	0	0	0
T18	70446	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	3	0	0
T45	0	7	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	1020	0	0
T2	337943	7	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	2	0	0
T12	0	1	0	0
T13	0	3	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	2	0	0
T24	0	5	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	3	0	0
T45	0	7	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	1025	0	0
T2	337943	2	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	9	0	0
T15	3598	0	0	0
T16	6150	1	0	0
T17	406707	0	0	0
T18	70446	2	0	0
T24	0	7	0	0
T26	0	1	0	0
T45	0	3	0	0
T73	0	1	0	0
T80	0	2	0	0
T81	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	115609	0	0
T2	337943	67	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	1472	0	0
T15	3598	0	0	0
T16	6150	140	0	0
T17	406707	0	0	0
T18	70446	867	0	0
T24	0	1263	0	0
T26	0	109	0	0
T45	0	464	0	0
T73	0	317	0	0
T80	0	522	0	0
T81	0	218	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	914	0	0
T2	337943	1	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	9	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	1	0	0
T24	0	7	0	0
T26	0	1	0	0
T45	0	2	0	0
T73	0	1	0	0
T80	0	1	0	0
T81	0	2	0	0
T82	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	68	0	0
T6	267810	0	0	0
T8	795526	0	0	0
T12	383750	0	0	0
T13	151770	0	0	0
T16	6150	1	0	0
T17	406707	0	0	0
T18	70446	1	0	0
T23	0	1	0	0
T38	0	3	0	0
T41	2819	0	0	0
T42	58167	0	0	0
T43	23895	0	0	0
T45	0	1	0	0
T47	0	1	0	0
T76	0	1	0	0
T80	0	1	0	0
T84	0	3	0	0
T87	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	1014	0	0
T9	22646	178	0	0
T10	0	336	0	0
T11	0	159	0	0
T30	0	186	0	0
T31	0	155	0	0
T32	15877	0	0	0
T33	93522	0	0	0
T34	115647	0	0	0
T35	55192	0	0	0
T36	11607	0	0	0
T37	936485	0	0	0
T38	95693	0	0	0
T39	58942	0	0	0
T40	47420	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	834	0	0
T9	22646	148	0	0
T10	0	276	0	0
T11	0	129	0	0
T30	0	156	0	0
T31	0	125	0	0
T32	15877	0	0	0
T33	93522	0	0	0
T34	115647	0	0	0
T35	55192	0	0	0
T36	11607	0	0	0
T37	936485	0	0	0
T38	95693	0	0	0
T39	58942	0	0	0
T40	47420	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734489636	734414656	0	0
T1	88387	88295	0	0
T2	337943	337909	0	0
T3	941565	941501	0	0
T4	545972	545893	0	0
T5	159955	159945	0	0
T6	267810	267802	0	0
T7	138812	138761	0	0
T15	3598	3524	0	0
T16	6150	6059	0	0
T17	406707	406637	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	734466055	0	0
T1	88387	88295	0	0
T2	337943	337909	0	0
T3	941565	941501	0	0
T4	545972	545893	0	0
T5	159955	159945	0	0
T6	267810	267802	0	0
T7	138812	138761	0	0
T15	3598	3524	0	0
T16	6150	6059	0	0
T17	406707	406637	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T18
1	0	1	Covered	T2,T4,T7
1	1	0	Covered	T2,T7,T18
1	1	1	Covered	T2,T7,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T18
0	1	Covered	T2,T7,T13
1	0	Covered	T21,T49,T54

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T7,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T21,T49,T54

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T18
1	0	Covered	T13
1	1	Covered	T2,T7,T13

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T7,T17,T41

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T2,T17,T12

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T2,T7,T18

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T17
1	Covered	T2,T3,T7

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T7,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T5,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T7
Phase1St	198	Covered	T2,T3,T7
Phase2St	215	Covered	T2,T3,T7
Phase3St	233	Covered	T2,T3,T7
TerminalSt	249	Covered	T2,T3,T7
TimeoutSt	159	Covered	T2,T7,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T2,T3,T7
IdleSt->TimeoutSt	159	Covered	T2,T7,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T23,T89,T91
Phase0St->Phase1St	198	Covered	T2,T3,T7
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T92,T61,T62
Phase1St->Phase2St	215	Covered	T2,T3,T7
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T47,T93,T94
Phase2St->Phase3St	233	Covered	T2,T3,T7
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T17,T92,T19
Phase3St->TerminalSt	249	Covered	T2,T3,T7
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T3,T7
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T7,T18,T13
TimeoutSt->Phase0St	172	Covered	T2,T7,T13

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T13
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T7,T18,T13
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T23,T89,T91
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T92,T61,T62
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T47,T93,T94
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T17,T92,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	734617330	188	0	0
CheckAccumTrig0_A	734617330	549	0	0
CheckAccumTrig1_A	734617330	25	0	0
CheckClr_A	734617330	271	0	0
CheckEn_A	734491542	342155066	0	0
CheckPhase0_A	734617330	631	0	0
CheckPhase1_A	734617330	616	0	0
CheckPhase2_A	734617330	602	0	0
CheckPhase3_A	734617330	594	0	0
CheckTimeout0_A	734617330	710	0	0
CheckTimeoutSt1_A	734617330	90855	0	0
CheckTimeoutSt2_A	734617330	617	0	0
CheckTimeoutStTrig_A	734617330	68	0	0
ErrorStAllEscAsserted_A	734617330	1045	0	0
ErrorStIsTerminal_A	734617330	865	0	0
EscStateOut_A	734489636	734414656	0	0
u_state_regs_A	734617330	734466055	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	188	0	0
T9	22646	35	0	0
T10	0	69	0	0
T11	0	19	0	0
T30	0	37	0	0
T31	0	28	0	0
T32	15877	0	0	0
T33	93522	0	0	0
T34	115647	0	0	0
T35	55192	0	0	0
T36	11607	0	0	0
T37	936485	0	0	0
T38	95693	0	0	0
T39	58942	0	0	0
T40	47420	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	549	0	0
T2	337943	1	0	0
T3	941565	1	0	0
T4	545972	0	0	0
T5	159955	1	0	0
T6	267810	1	0	0
T7	138812	2	0	0
T12	0	1	0	0
T13	0	3	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	2	0	0
T18	70446	2	0	0
T41	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	25	0	0
T19	0	1	0	0
T21	331179	1	0	0
T49	0	1	0	0
T54	0	1	0	0
T55	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	36409	0	0	0
T65	220143	0	0	0
T66	11492	0	0	0
T67	1148	0	0	0
T68	367327	0	0	0
T69	111636	0	0	0
T70	354883	0	0	0
T71	426501	0	0	0
T72	88028	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	271	0	0
T2	337943	1	0	0
T3	941565	1	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	0	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	1	0	0
T18	70446	2	0	0
T21	0	3	0	0
T24	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734491542	342155066	0	0
T1	88387	88294	0	0
T2	337943	251195	0	0
T3	941565	74569	0	0
T4	545972	586	0	0
T5	159955	586	0	0
T6	267810	35814	0	0
T7	138812	127034	0	0
T15	3598	3188	0	0
T16	6150	6058	0	0
T17	406707	35879	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	631	0	0
T2	337943	3	0	0
T3	941565	1	0	0
T4	545972	0	0	0
T5	159955	1	0	0
T6	267810	1	0	0
T7	138812	3	0	0
T12	0	1	0	0
T13	0	4	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	2	0	0
T18	70446	2	0	0
T41	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	616	0	0
T2	337943	3	0	0
T3	941565	1	0	0
T4	545972	0	0	0
T5	159955	1	0	0
T6	267810	1	0	0
T7	138812	3	0	0
T12	0	1	0	0
T13	0	4	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	2	0	0
T18	70446	2	0	0
T41	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	602	0	0
T2	337943	3	0	0
T3	941565	1	0	0
T4	545972	0	0	0
T5	159955	1	0	0
T6	267810	1	0	0
T7	138812	3	0	0
T12	0	1	0	0
T13	0	4	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	2	0	0
T18	70446	2	0	0
T41	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	594	0	0
T2	337943	3	0	0
T3	941565	1	0	0
T4	545972	0	0	0
T5	159955	1	0	0
T6	267810	1	0	0
T7	138812	3	0	0
T12	0	1	0	0
T13	0	4	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	1	0	0
T18	70446	2	0	0
T41	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	710	0	0
T2	337943	2	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	10	0	0
T13	0	17	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	1	0	0
T21	0	1	0	0
T27	0	2	0	0
T46	0	1	0	0
T75	0	2	0	0
T76	0	3	0	0
T83	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	90855	0	0
T2	337943	169	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	1406	0	0
T13	0	944	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	51	0	0
T27	0	489	0	0
T46	0	76	0	0
T68	0	10145	0	0
T75	0	44	0	0
T76	0	456	0	0
T83	0	60	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	617	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	9	0	0
T12	383750	0	0	0
T13	0	16	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	1	0	0
T27	0	2	0	0
T41	2819	0	0	0
T42	58167	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T68	0	58	0	0
T69	0	1	0	0
T76	0	2	0	0
T83	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	68	0	0
T2	337943	2	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	1	0	0
T13	0	1	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	0	0	0
T23	0	2	0	0
T25	0	2	0	0
T48	0	1	0	0
T68	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0
T84	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	1045	0	0
T9	22646	168	0	0
T10	0	347	0	0
T11	0	167	0	0
T30	0	192	0	0
T31	0	171	0	0
T32	15877	0	0	0
T33	93522	0	0	0
T34	115647	0	0	0
T35	55192	0	0	0
T36	11607	0	0	0
T37	936485	0	0	0
T38	95693	0	0	0
T39	58942	0	0	0
T40	47420	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	865	0	0
T9	22646	138	0	0
T10	0	287	0	0
T11	0	137	0	0
T30	0	162	0	0
T31	0	141	0	0
T32	15877	0	0	0
T33	93522	0	0	0
T34	115647	0	0	0
T35	55192	0	0	0
T36	11607	0	0	0
T37	936485	0	0	0
T38	95693	0	0	0
T39	58942	0	0	0
T40	47420	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734489636	734414656	0	0
T1	88387	88295	0	0
T2	337943	337909	0	0
T3	941565	941501	0	0
T4	545972	545893	0	0
T5	159955	159945	0	0
T6	267810	267802	0	0
T7	138812	138761	0	0
T15	3598	3524	0	0
T16	6150	6059	0	0
T17	406707	406637	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	734466055	0	0
T1	88387	88295	0	0
T2	337943	337909	0	0
T3	941565	941501	0	0
T4	545972	545893	0	0
T5	159955	159945	0	0
T6	267810	267802	0	0
T7	138812	138761	0	0
T15	3598	3524	0	0
T16	6150	6059	0	0
T17	406707	406637	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T19
1	1	1	Covered	T2,T3,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T18
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T2,T7,T18
1	1	1	Covered	T2,T7,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T18
0	1	Covered	T7,T24,T73
1	0	Covered	T2,T18,T21

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T7,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T18,T21

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T18
1	0	Not Covered
1	1	Covered	T7,T24,T73

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T2,T45,T24

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T2,T7,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T5
1	Covered	T2,T3,T77

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T2,T7,T18

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T7,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T7,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T7
Phase1St	198	Covered	T2,T3,T7
Phase2St	215	Covered	T2,T3,T7
Phase3St	233	Covered	T2,T3,T7
TerminalSt	249	Covered	T2,T3,T7
TimeoutSt	159	Covered	T2,T7,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T2,T3,T7
IdleSt->TimeoutSt	159	Covered	T2,T7,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T28,T95,T96
Phase0St->Phase1St	198	Covered	T2,T3,T7
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T5,T97,T98
Phase1St->Phase2St	215	Covered	T2,T3,T7
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T5,T68,T91
Phase2St->Phase3St	233	Covered	T2,T3,T7
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T49,T99,T20
Phase3St->TerminalSt	249	Covered	T2,T3,T7
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T7,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T7,T18
TimeoutSt->Phase0St	172	Covered	T2,T7,T18

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T18
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T96,T100
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T97,T98
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T68,T91
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T49,T99,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T7,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	734617330	203	0	0
CheckAccumTrig0_A	734617330	514	0	0
CheckAccumTrig1_A	734617330	24	0	0
CheckClr_A	734617330	208	0	0
CheckEn_A	734491542	353599416	0	0
CheckPhase0_A	734617330	582	0	0
CheckPhase1_A	734617330	574	0	0
CheckPhase2_A	734617330	561	0	0
CheckPhase3_A	734617330	553	0	0
CheckTimeout0_A	734617330	833	0	0
CheckTimeoutSt1_A	734617330	103186	0	0
CheckTimeoutSt2_A	734617330	754	0	0
CheckTimeoutStTrig_A	734617330	54	0	0
ErrorStAllEscAsserted_A	734617330	1078	0	0
ErrorStIsTerminal_A	734617330	898	0	0
EscStateOut_A	734489636	734414656	0	0
u_state_regs_A	734617330	734466055	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	203	0	0
T9	22646	32	0	0
T10	0	72	0	0
T11	0	43	0	0
T30	0	35	0	0
T31	0	21	0	0
T32	15877	0	0	0
T33	93522	0	0	0
T34	115647	0	0	0
T35	55192	0	0	0
T36	11607	0	0	0
T37	936485	0	0	0
T38	95693	0	0	0
T39	58942	0	0	0
T40	47420	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	514	0	0
T2	337943	6	0	0
T3	941565	1	0	0
T4	545972	0	0	0
T5	159955	7	0	0
T6	267810	0	0	0
T7	138812	2	0	0
T12	0	1	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	1	0	0
T24	0	1	0	0
T27	0	4	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	24	0	0
T2	337943	1	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	0	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	1	0	0
T21	0	2	0	0
T48	0	1	0	0
T50	0	2	0	0
T55	0	2	0	0
T62	0	1	0	0
T96	0	2	0	0
T101	0	1	0	0
T102	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	208	0	0
T2	337943	4	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	6	0	0
T6	267810	0	0	0
T7	138812	1	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	1	0	0
T21	0	1	0	0
T24	0	1	0	0
T68	0	5	0	0
T73	0	2	0	0
T79	0	1	0	0
T103	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734491542	353599416	0	0
T1	88387	88294	0	0
T2	337943	145022	0	0
T3	941565	172930	0	0
T4	545972	3394	0	0
T5	159955	3780	0	0
T6	267810	267237	0	0
T7	138812	83085	0	0
T15	3598	3203	0	0
T16	6150	6058	0	0
T17	406707	406636	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	582	0	0
T2	337943	7	0	0
T3	941565	1	0	0
T4	545972	0	0	0
T5	159955	7	0	0
T6	267810	0	0	0
T7	138812	3	0	0
T12	0	1	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	2	0	0
T24	0	2	0	0
T45	0	1	0	0
T73	0	3	0	0
T80	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	574	0	0
T2	337943	7	0	0
T3	941565	1	0	0
T4	545972	0	0	0
T5	159955	6	0	0
T6	267810	0	0	0
T7	138812	3	0	0
T12	0	1	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	2	0	0
T24	0	2	0	0
T45	0	1	0	0
T73	0	3	0	0
T80	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	561	0	0
T2	337943	7	0	0
T3	941565	1	0	0
T4	545972	0	0	0
T5	159955	5	0	0
T6	267810	0	0	0
T7	138812	3	0	0
T12	0	1	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	2	0	0
T24	0	2	0	0
T45	0	1	0	0
T73	0	3	0	0
T80	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	553	0	0
T2	337943	7	0	0
T3	941565	1	0	0
T4	545972	0	0	0
T5	159955	5	0	0
T6	267810	0	0	0
T7	138812	3	0	0
T12	0	1	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	2	0	0
T24	0	2	0	0
T45	0	1	0	0
T73	0	3	0	0
T80	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	833	0	0
T2	337943	6	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	13	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	2	0	0
T24	0	2	0	0
T27	0	1	0	0
T73	0	3	0	0
T75	0	7	0	0
T80	0	1	0	0
T81	0	2	0	0
T82	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	103186	0	0
T2	337943	387	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	1819	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	31	0	0
T24	0	684	0	0
T27	0	423	0	0
T73	0	561	0	0
T75	0	1383	0	0
T80	0	154	0	0
T81	0	217	0	0
T82	0	49	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	754	0	0
T2	337943	5	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	12	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	1	0	0
T24	0	1	0	0
T27	0	1	0	0
T75	0	7	0	0
T76	0	1	0	0
T81	0	2	0	0
T82	0	1	0	0
T83	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	54	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	1	0	0
T12	383750	0	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	0	0	0
T23	0	1	0	0
T24	0	1	0	0
T41	2819	0	0	0
T42	58167	0	0	0
T68	0	1	0	0
T73	0	3	0	0
T80	0	1	0	0
T84	0	2	0	0
T85	0	1	0	0
T86	0	1	0	0
T104	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	1078	0	0
T9	22646	166	0	0
T10	0	356	0	0
T11	0	180	0	0
T30	0	218	0	0
T31	0	158	0	0
T32	15877	0	0	0
T33	93522	0	0	0
T34	115647	0	0	0
T35	55192	0	0	0
T36	11607	0	0	0
T37	936485	0	0	0
T38	95693	0	0	0
T39	58942	0	0	0
T40	47420	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	898	0	0
T9	22646	136	0	0
T10	0	296	0	0
T11	0	150	0	0
T30	0	188	0	0
T31	0	128	0	0
T32	15877	0	0	0
T33	93522	0	0	0
T34	115647	0	0	0
T35	55192	0	0	0
T36	11607	0	0	0
T37	936485	0	0	0
T38	95693	0	0	0
T39	58942	0	0	0
T40	47420	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734489636	734414656	0	0
T1	88387	88295	0	0
T2	337943	337909	0	0
T3	941565	941501	0	0
T4	545972	545893	0	0
T5	159955	159945	0	0
T6	267810	267802	0	0
T7	138812	138761	0	0
T15	3598	3524	0	0
T16	6150	6059	0	0
T17	406707	406637	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	734466055	0	0
T1	88387	88295	0	0
T2	337943	337909	0	0
T3	941565	941501	0	0
T4	545972	545893	0	0
T5	159955	159945	0	0
T6	267810	267802	0	0
T7	138812	138761	0	0
T15	3598	3524	0	0
T16	6150	6059	0	0
T17	406707	406637	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	44	97.78
Logical	45	44	97.78
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T7,T15
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T15

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T20
1	1	1	Covered	T2,T7,T15

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T18
1	0	1	Covered	T2,T3,T7
1	1	0	Covered	T2,T7,T18
1	1	1	Covered	T2,T7,T13

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T13
0	1	Covered	T7,T84,T105
1	0	Covered	T2,T76,T47

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T7,T13
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T76,T47

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T13
1	0	Covered	T22
1	1	Covered	T7,T84,T105

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T17
1	Covered	T15,T27,T76

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T15
1	Covered	T2,T17,T13

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T15
1	Covered	T2,T7,T18

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T15
1	Covered	T2,T7,T13

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T7,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T7,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T7,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T15,T18

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T7,T15
Phase1St	198	Covered	T2,T7,T15
Phase2St	215	Covered	T2,T7,T15
Phase3St	233	Covered	T2,T7,T15
TerminalSt	249	Covered	T2,T7,T15
TimeoutSt	159	Covered	T2,T7,T13

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T2,T7,T15
IdleSt->TimeoutSt	159	Covered	T2,T7,T13
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T13,T106,T107
Phase0St->Phase1St	198	Covered	T2,T7,T15
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T2,T108,T109
Phase1St->Phase2St	215	Covered	T2,T7,T15
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T57,T19,T95
Phase2St->Phase3St	233	Covered	T2,T7,T15
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T90,T19,T110
Phase3St->TerminalSt	249	Covered	T2,T7,T15
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T7,T18
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T7,T13
TimeoutSt->Phase0St	172	Covered	T2,T7,T76

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T15
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T76
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T13
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T106,T107,T102
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T7,T15
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T7,T17
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T108,T109
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T7,T15
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T7,T17
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T57,T19,T95
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T7,T15
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T7,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T90,T19,T110
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T7,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T7,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T18,T44
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T7,T15
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	734617330	204	0	0
CheckAccumTrig0_A	734617330	523	0	0
CheckAccumTrig1_A	734617330	26	0	0
CheckClr_A	734617330	234	0	0
CheckEn_A	734491542	335446002	0	0
CheckPhase0_A	734617330	594	0	0
CheckPhase1_A	734617330	584	0	0
CheckPhase2_A	734617330	576	0	0
CheckPhase3_A	734617330	566	0	0
CheckTimeout0_A	734617330	735	0	0
CheckTimeoutSt1_A	734617330	76376	0	0
CheckTimeoutSt2_A	734617330	656	0	0
CheckTimeoutStTrig_A	734617330	53	0	0
ErrorStAllEscAsserted_A	734617330	1083	0	0
ErrorStIsTerminal_A	734617330	903	0	0
EscStateOut_A	734489636	734414656	0	0
u_state_regs_A	734617330	734466055	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	204	0	0
T9	22646	32	0	0
T10	0	73	0	0
T11	0	38	0	0
T30	0	24	0	0
T31	0	37	0	0
T32	15877	0	0	0
T33	93522	0	0	0
T34	115647	0	0	0
T35	55192	0	0	0
T36	11607	0	0	0
T37	936485	0	0	0
T38	95693	0	0	0
T39	58942	0	0	0
T40	47420	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	523	0	0
T2	337943	6	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	2	0	0
T12	0	1	0	0
T13	0	4	0	0
T15	3598	1	0	0
T16	6150	0	0	0
T17	406707	1	0	0
T18	70446	2	0	0
T24	0	1	0	0
T44	0	2	0	0
T45	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	26	0	0
T2	337943	1	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	0	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	0	0	0
T29	0	1	0	0
T61	0	1	0	0
T76	0	1	0	0
T102	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	234	0	0
T2	337943	5	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	0	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	1	0	0
T21	0	1	0	0
T24	0	1	0	0
T44	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T76	0	1	0	0
T78	0	1	0	0
T111	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734491542	335446002	0	0
T1	88387	88294	0	0
T2	337943	154211	0	0
T3	941565	805898	0	0
T4	545972	545892	0	0
T5	159955	159945	0	0
T6	267810	45781	0	0
T7	138812	83201	0	0
T15	3598	3214	0	0
T16	6150	6058	0	0
T17	406707	6153	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	594	0	0
T2	337943	7	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	3	0	0
T12	0	1	0	0
T13	0	3	0	0
T15	3598	1	0	0
T16	6150	0	0	0
T17	406707	1	0	0
T18	70446	2	0	0
T24	0	1	0	0
T44	0	2	0	0
T45	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	584	0	0
T2	337943	6	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	3	0	0
T12	0	1	0	0
T13	0	3	0	0
T15	3598	1	0	0
T16	6150	0	0	0
T17	406707	1	0	0
T18	70446	2	0	0
T24	0	1	0	0
T44	0	2	0	0
T45	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	576	0	0
T2	337943	6	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	3	0	0
T12	0	1	0	0
T13	0	3	0	0
T15	3598	1	0	0
T16	6150	0	0	0
T17	406707	1	0	0
T18	70446	2	0	0
T24	0	1	0	0
T44	0	2	0	0
T45	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	566	0	0
T2	337943	6	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	3	0	0
T12	0	1	0	0
T13	0	3	0	0
T15	3598	1	0	0
T16	6150	0	0	0
T17	406707	1	0	0
T18	70446	2	0	0
T24	0	1	0	0
T44	0	2	0	0
T45	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	735	0	0
T2	337943	3	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	20	0	0
T13	0	18	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	0	0	0
T21	0	2	0	0
T24	0	1	0	0
T27	0	1	0	0
T45	0	74	0	0
T76	0	9	0	0
T78	0	1	0	0
T82	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	76376	0	0
T2	337943	178	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	2923	0	0
T13	0	963	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	0	0	0
T21	0	614	0	0
T24	0	29	0	0
T27	0	47	0	0
T45	0	4739	0	0
T76	0	1555	0	0
T78	0	26	0	0
T82	0	49	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	656	0	0
T2	337943	2	0	0
T3	941565	0	0	0
T4	545972	0	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	19	0	0
T13	0	18	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	0	0	0
T21	0	2	0	0
T24	0	1	0	0
T27	0	1	0	0
T45	0	74	0	0
T76	0	8	0	0
T78	0	1	0	0
T82	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	53	0	0
T5	159955	0	0	0
T6	267810	0	0	0
T7	138812	1	0	0
T12	383750	0	0	0
T15	3598	0	0	0
T16	6150	0	0	0
T17	406707	0	0	0
T18	70446	0	0	0
T41	2819	0	0	0
T42	58167	0	0	0
T57	0	4	0	0
T58	0	2	0	0
T59	0	4	0	0
T84	0	1	0	0
T105	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	1083	0	0
T9	22646	185	0	0
T10	0	360	0	0
T11	0	155	0	0
T30	0	186	0	0
T31	0	197	0	0
T32	15877	0	0	0
T33	93522	0	0	0
T34	115647	0	0	0
T35	55192	0	0	0
T36	11607	0	0	0
T37	936485	0	0	0
T38	95693	0	0	0
T39	58942	0	0	0
T40	47420	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	903	0	0
T9	22646	155	0	0
T10	0	300	0	0
T11	0	125	0	0
T30	0	156	0	0
T31	0	167	0	0
T32	15877	0	0	0
T33	93522	0	0	0
T34	115647	0	0	0
T35	55192	0	0	0
T36	11607	0	0	0
T37	936485	0	0	0
T38	95693	0	0	0
T39	58942	0	0	0
T40	47420	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734489636	734414656	0	0
T1	88387	88295	0	0
T2	337943	337909	0	0
T3	941565	941501	0	0
T4	545972	545893	0	0
T5	159955	159945	0	0
T6	267810	267802	0	0
T7	138812	138761	0	0
T15	3598	3524	0	0
T16	6150	6059	0	0
T17	406707	406637	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	734617330	734466055	0	0
T1	88387	88295	0	0
T2	337943	337909	0	0
T3	941565	941501	0	0
T4	545972	545893	0	0
T5	159955	159945	0	0
T6	267810	267802	0	0
T7	138812	138761	0	0
T15	3598	3524	0	0
T16	6150	6059	0	0
T17	406707	406637	0	0