Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	99421	1			T16	1435		T6	7		T46	43
class_i[0x1]	44296	1			T16	1		T5	9		T238	4
class_i[0x2]	55805	1			T4	8		T5	7		T240	1
class_i[0x3]	78439	1			T16	3807		T11	4238		T5	1

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	70395	1			T4	3		T16	1249		T11	1098
alert[0x1]	69610	1			T4	2		T16	1345		T11	1008
alert[0x2]	69383	1			T4	3		T16	1369		T11	991
alert[0x3]	68573	1			T16	1280		T11	1141		T5	3

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

277679

1

T16

5243

T11

4238

T5

11

esc_ping_fail

282

1

T4

8

T5

6

T6

7

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	70317	1			T16	1249		T11	1098		T5	2
esc_integrity_fail	alert[0x1]	69533	1			T16	1345		T11	1008		T5	2
esc_integrity_fail	alert[0x2]	69312	1			T16	1369		T11	991		T5	5
esc_integrity_fail	alert[0x3]	68517	1			T16	1280		T11	1141		T5	2
esc_ping_fail	alert[0x0]	78	1			T4	3		T5	1		T6	3
esc_ping_fail	alert[0x1]	77	1			T4	2		T5	2		T6	3
esc_ping_fail	alert[0x2]	71	1			T4	3		T5	2		T6	1
esc_ping_fail	alert[0x3]	56	1			T5	1		T240	1		T67	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	99348	1			T16	1435		T46	43		T49	1023
esc_integrity_fail	class_i[0x1]	44237	1			T16	1		T5	9		T238	4
esc_integrity_fail	class_i[0x2]	55740	1			T5	2		T19	192		T22	2513
esc_integrity_fail	class_i[0x3]	78354	1			T16	3807		T11	4238		T46	3396
esc_ping_fail	class_i[0x0]	73	1			T6	7		T67	5		T298	2
esc_ping_fail	class_i[0x1]	59	1			T291	3		T217	1		T294	4
esc_ping_fail	class_i[0x2]	65	1			T4	8		T5	5		T240	1
esc_ping_fail	class_i[0x3]	85	1			T5	1		T291	2		T101	6