Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	724532356	0	0	626
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	724532356	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	724532356	724345464	0	0
tb.dut.CheckAccuCntDw	0	0	626	626	0	0
tb.dut.CheckEscCntDw	0	0	626	626	0	0
tb.dut.CheckNAlerts	0	0	626	626	0	0
tb.dut.CheckNClasses	0	0	626	626	0	0
tb.dut.CheckNEscSev	0	0	626	626	0	0
tb.dut.CrashdumpKnownO_A	0	0	724532356	724345464	0	0
tb.dut.EdnKnownO_A	0	0	724532356	724345464	0	0
tb.dut.EscPKnownO_A	0	0	724532356	724345464	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	724532356	90	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	724532356	90	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	724532356	90	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	724532356	90	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	724532356	90	0	0
tb.dut.IrqAKnownO_A	0	0	724532356	724345464	0	0
tb.dut.IrqBKnownO_A	0	0	724532356	724345464	0	0
tb.dut.IrqCKnownO_A	0	0	724532356	724345464	0	0
tb.dut.IrqDKnownO_A	0	0	724532356	724345464	0	0
tb.dut.TlAReadyKnownO_A	0	0	724532356	724345464	0	0
tb.dut.TlDValidKnownO_A	0	0	724532356	724345464	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	750803996	3250057	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	750803996	11273	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	750803996	10566	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	750803996	11437	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	750803996	12200	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	750803996	11423	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	750803996	11366	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	750803996	11635	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	750803996	10802	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	750803996	11022	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	750803996	11314	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	750803996	10558	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	750803996	11363	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	750803996	10742	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	750803996	10612	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	750803996	11759	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	750803996	11253	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	750803996	11394	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	750803996	10736	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	750803996	10474	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	750803996	10806	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	750803996	10718	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	750803996	11265	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	750803996	10991	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	750803996	10489	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	750803996	10645	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	750803996	11392	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	750803996	11360	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	750803996	10801	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	750803996	11423	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	750803996	11311	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	750803996	11396	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	750803996	11378	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	750803996	11522	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	750803996	10572	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	750803996	11431	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	750803996	11160	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	750803996	12160	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	750803996	12065	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	750803996	10440	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	750803996	10950	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	750803996	10942	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	750803996	11190	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	750803996	11460	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	750803996	10645	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	750803996	10771	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	750803996	11395	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	750803996	11524	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	750803996	10893	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	750803996	11962	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	750803996	11390	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	750803996	10791	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	750803996	11249	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	750803996	11705	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	750803996	10880	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	750803996	11491	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	750803996	10758	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	750803996	10464	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	750803996	10731	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	750803996	10774	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	750803996	10946	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	750803996	11530	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	750803996	12094	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	750803996	11284	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	750803996	10857	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	750803996	10620	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	750803996	11316	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	750803996	10758	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	750803996	10922	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	750803996	11043	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	750803996	19128	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	750803996	10785	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	750803996	10505	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	750803996	10340	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	750803996	11277	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	750803996	10650	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	750803996	11182	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	750803996	11481	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	750803996	11306	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	724532356	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	724532356	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	724532356	90	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	724532356	1535	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	724532356	297254	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	724532356	356571526	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	724532356	310	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	724532356	897	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	724532356	36	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	724532356	469	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	724220815	278322271	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	724532356	979	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	724532356	962	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	724532356	938	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	724532356	916	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	724532356	992	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	724532356	102760	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	724532356	885	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	724532356	68	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	724532356	1624	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	724532356	1354	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	724219181	724146513	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	724532356	724345464	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	724532356	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	724532356	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	724532356	90	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	724532356	6116	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	724532356	167777	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	724532356	409497255	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	724532356	282	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	724532356	491	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	724532356	16	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	724532356	204	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	724220815	312177953	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	724532356	558	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	724532356	548	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	724532356	539	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	724532356	525	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	724532356	1425	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	724532356	139846	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	724532356	1347	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	724532356	61	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	724532356	1609	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	724532356	1339	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	724219181	724146513	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	724532356	724345464	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	724532356	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	724532356	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	724532356	90	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	724532356	5311	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	724532356	192207	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	724532356	434747276	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	724532356	322	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	724532356	489	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	724532356	16	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	724532356	215	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	724220815	348728086	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	724532356	547	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	724532356	538	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	724532356	528	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	724532356	516	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	724532356	1479	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	724532356	140625	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	724532356	1408	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	724532356	55	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	724532356	1620	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	724532356	1350	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	724219181	724146513	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	724532356	724345464	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	724532356	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	724532356	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	724532356	90	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	724532356	2696	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	724532356	149066	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	724532356	437021185	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	724532356	343	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	724532356	504	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	724532356	15	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	724532356	249	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	724220815	343609793	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	724532356	582	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	724532356	578	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	724532356	565	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	724532356	554	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	724532356	1890	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	724532356	149208	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	724532356	1803	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	724532356	69	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	724532356	1582	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	724532356	1312	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	724219181	724146513	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	724532356	724345464	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	750803996	137709545	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	750803996	750096479	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	750803996	750096479	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	750803996	197100678	0	0
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