Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.74	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	5	35	87.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	5	35	87.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	68	1			T19	1		T26	1		T65	1
class_index[0x1]	61	1			T18	2		T24	1		T73	1
class_index[0x2]	55	1			T16	1		T28	3		T26	1
class_index[0x3]	69	1			T16	1		T19	1		T26	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	105	1			T16	1		T19	1		T28	3
intr_timeout_cnt[1]	56	1			T16	1		T24	1		T75	2
intr_timeout_cnt[2]	22	1			T26	1		T82	1		T59	2
intr_timeout_cnt[3]	12	1			T76	1		T81	1		T59	1
intr_timeout_cnt[4]	10	1			T18	2		T65	1		T81	1
intr_timeout_cnt[5]	10	1			T65	1		T254	1		T59	1
intr_timeout_cnt[6]	14	1			T54	3		T81	1		T255	1
intr_timeout_cnt[7]	12	1			T76	1		T86	1		T227	1
intr_timeout_cnt[8]	7	1			T26	1		T59	1		T256	2
intr_timeout_cnt[9]	5	1			T19	1		T256	1		T257	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	5	35	87.50	5

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[7] , intr_timeout_cnt[8]]	--	--	2
[class_index[0x2]]	[intr_timeout_cnt[4]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[8]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	28	1			T19	1		T57	1		T82	2
class_index[0x0]	intr_timeout_cnt[1]	15	1			T75	1		T57	1		T79	4
class_index[0x0]	intr_timeout_cnt[2]	4	1			T258	1		T259	1		T260	1
class_index[0x0]	intr_timeout_cnt[3]	5	1			T76	1		T99	1		T261	1
class_index[0x0]	intr_timeout_cnt[4]	4	1			T65	1		T81	1		T262	1
class_index[0x0]	intr_timeout_cnt[5]	5	1			T254	1		T59	1		T263	1
class_index[0x0]	intr_timeout_cnt[6]	2	1			T255	1		T93	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	4	1			T86	1		T264	1		T265	1
class_index[0x0]	intr_timeout_cnt[8]	1	1			T26	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	26	1			T73	1		T26	1		T55	1
class_index[0x1]	intr_timeout_cnt[1]	18	1			T24	1		T75	1		T30	1
class_index[0x1]	intr_timeout_cnt[2]	8	1			T59	1		T38	1		T97	2
class_index[0x1]	intr_timeout_cnt[3]	1	1			T93	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[4]	4	1			T18	2		T255	1		T266	1
class_index[0x1]	intr_timeout_cnt[5]	1	1			T93	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[6]	2	1			T262	1		T267	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T257	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	26	1			T28	3		T75	1		T77	1
class_index[0x2]	intr_timeout_cnt[1]	10	1			T16	1		T57	1		T80	1
class_index[0x2]	intr_timeout_cnt[2]	6	1			T26	1		T59	1		T114	2
class_index[0x2]	intr_timeout_cnt[3]	5	1			T81	1		T59	1		T89	1
class_index[0x2]	intr_timeout_cnt[5]	3	1			T65	1		T268	1		T266	1
class_index[0x2]	intr_timeout_cnt[6]	1	1			T269	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	2	1			T227	1		T96	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	2	1			T93	2		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	25	1			T16	1		T26	1		T55	2
class_index[0x3]	intr_timeout_cnt[1]	13	1			T80	1		T270	1		T40	1
class_index[0x3]	intr_timeout_cnt[2]	4	1			T82	1		T89	1		T271	1
class_index[0x3]	intr_timeout_cnt[3]	1	1			T179	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[4]	2	1			T96	1		T272	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	1	1			T273	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[6]	9	1			T54	3		T81	1		T268	1
class_index[0x3]	intr_timeout_cnt[7]	6	1			T76	1		T272	1		T258	2
class_index[0x3]	intr_timeout_cnt[8]	6	1			T59	1		T256	2		T259	1
class_index[0x3]	intr_timeout_cnt[9]	2	1			T19	1		T256	1		-	-