Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	364905	1			T1	1239		T2	1851		T3	1853
all_values[1]	364905	1			T1	1239		T2	1851		T3	1853
all_values[2]	364905	1			T1	1239		T2	1851		T3	1853
all_values[3]	364905	1			T1	1239		T2	1851		T3	1853

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

727344

1

T1

2523

T2

3709

T3

3788

auto[1]

732276

1

T1

2433

T2

3695

T3

3624

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

871013

1

T1

3621

T2

6709

T3

3749

auto[1]

588607

1

T1

1335

T2

695

T3

3663

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	103259	1			T1	374		T2	913		T3	478
all_values[0]	auto[0]	auto[1]	79016	1			T1	240		T2	1		T3	476
all_values[0]	auto[1]	auto[0]	104045	1			T1	384		T2	936		T3	453
all_values[0]	auto[1]	auto[1]	78585	1			T1	241		T2	1		T3	446
all_values[1]	auto[0]	auto[0]	110084	1			T1	611		T2	931		T3	501
all_values[1]	auto[0]	auto[1]	71357	1			T2	1		T3	471		T14	8
all_values[1]	auto[1]	auto[0]	111467	1			T1	626		T2	916		T3	463
all_values[1]	auto[1]	auto[1]	71997	1			T1	2		T2	3		T3	418
all_values[2]	auto[0]	auto[0]	109856	1			T1	374		T2	580		T3	489
all_values[2]	auto[0]	auto[1]	71795	1			T1	286		T2	333		T3	489
all_values[2]	auto[1]	auto[0]	111540	1			T1	328		T2	588		T3	438
all_values[2]	auto[1]	auto[1]	71714	1			T1	251		T2	350		T3	437
all_values[3]	auto[0]	auto[0]	109967	1			T1	478		T2	946		T3	442
all_values[3]	auto[0]	auto[1]	72010	1			T1	160		T2	4		T3	442
all_values[3]	auto[1]	auto[0]	110795	1			T1	446		T2	899		T3	485
all_values[3]	auto[1]	auto[1]	72133	1			T1	155		T2	2		T3	484