Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	364905	1			T1	1239		T2	1851		T3	1853
all_pins[1]	364905	1			T1	1239		T2	1851		T3	1853
all_pins[2]	364905	1			T1	1239		T2	1851		T3	1853
all_pins[3]	364905	1			T1	1239		T2	1851		T3	1853

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1165191	1			T1	4307		T2	7048		T3	5627
values[0x1]	294429	1			T1	649		T2	356		T3	1785
transitions[0x0=>0x1]	196782	1			T1	577		T2	352		T3	1173
transitions[0x1=>0x0]	197054	1			T1	578		T2	352		T3	1173

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	286320	1			T1	998		T2	1850		T3	1407
all_pins[0]	values[0x1]	78585	1			T1	241		T2	1		T3	446
all_pins[0]	transitions[0x0=>0x1]	77923	1			T1	240		T2	1		T3	446
all_pins[0]	transitions[0x1=>0x0]	71743	1			T1	155		T2	2		T3	484
all_pins[1]	values[0x0]	292908	1			T1	1237		T2	1848		T3	1435
all_pins[1]	values[0x1]	71997	1			T1	2		T2	3		T3	418
all_pins[1]	transitions[0x0=>0x1]	39367	1			T2	3		T3	212		T14	4
all_pins[1]	transitions[0x1=>0x0]	45955	1			T1	239		T2	1		T3	240
all_pins[2]	values[0x0]	293191	1			T1	988		T2	1501		T3	1416
all_pins[2]	values[0x1]	71714	1			T1	251		T2	350		T3	437
all_pins[2]	transitions[0x0=>0x1]	39555	1			T1	249		T2	348		T3	254
all_pins[2]	transitions[0x1=>0x0]	39838	1			T2	1		T3	235		T14	2
all_pins[3]	values[0x0]	292772	1			T1	1084		T2	1849		T3	1369
all_pins[3]	values[0x1]	72133	1			T1	155		T2	2		T3	484
all_pins[3]	transitions[0x0=>0x1]	39937	1			T1	88		T3	261		T4	20
all_pins[3]	transitions[0x1=>0x0]	39518	1			T1	184		T2	348		T3	214