Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	287	1			T162	4		T163	7		T235	7
all_values[1]	287	1			T162	4		T163	7		T235	7
all_values[2]	287	1			T162	4		T163	7		T235	7
all_values[3]	287	1			T162	4		T163	7		T235	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

662

1

T162

12

T163

22

T235

16

auto[1]

486

1

T162

4

T163

6

T235

12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

452

1

T162

9

T163

17

T235

8

auto[1]

696

1

T162

7

T163

11

T235

20

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

682

1

T162

10

T163

20

T235

15

auto[1]

466

1

T162

6

T163

8

T235

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

64

1

T163

1

T235

2

T329

1

all_values[0]

auto[0]

auto[0]

auto[1]

36

1

T162

1

T163

1

T236

1

all_values[0]

auto[0]

auto[1]

auto[0]

35

1

T163

1

T330

2

T331

2

all_values[0]

auto[0]

auto[1]

auto[1]

26

1

T163

1

T332

1

T333

1

all_values[0]

auto[1]

auto[0]

auto[1]

66

1

T162

2

T163

3

T236

3

all_values[0]

auto[1]

auto[1]

auto[1]

60

1

T162

1

T235

5

T330

2

all_values[1]

auto[0]

auto[0]

auto[0]

71

1

T162

2

T163

4

T235

1

all_values[1]

auto[0]

auto[0]

auto[1]

34

1

T163

1

T235

2

T329

1

all_values[1]

auto[0]

auto[1]

auto[0]

43

1

T236

1

T330

1

T331

2

all_values[1]

auto[0]

auto[1]

auto[1]

31

1

T235

1

T334

1

T332

1

all_values[1]

auto[1]

auto[0]

auto[1]

66

1

T162

2

T163

2

T235

3

all_values[1]

auto[1]

auto[1]

auto[1]

42

1

T236

2

T334

2

T335

2

all_values[2]

auto[0]

auto[0]

auto[0]

72

1

T162

2

T163

5

T235

2

all_values[2]

auto[0]

auto[0]

auto[1]

24

1

T235

1

T330

2

T334

1

all_values[2]

auto[0]

auto[1]

auto[0]

59

1

T162

1

T163

1

T236

2

all_values[2]

auto[0]

auto[1]

auto[1]

23

1

T235

2

T330

1

T331

1

all_values[2]

auto[1]

auto[0]

auto[1]

60

1

T162

1

T163

1

T235

2

all_values[2]

auto[1]

auto[1]

auto[1]

49

1

T329

1

T330

3

T331

1

all_values[3]

auto[0]

auto[0]

auto[0]

64

1

T162

2

T163

2

T236

1

all_values[3]

auto[0]

auto[0]

auto[1]

30

1

T235

1

T330

2

T331

3

all_values[3]

auto[0]

auto[1]

auto[0]

44

1

T162

2

T163

3

T235

3

all_values[3]

auto[0]

auto[1]

auto[1]

26

1

T329

1

T330

2

T336

2

all_values[3]

auto[1]

auto[0]

auto[1]

75

1

T163

2

T235

2

T236

1

all_values[3]

auto[1]

auto[1]

auto[1]

48

1

T235

1

T330

1

T336

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal