Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	93432	1			T3	1659		T16	1173		T11	509
accum_cnt_1000	225117	1			T1	2220		T3	1510		T16	2774
accum_cnt_100	27787	1			T1	311		T3	91		T16	299
accum_cnt_50	73270	1			T1	236		T3	61		T4	16
accum_cnt_10	194209	1			T1	73		T2	4177		T3	1412
accum_cnt_0	419741	1			T1	976		T2	1415		T3	11

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	269258	1			T1	954		T2	1398		T3	1390
class_index[0x1]	269258	1			T1	954		T2	1398		T3	1390
class_index[0x2]	269258	1			T1	954		T2	1398		T3	1390
class_index[0x3]	269258	1			T1	954		T2	1398		T3	1390

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	28825	1			T3	629		T11	509		T46	435
class_index[0x0]	accum_cnt_1000	67228	1			T1	772		T3	564		T16	417
class_index[0x0]	accum_cnt_100	8910	1			T1	74		T3	34		T16	73
class_index[0x0]	accum_cnt_50	17465	1			T1	79		T3	24		T14	9
class_index[0x0]	accum_cnt_10	41343	1			T1	23		T3	7		T14	12
class_index[0x0]	accum_cnt_0	90148	1			T1	6		T2	1398		T3	4
class_index[0x1]	accum_cnt_2000	20636	1			T46	88		T22	78		T23	1
class_index[0x1]	accum_cnt_1000	59003	1			T16	223		T42	7		T12	1249
class_index[0x1]	accum_cnt_100	6160	1			T16	81		T42	28		T12	80
class_index[0x1]	accum_cnt_50	19710	1			T16	1306		T42	23		T12	76
class_index[0x1]	accum_cnt_10	49931	1			T1	1		T2	1394		T3	1390
class_index[0x1]	accum_cnt_0	106111	1			T1	953		T2	4		T4	41
class_index[0x2]	accum_cnt_2000	21918	1			T3	587		T16	530		T22	250
class_index[0x2]	accum_cnt_1000	47357	1			T1	804		T3	538		T16	851
class_index[0x2]	accum_cnt_100	5048	1			T1	75		T3	31		T16	46
class_index[0x2]	accum_cnt_50	18246	1			T1	52		T3	23		T16	44
class_index[0x2]	accum_cnt_10	50147	1			T1	17		T2	1392		T3	9
class_index[0x2]	accum_cnt_0	115012	1			T1	6		T2	6		T3	3
class_index[0x3]	accum_cnt_2000	22053	1			T3	443		T16	643		T47	589
class_index[0x3]	accum_cnt_1000	51529	1			T1	644		T3	408		T16	1283
class_index[0x3]	accum_cnt_100	7669	1			T1	162		T3	26		T16	99
class_index[0x3]	accum_cnt_50	17849	1			T1	105		T3	14		T4	16
class_index[0x3]	accum_cnt_10	52788	1			T1	32		T2	1391		T3	6
class_index[0x3]	accum_cnt_0	108470	1			T1	11		T2	7		T3	4