Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	10784	1			T4	2		T28	6		T118	22
alert[0x1]	6435	1			T19	36		T118	239		T55	641
alert[0x2]	4835	1			T16	11		T6	1		T46	1
alert[0x3]	8475	1			T5	1		T23	5		T118	2472
alert[0x4]	6397	1			T6	1		T28	18		T118	30
alert[0x5]	6671	1			T4	1		T5	1		T6	2
alert[0x6]	7408	1			T16	1		T5	1		T49	57
alert[0x7]	10652	1			T6	1		T48	1		T49	2
alert[0x8]	4593	1			T5	1		T85	1		T26	210
alert[0x9]	4869	1			T4	1		T6	1		T240	1
alert[0xa]	16132	1			T6	1		T49	5		T55	4
alert[0xb]	5713	1			T5	1		T24	17		T28	6
alert[0xc]	5013	1			T5	2		T24	241		T52	102
alert[0xd]	10559	1			T46	806		T51	90		T55	16
alert[0xe]	6135	1			T46	295		T118	1687		T26	185
alert[0xf]	4963	1			T46	1		T24	36		T57	84
alert[0x10]	8303	1			T46	9		T24	85		T69	6
alert[0x11]	5905	1			T4	1		T6	1		T49	3
alert[0x12]	6665	1			T5	1		T6	1		T46	101
alert[0x13]	4496	1			T46	52		T24	10		T28	5
alert[0x14]	7996	1			T240	1		T51	56		T118	89
alert[0x15]	15272	1			T46	1025		T49	2		T28	38
alert[0x16]	5699	1			T4	1		T10	1		T46	27
alert[0x17]	10525	1			T4	2		T12	1		T46	305
alert[0x18]	3967	1			T49	1		T51	51		T118	43
alert[0x19]	7810	1			T16	53		T12	1		T5	1
alert[0x1a]	5571	1			T46	198		T73	2		T52	143
alert[0x1b]	16704	1			T46	6		T28	53		T55	2656
alert[0x1c]	10322	1			T46	218		T24	174		T118	87
alert[0x1d]	5059	1			T24	82		T52	7		T75	1
alert[0x1e]	6963	1			T4	1		T12	1		T6	1
alert[0x1f]	5259	1			T4	1		T12	1		T46	33
alert[0x20]	5676	1			T16	6		T24	24		T28	2
alert[0x21]	3748	1			T46	69		T49	1		T24	1179
alert[0x22]	4062	1			T16	1		T48	1		T49	1
alert[0x23]	13938	1			T4	1		T240	1		T24	211
alert[0x24]	3262	1			T23	5		T52	14		T53	5
alert[0x25]	18265	1			T11	4		T240	1		T118	111
alert[0x26]	16577	1			T19	24		T24	2399		T28	17
alert[0x27]	8051	1			T53	5		T26	3		T30	45
alert[0x28]	12253	1			T2	2		T5	1		T46	156
alert[0x29]	11779	1			T24	36		T51	29		T118	162
alert[0x2a]	6966	1			T4	1		T6	1		T49	7
alert[0x2b]	8332	1			T49	1		T24	4		T22	46
alert[0x2c]	8553	1			T16	8		T5	1		T6	2
alert[0x2d]	9971	1			T4	1		T12	1		T5	1
alert[0x2e]	4146	1			T46	718		T55	341		T101	1
alert[0x2f]	3238	1			T1	1		T6	1		T51	22
alert[0x30]	9743	1			T1	1		T16	3		T5	1
alert[0x31]	3523	1			T6	1		T240	1		T19	2
alert[0x32]	8522	1			T5	1		T6	1		T49	1
alert[0x33]	4896	1			T4	1		T19	4		T28	22
alert[0x34]	3845	1			T4	1		T5	1		T240	1
alert[0x35]	3605	1			T4	1		T6	1		T46	29
alert[0x36]	5425	1			T5	1		T6	1		T46	21
alert[0x37]	3444	1			T5	2		T6	1		T28	32
alert[0x38]	5362	1			T6	1		T22	277		T118	67
alert[0x39]	10894	1			T5	1		T46	18		T240	1
alert[0x3a]	2825	1			T11	6		T5	1		T24	17
alert[0x3b]	10454	1			T4	1		T28	292		T118	960
alert[0x3c]	6169	1			T16	1		T51	11		T118	19
alert[0x3d]	10168	1			T4	1		T118	3		T55	12
alert[0x3e]	7229	1			T4	1		T16	3		T49	9
alert[0x3f]	4268	1			T46	14		T118	92		T54	10
alert[0x40]	8381	1			T4	1		T46	17		T24	26

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	131183	1			T1	2		T16	8		T240	1
class_i[0x1]	58924	1			T16	70		T6	22		T46	59
class_i[0x2]	192964	1			T2	2		T16	1		T11	10
class_i[0x3]	110649	1			T4	20		T16	8		T10	1

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

493018

1

T16

87

T11

10

T46

4681

alert_ping_fail

702

1

T1

2

T2

2

T4

20

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	10772	1			T28	6		T118	22		T52	10
alert_integrity_fail	alert[0x1]	6429	1			T19	36		T118	239		T55	641
alert_integrity_fail	alert[0x2]	4826	1			T16	11		T46	1		T49	9
alert_integrity_fail	alert[0x3]	8462	1			T23	5		T118	2472		T76	9
alert_integrity_fail	alert[0x4]	6390	1			T28	18		T118	30		T55	10
alert_integrity_fail	alert[0x5]	6656	1			T46	34		T24	55		T28	18
alert_integrity_fail	alert[0x6]	7391	1			T16	1		T49	57		T26	1685
alert_integrity_fail	alert[0x7]	10639	1			T49	2		T51	1015		T52	1
alert_integrity_fail	alert[0x8]	4577	1			T26	210		T75	33		T58	155
alert_integrity_fail	alert[0x9]	4856	1			T118	202		T26	47		T69	12
alert_integrity_fail	alert[0xa]	16115	1			T49	5		T55	4		T58	683
alert_integrity_fail	alert[0xb]	5703	1			T24	17		T28	6		T51	13
alert_integrity_fail	alert[0xc]	5006	1			T24	241		T52	102		T55	6
alert_integrity_fail	alert[0xd]	10551	1			T46	806		T51	90		T55	16
alert_integrity_fail	alert[0xe]	6124	1			T46	295		T118	1687		T26	185
alert_integrity_fail	alert[0xf]	4957	1			T46	1		T24	36		T57	84
alert_integrity_fail	alert[0x10]	8291	1			T46	9		T24	85		T69	6
alert_integrity_fail	alert[0x11]	5896	1			T49	3		T118	277		T26	1
alert_integrity_fail	alert[0x12]	6658	1			T46	101		T24	10		T118	26
alert_integrity_fail	alert[0x13]	4479	1			T46	52		T24	10		T28	5
alert_integrity_fail	alert[0x14]	7977	1			T51	56		T118	89		T53	2
alert_integrity_fail	alert[0x15]	15261	1			T46	1025		T49	2		T28	38
alert_integrity_fail	alert[0x16]	5685	1			T46	27		T118	487		T26	83
alert_integrity_fail	alert[0x17]	10513	1			T46	305		T24	5		T28	4
alert_integrity_fail	alert[0x18]	3957	1			T49	1		T51	51		T118	43
alert_integrity_fail	alert[0x19]	7799	1			T16	53		T49	10		T28	192
alert_integrity_fail	alert[0x1a]	5554	1			T46	198		T73	2		T52	143
alert_integrity_fail	alert[0x1b]	16691	1			T46	6		T28	53		T55	2656
alert_integrity_fail	alert[0x1c]	10314	1			T46	218		T24	174		T118	87
alert_integrity_fail	alert[0x1d]	5051	1			T24	82		T52	7		T75	1
alert_integrity_fail	alert[0x1e]	6952	1			T19	1		T24	30		T118	86
alert_integrity_fail	alert[0x1f]	5251	1			T46	33		T49	6		T52	19
alert_integrity_fail	alert[0x20]	5673	1			T16	6		T24	24		T28	2
alert_integrity_fail	alert[0x21]	3740	1			T46	69		T49	1		T24	1179
alert_integrity_fail	alert[0x22]	4052	1			T16	1		T49	1		T118	219
alert_integrity_fail	alert[0x23]	13925	1			T24	211		T28	15		T51	2
alert_integrity_fail	alert[0x24]	3250	1			T23	5		T52	14		T53	5
alert_integrity_fail	alert[0x25]	18253	1			T11	4		T118	111		T55	3
alert_integrity_fail	alert[0x26]	16567	1			T19	24		T24	2399		T28	17
alert_integrity_fail	alert[0x27]	8042	1			T53	5		T26	3		T30	45
alert_integrity_fail	alert[0x28]	12241	1			T46	156		T28	29		T53	14
alert_integrity_fail	alert[0x29]	11775	1			T24	36		T51	29		T118	162
alert_integrity_fail	alert[0x2a]	6959	1			T49	7		T28	1		T51	124
alert_integrity_fail	alert[0x2b]	8328	1			T49	1		T24	4		T22	46
alert_integrity_fail	alert[0x2c]	8540	1			T16	8		T28	48		T52	1
alert_integrity_fail	alert[0x2d]	9953	1			T69	128		T30	66		T77	9
alert_integrity_fail	alert[0x2e]	4131	1			T46	718		T55	341		T30	83
alert_integrity_fail	alert[0x2f]	3229	1			T51	22		T118	81		T26	65
alert_integrity_fail	alert[0x30]	9730	1			T16	3		T46	528		T118	697
alert_integrity_fail	alert[0x31]	3514	1			T19	2		T73	2		T52	2
alert_integrity_fail	alert[0x32]	8515	1			T49	1		T19	1		T73	1
alert_integrity_fail	alert[0x33]	4885	1			T19	4		T28	22		T118	4
alert_integrity_fail	alert[0x34]	3832	1			T49	2		T24	146		T28	13
alert_integrity_fail	alert[0x35]	3594	1			T46	29		T24	38		T118	230
alert_integrity_fail	alert[0x36]	5415	1			T46	21		T24	63		T51	12
alert_integrity_fail	alert[0x37]	3428	1			T28	32		T118	149		T69	43
alert_integrity_fail	alert[0x38]	5353	1			T22	277		T118	67		T53	55
alert_integrity_fail	alert[0x39]	10879	1			T46	18		T118	31		T55	4
alert_integrity_fail	alert[0x3a]	2811	1			T11	6		T24	17		T28	83
alert_integrity_fail	alert[0x3b]	10443	1			T28	292		T118	960		T52	87
alert_integrity_fail	alert[0x3c]	6159	1			T16	1		T51	11		T118	19
alert_integrity_fail	alert[0x3d]	10158	1			T118	3		T55	12		T30	1
alert_integrity_fail	alert[0x3e]	7221	1			T16	3		T49	9		T118	469
alert_integrity_fail	alert[0x3f]	4262	1			T46	14		T118	92		T54	10
alert_integrity_fail	alert[0x40]	8378	1			T46	17		T24	26		T23	55
alert_ping_fail	alert[0x0]	12	1			T4	2		T102	1		T290	1
alert_ping_fail	alert[0x1]	6	1			T291	1		T101	1		T292	1
alert_ping_fail	alert[0x2]	9	1			T6	1		T240	1		T291	1
alert_ping_fail	alert[0x3]	13	1			T5	1		T291	1		T232	1
alert_ping_fail	alert[0x4]	7	1			T6	1		T67	1		T291	1
alert_ping_fail	alert[0x5]	15	1			T4	1		T5	1		T6	2
alert_ping_fail	alert[0x6]	17	1			T5	1		T101	1		T293	2
alert_ping_fail	alert[0x7]	13	1			T6	1		T48	1		T101	1
alert_ping_fail	alert[0x8]	16	1			T5	1		T85	1		T101	1
alert_ping_fail	alert[0x9]	13	1			T4	1		T6	1		T240	1
alert_ping_fail	alert[0xa]	17	1			T6	1		T101	1		T95	2
alert_ping_fail	alert[0xb]	10	1			T5	1		T217	1		T294	1
alert_ping_fail	alert[0xc]	7	1			T5	2		T232	1		T295	1
alert_ping_fail	alert[0xd]	8	1			T39	1		T293	1		T292	1
alert_ping_fail	alert[0xe]	11	1			T101	1		T217	1		T294	1
alert_ping_fail	alert[0xf]	6	1			T232	1		T39	1		T296	1
alert_ping_fail	alert[0x10]	12	1			T102	1		T217	1		T39	1
alert_ping_fail	alert[0x11]	9	1			T4	1		T6	1		T293	1
alert_ping_fail	alert[0x12]	7	1			T5	1		T6	1		T229	1
alert_ping_fail	alert[0x13]	17	1			T67	1		T94	1		T232	1
alert_ping_fail	alert[0x14]	19	1			T240	1		T67	1		T297	1
alert_ping_fail	alert[0x15]	11	1			T298	1		T294	1		T229	1
alert_ping_fail	alert[0x16]	14	1			T4	1		T10	1		T67	1
alert_ping_fail	alert[0x17]	12	1			T4	2		T12	1		T101	1
alert_ping_fail	alert[0x18]	10	1			T294	2		T299	1		T300	1
alert_ping_fail	alert[0x19]	11	1			T12	1		T5	1		T6	1
alert_ping_fail	alert[0x1a]	17	1			T291	2		T217	1		T293	1
alert_ping_fail	alert[0x1b]	13	1			T101	1		T102	1		T95	2
alert_ping_fail	alert[0x1c]	8	1			T217	1		T232	1		T301	1
alert_ping_fail	alert[0x1d]	8	1			T229	1		T292	1		T302	2
alert_ping_fail	alert[0x1e]	11	1			T4	1		T12	1		T6	1
alert_ping_fail	alert[0x1f]	8	1			T4	1		T12	1		T297	1
alert_ping_fail	alert[0x20]	3	1			T292	1		T303	1		T304	1
alert_ping_fail	alert[0x21]	8	1			T95	1		T290	1		T280	1
alert_ping_fail	alert[0x22]	10	1			T48	1		T39	1		T305	1
alert_ping_fail	alert[0x23]	13	1			T4	1		T240	1		T102	1
alert_ping_fail	alert[0x24]	12	1			T101	1		T102	1		T298	1
alert_ping_fail	alert[0x25]	12	1			T240	1		T291	1		T217	1
alert_ping_fail	alert[0x26]	10	1			T101	1		T217	1		T293	1
alert_ping_fail	alert[0x27]	9	1			T217	2		T294	1		T39	2
alert_ping_fail	alert[0x28]	12	1			T2	2		T5	1		T67	1
alert_ping_fail	alert[0x29]	4	1			T295	1		T290	1		T303	1
alert_ping_fail	alert[0x2a]	7	1			T4	1		T6	1		T290	1
alert_ping_fail	alert[0x2b]	4	1			T39	1		T306	1		T307	2
alert_ping_fail	alert[0x2c]	13	1			T5	1		T6	2		T291	1
alert_ping_fail	alert[0x2d]	18	1			T4	1		T12	1		T5	1
alert_ping_fail	alert[0x2e]	15	1			T101	1		T308	1		T299	1
alert_ping_fail	alert[0x2f]	9	1			T1	1		T6	1		T291	1
alert_ping_fail	alert[0x30]	13	1			T1	1		T5	1		T6	1
alert_ping_fail	alert[0x31]	9	1			T6	1		T240	1		T102	1
alert_ping_fail	alert[0x32]	7	1			T5	1		T6	1		T280	1
alert_ping_fail	alert[0x33]	11	1			T4	1		T229	1		T232	1
alert_ping_fail	alert[0x34]	13	1			T4	1		T5	1		T240	1
alert_ping_fail	alert[0x35]	11	1			T4	1		T6	1		T232	1
alert_ping_fail	alert[0x36]	10	1			T5	1		T6	1		T217	1
alert_ping_fail	alert[0x37]	16	1			T5	2		T6	1		T294	1
alert_ping_fail	alert[0x38]	9	1			T6	1		T67	1		T101	1
alert_ping_fail	alert[0x39]	15	1			T5	1		T240	1		T101	1
alert_ping_fail	alert[0x3a]	14	1			T5	1		T291	3		T101	1
alert_ping_fail	alert[0x3b]	11	1			T4	1		T291	1		T102	2
alert_ping_fail	alert[0x3c]	10	1			T229	2		T232	1		T295	1
alert_ping_fail	alert[0x3d]	10	1			T4	1		T67	1		T294	1
alert_ping_fail	alert[0x3e]	8	1			T4	1		T101	1		T232	1
alert_ping_fail	alert[0x3f]	6	1			T102	1		T290	1		T292	1
alert_ping_fail	alert[0x40]	3	1			T4	1		T306	1		T309	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	130962	1			T16	8		T49	117		T19	6
alert_integrity_fail	class_i[0x1]	58755	1			T16	70		T46	59		T19	10
alert_integrity_fail	class_i[0x2]	192794	1			T16	1		T11	10		T19	38
alert_integrity_fail	class_i[0x3]	110507	1			T16	8		T46	4622		T19	14
alert_ping_fail	class_i[0x0]	221	1			T1	2		T240	1		T67	1
alert_ping_fail	class_i[0x1]	169	1			T6	22		T67	2		T291	3
alert_ping_fail	class_i[0x2]	170	1			T2	2		T12	5		T5	19
alert_ping_fail	class_i[0x3]	142	1			T4	20		T10	1		T5	1