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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.99 98.66 100.00 100.00 100.00 99.38 99.40


Total test records in report: 831
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T176 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.4050435822 Jun 06 03:11:38 PM PDT 24 Jun 06 03:12:21 PM PDT 24 926607438 ps
T142 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3682695205 Jun 06 03:10:40 PM PDT 24 Jun 06 03:12:12 PM PDT 24 886974269 ps
T767 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1441001492 Jun 06 03:13:28 PM PDT 24 Jun 06 03:13:30 PM PDT 24 15851453 ps
T768 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2392740217 Jun 06 03:18:10 PM PDT 24 Jun 06 03:18:15 PM PDT 24 12927348 ps
T769 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2827965559 Jun 06 03:11:23 PM PDT 24 Jun 06 03:20:03 PM PDT 24 17813105914 ps
T770 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2437056545 Jun 06 03:10:27 PM PDT 24 Jun 06 03:10:35 PM PDT 24 40379923 ps
T771 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.926801242 Jun 06 03:15:40 PM PDT 24 Jun 06 03:16:05 PM PDT 24 176940763 ps
T772 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2722442790 Jun 06 03:13:28 PM PDT 24 Jun 06 03:13:36 PM PDT 24 110052782 ps
T157 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.4237675408 Jun 06 03:11:01 PM PDT 24 Jun 06 03:20:19 PM PDT 24 25398965914 ps
T773 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.208550739 Jun 06 03:11:37 PM PDT 24 Jun 06 03:19:21 PM PDT 24 8920639327 ps
T774 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3924758048 Jun 06 03:17:16 PM PDT 24 Jun 06 03:17:30 PM PDT 24 379660788 ps
T775 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.982874129 Jun 06 03:11:01 PM PDT 24 Jun 06 03:11:09 PM PDT 24 63280180 ps
T776 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2680371679 Jun 06 03:11:44 PM PDT 24 Jun 06 03:11:51 PM PDT 24 188307507 ps
T777 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.188568342 Jun 06 03:17:35 PM PDT 24 Jun 06 03:17:39 PM PDT 24 12339485 ps
T778 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.258795097 Jun 06 03:12:14 PM PDT 24 Jun 06 03:12:30 PM PDT 24 732347067 ps
T779 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2840881261 Jun 06 03:13:16 PM PDT 24 Jun 06 03:13:32 PM PDT 24 184792337 ps
T147 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3919677864 Jun 06 03:12:31 PM PDT 24 Jun 06 03:16:38 PM PDT 24 2224996297 ps
T780 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1322954590 Jun 06 03:11:03 PM PDT 24 Jun 06 03:15:55 PM PDT 24 17302685173 ps
T781 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.4111339614 Jun 06 03:16:18 PM PDT 24 Jun 06 03:16:24 PM PDT 24 34924700 ps
T782 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1159074503 Jun 06 03:12:58 PM PDT 24 Jun 06 03:13:14 PM PDT 24 1364524681 ps
T783 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3429001974 Jun 06 03:11:03 PM PDT 24 Jun 06 03:11:06 PM PDT 24 10473003 ps
T784 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2759759611 Jun 06 03:18:40 PM PDT 24 Jun 06 03:18:43 PM PDT 24 30491586 ps
T155 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2676015998 Jun 06 03:14:09 PM PDT 24 Jun 06 03:16:55 PM PDT 24 3610892283 ps
T785 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2765858381 Jun 06 03:11:23 PM PDT 24 Jun 06 03:11:32 PM PDT 24 183223466 ps
T786 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.398588807 Jun 06 03:11:22 PM PDT 24 Jun 06 03:11:27 PM PDT 24 110847410 ps
T787 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.892606231 Jun 06 03:15:18 PM PDT 24 Jun 06 03:15:30 PM PDT 24 454746462 ps
T788 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1867610490 Jun 06 03:17:59 PM PDT 24 Jun 06 03:18:03 PM PDT 24 6357372 ps
T789 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2596643694 Jun 06 03:14:56 PM PDT 24 Jun 06 03:14:58 PM PDT 24 15328750 ps
T152 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1457978472 Jun 06 03:11:51 PM PDT 24 Jun 06 03:18:33 PM PDT 24 20684935867 ps
T790 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2650443741 Jun 06 03:10:28 PM PDT 24 Jun 06 03:10:33 PM PDT 24 228140578 ps
T791 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1354061782 Jun 06 03:11:47 PM PDT 24 Jun 06 03:11:53 PM PDT 24 63450554 ps
T792 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3710164834 Jun 06 03:12:24 PM PDT 24 Jun 06 03:12:26 PM PDT 24 6816180 ps
T793 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1108334782 Jun 06 03:15:01 PM PDT 24 Jun 06 03:15:17 PM PDT 24 388078505 ps
T794 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.284506771 Jun 06 03:17:50 PM PDT 24 Jun 06 03:17:53 PM PDT 24 12758486 ps
T795 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2463248929 Jun 06 03:11:41 PM PDT 24 Jun 06 03:11:44 PM PDT 24 12077786 ps
T340 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1222778834 Jun 06 03:14:57 PM PDT 24 Jun 06 03:31:22 PM PDT 24 52644068582 ps
T175 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3864296295 Jun 06 03:16:01 PM PDT 24 Jun 06 03:16:07 PM PDT 24 89254461 ps
T796 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1709534011 Jun 06 03:18:00 PM PDT 24 Jun 06 03:18:03 PM PDT 24 27004824 ps
T797 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.4156322818 Jun 06 03:11:03 PM PDT 24 Jun 06 03:11:09 PM PDT 24 123063607 ps
T798 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2682298478 Jun 06 03:10:27 PM PDT 24 Jun 06 03:17:19 PM PDT 24 22865154245 ps
T153 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2292417144 Jun 06 03:13:18 PM PDT 24 Jun 06 03:15:52 PM PDT 24 14507100906 ps
T799 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3502183566 Jun 06 03:16:57 PM PDT 24 Jun 06 03:17:13 PM PDT 24 95366293 ps
T151 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3621419237 Jun 06 03:16:32 PM PDT 24 Jun 06 03:18:42 PM PDT 24 1360775663 ps
T800 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1874266559 Jun 06 03:14:56 PM PDT 24 Jun 06 03:15:02 PM PDT 24 50388897 ps
T801 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2374603306 Jun 06 03:15:40 PM PDT 24 Jun 06 03:15:55 PM PDT 24 291875701 ps
T802 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3442227780 Jun 06 03:11:50 PM PDT 24 Jun 06 03:12:17 PM PDT 24 619506835 ps
T803 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1287530612 Jun 06 03:18:10 PM PDT 24 Jun 06 03:18:14 PM PDT 24 11305422 ps
T168 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2738291310 Jun 06 03:10:39 PM PDT 24 Jun 06 03:10:44 PM PDT 24 44728083 ps
T804 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1344868181 Jun 06 03:18:36 PM PDT 24 Jun 06 03:18:39 PM PDT 24 8109925 ps
T805 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3875313167 Jun 06 03:16:51 PM PDT 24 Jun 06 03:17:25 PM PDT 24 466320626 ps
T806 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2726564631 Jun 06 03:17:59 PM PDT 24 Jun 06 03:18:03 PM PDT 24 10250081 ps
T807 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3427218049 Jun 06 03:15:43 PM PDT 24 Jun 06 03:15:49 PM PDT 24 753645957 ps
T808 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2996057584 Jun 06 03:16:13 PM PDT 24 Jun 06 03:16:15 PM PDT 24 11483863 ps
T809 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.4165133010 Jun 06 03:10:26 PM PDT 24 Jun 06 03:10:29 PM PDT 24 7624797 ps
T810 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.920258247 Jun 06 03:12:47 PM PDT 24 Jun 06 03:13:14 PM PDT 24 177339235 ps
T170 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2303912718 Jun 06 03:11:37 PM PDT 24 Jun 06 03:13:03 PM PDT 24 3693702761 ps
T811 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3353759755 Jun 06 03:10:39 PM PDT 24 Jun 06 03:10:48 PM PDT 24 101480146 ps
T812 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.990729537 Jun 06 03:17:01 PM PDT 24 Jun 06 03:17:24 PM PDT 24 1043305676 ps
T813 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2237674327 Jun 06 03:18:36 PM PDT 24 Jun 06 03:18:39 PM PDT 24 7501014 ps
T814 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.4095478988 Jun 06 03:15:17 PM PDT 24 Jun 06 03:15:31 PM PDT 24 298911506 ps
T815 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2174287711 Jun 06 03:11:39 PM PDT 24 Jun 06 03:11:43 PM PDT 24 7812879 ps
T143 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.111685300 Jun 06 03:14:42 PM PDT 24 Jun 06 03:16:39 PM PDT 24 2922429074 ps
T816 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.4077341566 Jun 06 03:15:29 PM PDT 24 Jun 06 03:15:42 PM PDT 24 1350521282 ps
T817 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.549395683 Jun 06 03:14:19 PM PDT 24 Jun 06 03:14:22 PM PDT 24 12030754 ps
T818 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3057246140 Jun 06 03:17:59 PM PDT 24 Jun 06 03:18:02 PM PDT 24 21871632 ps
T819 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.467294183 Jun 06 03:18:41 PM PDT 24 Jun 06 03:18:43 PM PDT 24 16414887 ps
T167 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.4170850052 Jun 06 03:12:22 PM PDT 24 Jun 06 03:12:28 PM PDT 24 111052731 ps
T820 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.897556939 Jun 06 03:12:12 PM PDT 24 Jun 06 03:12:30 PM PDT 24 1471525519 ps
T821 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.856798667 Jun 06 03:16:45 PM PDT 24 Jun 06 03:16:52 PM PDT 24 111152926 ps
T154 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1808263818 Jun 06 03:15:52 PM PDT 24 Jun 06 03:18:16 PM PDT 24 7290442108 ps
T822 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2314584259 Jun 06 03:17:34 PM PDT 24 Jun 06 03:17:37 PM PDT 24 45311701 ps
T823 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.723607650 Jun 06 03:15:16 PM PDT 24 Jun 06 03:17:04 PM PDT 24 809892110 ps
T824 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.4175862174 Jun 06 03:18:50 PM PDT 24 Jun 06 03:18:53 PM PDT 24 6707506 ps
T825 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3940936810 Jun 06 03:13:27 PM PDT 24 Jun 06 03:13:49 PM PDT 24 229917672 ps
T826 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1092368095 Jun 06 03:11:41 PM PDT 24 Jun 06 03:11:51 PM PDT 24 55248467 ps
T827 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.4093151905 Jun 06 03:12:32 PM PDT 24 Jun 06 03:12:36 PM PDT 24 24434246 ps
T828 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1821849226 Jun 06 03:17:35 PM PDT 24 Jun 06 03:17:39 PM PDT 24 14073005 ps
T829 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1742493890 Jun 06 03:12:22 PM PDT 24 Jun 06 03:12:31 PM PDT 24 184618981 ps
T156 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1942208444 Jun 06 03:11:23 PM PDT 24 Jun 06 03:18:37 PM PDT 24 6421828108 ps
T830 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1209044106 Jun 06 03:16:59 PM PDT 24 Jun 06 03:17:12 PM PDT 24 270927690 ps
T831 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2024219729 Jun 06 03:16:32 PM PDT 24 Jun 06 03:16:41 PM PDT 24 81313060 ps

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.944592552
Short name T16
Test name
Test status
Simulation time 189439154467 ps
CPU time 9246.19 seconds
Started Jun 06 03:18:48 PM PDT 24
Finished Jun 06 05:52:58 PM PDT 24
Peak memory 370108 kb
Host smart-54cbe73b-2df3-42e5-af89-82e6286644cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944592552 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.944592552
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.705002490
Short name T13
Test name
Test status
Simulation time 1981928327 ps
CPU time 22.96 seconds
Started Jun 06 03:18:37 PM PDT 24
Finished Jun 06 03:19:02 PM PDT 24
Peak memory 240556 kb
Host smart-7b710ee9-d66d-49ee-8ba5-f1bacb4b2e56
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=705002490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.705002490
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.4228242991
Short name T9
Test name
Test status
Simulation time 1029264877 ps
CPU time 45.72 seconds
Started Jun 06 03:13:55 PM PDT 24
Finished Jun 06 03:14:42 PM PDT 24
Peak memory 277608 kb
Host smart-2f42630b-7133-4bfe-9069-3d2370eb7fb5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4228242991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.4228242991
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.1843277148
Short name T55
Test name
Test status
Simulation time 51667708852 ps
CPU time 2716.59 seconds
Started Jun 06 03:14:57 PM PDT 24
Finished Jun 06 04:00:16 PM PDT 24
Peak memory 305724 kb
Host smart-d6a44278-3b9b-4f01-addc-025c3eefdeb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843277148 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.1843277148
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1280981788
Short name T159
Test name
Test status
Simulation time 3526501425 ps
CPU time 77.48 seconds
Started Jun 06 03:15:54 PM PDT 24
Finished Jun 06 03:17:13 PM PDT 24
Peak memory 239916 kb
Host smart-cbdcf679-9ea5-4959-bf23-12f509bcd6a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1280981788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1280981788
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.1628735463
Short name T22
Test name
Test status
Simulation time 216988171449 ps
CPU time 7097.98 seconds
Started Jun 06 03:26:56 PM PDT 24
Finished Jun 06 05:25:16 PM PDT 24
Peak memory 322080 kb
Host smart-d7c88a49-0b1a-4186-ad71-5c74db1bd205
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628735463 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.1628735463
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.3668132347
Short name T2
Test name
Test status
Simulation time 52424652260 ps
CPU time 2922.83 seconds
Started Jun 06 03:21:52 PM PDT 24
Finished Jun 06 04:10:37 PM PDT 24
Peak memory 289452 kb
Host smart-fbc3dccf-6a4c-4057-9e7c-66cca6e7659c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668132347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3668132347
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.1835814178
Short name T28
Test name
Test status
Simulation time 28106757046 ps
CPU time 3359.96 seconds
Started Jun 06 03:14:27 PM PDT 24
Finished Jun 06 04:10:28 PM PDT 24
Peak memory 314548 kb
Host smart-eb860d02-1233-45f3-8f24-3cba60cf4c26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835814178 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.1835814178
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.432953554
Short name T126
Test name
Test status
Simulation time 43069380438 ps
CPU time 946.37 seconds
Started Jun 06 03:13:39 PM PDT 24
Finished Jun 06 03:29:27 PM PDT 24
Peak memory 266524 kb
Host smart-6d053701-859c-4f62-83af-5ca9ab78e480
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432953554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.432953554
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.457500425
Short name T59
Test name
Test status
Simulation time 111599395213 ps
CPU time 7932.9 seconds
Started Jun 06 03:22:02 PM PDT 24
Finished Jun 06 05:34:17 PM PDT 24
Peak memory 336672 kb
Host smart-e66af1e4-6618-4c70-b948-de07ad5a0dd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457500425 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.457500425
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1611855183
Short name T57
Test name
Test status
Simulation time 10145682158 ps
CPU time 961.67 seconds
Started Jun 06 03:13:57 PM PDT 24
Finished Jun 06 03:30:00 PM PDT 24
Peak memory 283672 kb
Host smart-d8007e48-0f03-47cc-b6bc-2a14492965a1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611855183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1611855183
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3097837711
Short name T120
Test name
Test status
Simulation time 11029853921 ps
CPU time 350.35 seconds
Started Jun 06 03:10:16 PM PDT 24
Finished Jun 06 03:16:08 PM PDT 24
Peak memory 265480 kb
Host smart-cd1ded69-0ac6-4549-bc07-a08a8d899fbf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3097837711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3097837711
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1175232369
Short name T94
Test name
Test status
Simulation time 117720991853 ps
CPU time 2195.63 seconds
Started Jun 06 03:22:14 PM PDT 24
Finished Jun 06 03:58:51 PM PDT 24
Peak memory 289768 kb
Host smart-26e51111-b73b-4f86-b9d2-d5d14ab6f806
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175232369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1175232369
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.247729897
Short name T135
Test name
Test status
Simulation time 3625044606 ps
CPU time 274.42 seconds
Started Jun 06 03:11:40 PM PDT 24
Finished Jun 06 03:16:17 PM PDT 24
Peak memory 265484 kb
Host smart-432e5b71-5f73-4775-b889-4b8d6572eff5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=247729897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_error
s.247729897
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2922204489
Short name T129
Test name
Test status
Simulation time 15950145323 ps
CPU time 1327.18 seconds
Started Jun 06 03:15:17 PM PDT 24
Finished Jun 06 03:37:25 PM PDT 24
Peak memory 265540 kb
Host smart-1a2bb771-0adf-479e-8e48-6b010f6c0c94
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922204489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.2922204489
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.2232056586
Short name T6
Test name
Test status
Simulation time 62530119352 ps
CPU time 652.65 seconds
Started Jun 06 03:20:30 PM PDT 24
Finished Jun 06 03:31:23 PM PDT 24
Peak memory 247124 kb
Host smart-a47b3f9b-f3ed-416b-be90-e1083b66fbfd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232056586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2232056586
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.616085322
Short name T297
Test name
Test status
Simulation time 81916387552 ps
CPU time 2698.52 seconds
Started Jun 06 03:19:13 PM PDT 24
Finished Jun 06 04:04:14 PM PDT 24
Peak memory 289248 kb
Host smart-6824fdc2-066d-40f2-a5fb-32906b5ea0f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616085322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.616085322
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1924449971
Short name T330
Test name
Test status
Simulation time 9965519 ps
CPU time 1.36 seconds
Started Jun 06 03:17:16 PM PDT 24
Finished Jun 06 03:17:18 PM PDT 24
Peak memory 236072 kb
Host smart-e562e738-225a-4b91-88af-2f172a8ed241
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1924449971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1924449971
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2300649201
Short name T124
Test name
Test status
Simulation time 4242578409 ps
CPU time 667.23 seconds
Started Jun 06 03:13:19 PM PDT 24
Finished Jun 06 03:24:27 PM PDT 24
Peak memory 265492 kb
Host smart-50ff8311-04b1-466d-a468-df4f7ecb985a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300649201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2300649201
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.2372435222
Short name T101
Test name
Test status
Simulation time 55761289176 ps
CPU time 546.13 seconds
Started Jun 06 03:17:09 PM PDT 24
Finished Jun 06 03:26:17 PM PDT 24
Peak memory 247552 kb
Host smart-3206d26b-e2c1-4e4e-b355-f69a5c1ebb5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372435222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.2372435222
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2164220159
Short name T128
Test name
Test status
Simulation time 6599801594 ps
CPU time 205.72 seconds
Started Jun 06 03:12:14 PM PDT 24
Finished Jun 06 03:15:40 PM PDT 24
Peak memory 265504 kb
Host smart-62cb472d-f4d0-4d60-a89b-204716814a9e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2164220159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.2164220159
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1467065199
Short name T118
Test name
Test status
Simulation time 97302916964 ps
CPU time 3081.17 seconds
Started Jun 06 03:27:13 PM PDT 24
Finished Jun 06 04:18:35 PM PDT 24
Peak memory 289044 kb
Host smart-5fe4bfb7-e965-4deb-8743-aa98261233eb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467065199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1467065199
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.3715048450
Short name T4
Test name
Test status
Simulation time 23289619388 ps
CPU time 515.58 seconds
Started Jun 06 03:19:28 PM PDT 24
Finished Jun 06 03:28:05 PM PDT 24
Peak memory 248004 kb
Host smart-eaafe216-220f-4858-bb03-24746cdbf9f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715048450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.3715048450
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.4063326834
Short name T144
Test name
Test status
Simulation time 40561737765 ps
CPU time 1057.35 seconds
Started Jun 06 03:16:50 PM PDT 24
Finished Jun 06 03:34:29 PM PDT 24
Peak memory 273500 kb
Host smart-68f8db3b-5e46-4c1a-9985-c213611af0ac
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063326834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.4063326834
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1821573239
Short name T310
Test name
Test status
Simulation time 214948299112 ps
CPU time 2316.78 seconds
Started Jun 06 03:20:48 PM PDT 24
Finished Jun 06 03:59:26 PM PDT 24
Peak memory 281544 kb
Host smart-037536e8-1d76-4200-9853-6ce45327e892
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821573239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1821573239
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.2807212517
Short name T81
Test name
Test status
Simulation time 167962542342 ps
CPU time 4313.81 seconds
Started Jun 06 03:21:25 PM PDT 24
Finished Jun 06 04:33:20 PM PDT 24
Peak memory 305520 kb
Host smart-ded7e6ce-228c-47bc-a942-58fcd0127c1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807212517 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.2807212517
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2232019001
Short name T134
Test name
Test status
Simulation time 2075186123 ps
CPU time 256.99 seconds
Started Jun 06 03:12:50 PM PDT 24
Finished Jun 06 03:17:08 PM PDT 24
Peak memory 265580 kb
Host smart-88d3233c-6f38-4ecf-8a83-8d5da6fd21b4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2232019001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.2232019001
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.2714299885
Short name T93
Test name
Test status
Simulation time 53102809342 ps
CPU time 3124.99 seconds
Started Jun 06 03:13:19 PM PDT 24
Finished Jun 06 04:05:26 PM PDT 24
Peak memory 289432 kb
Host smart-cd0d6df9-0c39-49d5-ba12-6ae6e0ce9ed4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714299885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.2714299885
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.580724612
Short name T333
Test name
Test status
Simulation time 10681300 ps
CPU time 1.38 seconds
Started Jun 06 03:18:10 PM PDT 24
Finished Jun 06 03:18:14 PM PDT 24
Peak memory 236148 kb
Host smart-5a4d7e33-7dad-475e-86ea-5e2155416b1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=580724612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.580724612
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3250624863
Short name T39
Test name
Test status
Simulation time 74459060183 ps
CPU time 575.47 seconds
Started Jun 06 03:18:47 PM PDT 24
Finished Jun 06 03:28:25 PM PDT 24
Peak memory 247172 kb
Host smart-c8944288-376c-417a-b991-b46b026c85f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250624863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3250624863
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1329317494
Short name T85
Test name
Test status
Simulation time 32145942288 ps
CPU time 1847.04 seconds
Started Jun 06 03:24:14 PM PDT 24
Finished Jun 06 03:55:02 PM PDT 24
Peak memory 282452 kb
Host smart-a216e037-261b-4b18-a963-c5f89655aaa4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329317494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1329317494
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.478196235
Short name T19
Test name
Test status
Simulation time 13623514440 ps
CPU time 1348.09 seconds
Started Jun 06 03:26:38 PM PDT 24
Finished Jun 06 03:49:09 PM PDT 24
Peak memory 289412 kb
Host smart-f13ecb3b-41f7-47fc-97ae-8d1fb4d156ed
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478196235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_han
dler_stress_all.478196235
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2676015998
Short name T155
Test name
Test status
Simulation time 3610892283 ps
CPU time 164.1 seconds
Started Jun 06 03:14:09 PM PDT 24
Finished Jun 06 03:16:55 PM PDT 24
Peak memory 265464 kb
Host smart-3f830f44-39ee-4134-a2d7-5d973aeb770d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2676015998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.2676015998
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.491626194
Short name T149
Test name
Test status
Simulation time 4434205168 ps
CPU time 752.06 seconds
Started Jun 06 03:11:50 PM PDT 24
Finished Jun 06 03:24:24 PM PDT 24
Peak memory 266712 kb
Host smart-9937ec22-b209-4630-9e61-b1a56a4c0892
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491626194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.491626194
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.4033010772
Short name T261
Test name
Test status
Simulation time 463426323251 ps
CPU time 4451.81 seconds
Started Jun 06 03:17:34 PM PDT 24
Finished Jun 06 04:31:48 PM PDT 24
Peak memory 305740 kb
Host smart-05f74603-79b1-4319-ba1c-5e59904269aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033010772 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.4033010772
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.709499740
Short name T290
Test name
Test status
Simulation time 240541138048 ps
CPU time 666.5 seconds
Started Jun 06 03:22:29 PM PDT 24
Finished Jun 06 03:33:37 PM PDT 24
Peak memory 248120 kb
Host smart-722ecbc9-5db2-4c82-be75-6a060a5976e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709499740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.709499740
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.3944195772
Short name T96
Test name
Test status
Simulation time 130590597382 ps
CPU time 3287.81 seconds
Started Jun 06 03:23:06 PM PDT 24
Finished Jun 06 04:17:56 PM PDT 24
Peak memory 289044 kb
Host smart-64c9f08b-ac4d-4700-84cf-a486f12878cf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944195772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.3944195772
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1417512428
Short name T1
Test name
Test status
Simulation time 139260518536 ps
CPU time 1616.55 seconds
Started Jun 06 03:17:49 PM PDT 24
Finished Jun 06 03:44:48 PM PDT 24
Peak memory 270324 kb
Host smart-a91f2f6b-1c1e-4073-a46c-8e191a58bb1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417512428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1417512428
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.62450835
Short name T60
Test name
Test status
Simulation time 53211960623 ps
CPU time 2661.01 seconds
Started Jun 06 03:21:23 PM PDT 24
Finished Jun 06 04:05:45 PM PDT 24
Peak memory 289196 kb
Host smart-391a64e2-55e2-48a2-af91-8bf9d7cc3b87
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62450835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_hand
ler_stress_all.62450835
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.1902579421
Short name T217
Test name
Test status
Simulation time 42446301959 ps
CPU time 299.93 seconds
Started Jun 06 03:22:48 PM PDT 24
Finished Jun 06 03:27:49 PM PDT 24
Peak memory 248352 kb
Host smart-46f82e58-d3fd-434e-8a1d-988ab0f0eaf8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902579421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1902579421
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3999479233
Short name T122
Test name
Test status
Simulation time 23859359300 ps
CPU time 1033.81 seconds
Started Jun 06 03:13:57 PM PDT 24
Finished Jun 06 03:31:12 PM PDT 24
Peak memory 265560 kb
Host smart-2037d325-41af-419b-9cac-d8eec03c203f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999479233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3999479233
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1598552478
Short name T160
Test name
Test status
Simulation time 894694194 ps
CPU time 34.99 seconds
Started Jun 06 03:14:58 PM PDT 24
Finished Jun 06 03:15:35 PM PDT 24
Peak memory 237284 kb
Host smart-ee861d8c-88b5-4d16-b4ff-2abcc51e64f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1598552478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1598552478
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1802911419
Short name T305
Test name
Test status
Simulation time 156016432201 ps
CPU time 2468.05 seconds
Started Jun 06 03:23:26 PM PDT 24
Finished Jun 06 04:04:37 PM PDT 24
Peak memory 272864 kb
Host smart-06169168-8a59-4e2b-857f-b4bc3b87cf8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802911419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1802911419
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2934735682
Short name T662
Test name
Test status
Simulation time 139957806344 ps
CPU time 394.96 seconds
Started Jun 06 03:25:19 PM PDT 24
Finished Jun 06 03:31:56 PM PDT 24
Peak memory 248260 kb
Host smart-e1832e22-91be-4b9a-ae10-f062b871ff87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934735682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2934735682
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.4248529324
Short name T199
Test name
Test status
Simulation time 46141219 ps
CPU time 3.66 seconds
Started Jun 06 03:12:35 PM PDT 24
Finished Jun 06 03:12:41 PM PDT 24
Peak memory 248952 kb
Host smart-7764b64b-f820-4160-9c6a-4cd42185c148
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4248529324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.4248529324
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.770664084
Short name T207
Test name
Test status
Simulation time 17184551 ps
CPU time 2.78 seconds
Started Jun 06 03:17:19 PM PDT 24
Finished Jun 06 03:17:24 PM PDT 24
Peak memory 248928 kb
Host smart-3fbb9d9c-60b3-4bf8-a1bc-edd766828cf5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=770664084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.770664084
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3804354872
Short name T198
Test name
Test status
Simulation time 14352196 ps
CPU time 2.44 seconds
Started Jun 06 03:19:02 PM PDT 24
Finished Jun 06 03:19:06 PM PDT 24
Peak memory 248920 kb
Host smart-0a4f8fa7-8c30-4605-b6dd-ecb365c39877
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3804354872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3804354872
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.524859808
Short name T210
Test name
Test status
Simulation time 15621463 ps
CPU time 2.42 seconds
Started Jun 06 03:14:31 PM PDT 24
Finished Jun 06 03:14:34 PM PDT 24
Peak memory 248872 kb
Host smart-e5dec9d5-6f18-41a8-8553-0fc5459d7900
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=524859808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.524859808
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.795524336
Short name T146
Test name
Test status
Simulation time 2196805667 ps
CPU time 218.01 seconds
Started Jun 06 03:17:00 PM PDT 24
Finished Jun 06 03:20:39 PM PDT 24
Peak memory 265728 kb
Host smart-e2604fbe-8a44-47fb-bb53-83bb3a2e3828
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=795524336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_erro
rs.795524336
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.705575305
Short name T266
Test name
Test status
Simulation time 24040345892 ps
CPU time 2120.75 seconds
Started Jun 06 03:17:20 PM PDT 24
Finished Jun 06 03:52:42 PM PDT 24
Peak memory 302360 kb
Host smart-3a377dbb-4ac1-42e8-b68d-cb3b91823c2b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705575305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_han
dler_stress_all.705575305
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1818124969
Short name T12
Test name
Test status
Simulation time 58647236585 ps
CPU time 3413.24 seconds
Started Jun 06 03:19:59 PM PDT 24
Finished Jun 06 04:16:54 PM PDT 24
Peak memory 289192 kb
Host smart-9a7569aa-8c3d-4a6a-8f7e-dcd7cce57775
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818124969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1818124969
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2907246004
Short name T275
Test name
Test status
Simulation time 16516028567 ps
CPU time 908.94 seconds
Started Jun 06 03:20:54 PM PDT 24
Finished Jun 06 03:36:05 PM PDT 24
Peak memory 289200 kb
Host smart-a267539b-591c-45d3-ab50-e66554283b18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907246004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2907246004
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.1797119796
Short name T24
Test name
Test status
Simulation time 15859952175 ps
CPU time 1095.21 seconds
Started Jun 06 03:24:24 PM PDT 24
Finished Jun 06 03:42:41 PM PDT 24
Peak memory 272740 kb
Host smart-299b0c4a-63a4-4cdd-a7ba-9ebf8647c6b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797119796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.1797119796
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.1762919031
Short name T26
Test name
Test status
Simulation time 695838126986 ps
CPU time 4891.01 seconds
Started Jun 06 03:25:19 PM PDT 24
Finished Jun 06 04:46:53 PM PDT 24
Peak memory 305772 kb
Host smart-44a48178-e62b-46b4-a11f-cda68c91d0c1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762919031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.1762919031
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1251849793
Short name T171
Test name
Test status
Simulation time 74504816 ps
CPU time 4.44 seconds
Started Jun 06 03:13:47 PM PDT 24
Finished Jun 06 03:13:53 PM PDT 24
Peak memory 237348 kb
Host smart-67f997ae-ac9d-42bd-b210-a70131016574
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1251849793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1251849793
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3259552433
Short name T250
Test name
Test status
Simulation time 67713281533 ps
CPU time 4074.63 seconds
Started Jun 06 03:22:36 PM PDT 24
Finished Jun 06 04:30:33 PM PDT 24
Peak memory 305580 kb
Host smart-23942622-2016-44c0-8cc2-0b9cd88a28d7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259552433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3259552433
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1222778834
Short name T340
Test name
Test status
Simulation time 52644068582 ps
CPU time 982.62 seconds
Started Jun 06 03:14:57 PM PDT 24
Finished Jun 06 03:31:22 PM PDT 24
Peak memory 265416 kb
Host smart-e696971c-6f25-4dad-9766-e971b13e193f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222778834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1222778834
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.713431620
Short name T138
Test name
Test status
Simulation time 53967095417 ps
CPU time 695.83 seconds
Started Jun 06 03:16:59 PM PDT 24
Finished Jun 06 03:28:37 PM PDT 24
Peak memory 265472 kb
Host smart-e0268d12-05bd-441a-817f-39140fe94818
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713431620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.713431620
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2723867345
Short name T735
Test name
Test status
Simulation time 9372867 ps
CPU time 1.71 seconds
Started Jun 06 03:10:52 PM PDT 24
Finished Jun 06 03:10:55 PM PDT 24
Peak memory 236120 kb
Host smart-376ae071-2350-4a6d-a90b-82f4d0244a6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2723867345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2723867345
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.1639069532
Short name T316
Test name
Test status
Simulation time 118815119528 ps
CPU time 3258.32 seconds
Started Jun 06 03:18:24 PM PDT 24
Finished Jun 06 04:12:44 PM PDT 24
Peak memory 289168 kb
Host smart-6114bf79-128d-4707-9bf9-1a37cbe4911f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639069532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.1639069532
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2074530803
Short name T267
Test name
Test status
Simulation time 13914357193 ps
CPU time 1463.79 seconds
Started Jun 06 03:18:39 PM PDT 24
Finished Jun 06 03:43:05 PM PDT 24
Peak memory 289528 kb
Host smart-8401dd1d-7faf-49a8-b715-bb0185b38c58
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074530803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2074530803
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1158815247
Short name T15
Test name
Test status
Simulation time 1593417340 ps
CPU time 36.02 seconds
Started Jun 06 03:18:37 PM PDT 24
Finished Jun 06 03:19:15 PM PDT 24
Peak memory 248772 kb
Host smart-61a40a6e-422d-4772-8265-08ceb14412a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11588
15247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1158815247
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.2944006472
Short name T281
Test name
Test status
Simulation time 3630183712 ps
CPU time 16.69 seconds
Started Jun 06 03:18:48 PM PDT 24
Finished Jun 06 03:19:06 PM PDT 24
Peak memory 256984 kb
Host smart-15d3da76-97da-4096-abd6-09783e5dcc97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29440
06472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.2944006472
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3409435205
Short name T643
Test name
Test status
Simulation time 4203346483 ps
CPU time 175.69 seconds
Started Jun 06 03:19:13 PM PDT 24
Finished Jun 06 03:22:11 PM PDT 24
Peak memory 255472 kb
Host smart-6a6c5e8b-6359-47e1-9627-0b71824791d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409435205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3409435205
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.4028971589
Short name T269
Test name
Test status
Simulation time 15257086663 ps
CPU time 1529.57 seconds
Started Jun 06 03:19:29 PM PDT 24
Finished Jun 06 03:44:59 PM PDT 24
Peak memory 289752 kb
Host smart-0fe1c28e-4a43-4369-80b8-dccc7f5ccb9a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028971589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.4028971589
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.855387633
Short name T273
Test name
Test status
Simulation time 454099622 ps
CPU time 38.16 seconds
Started Jun 06 03:19:48 PM PDT 24
Finished Jun 06 03:20:28 PM PDT 24
Peak memory 255628 kb
Host smart-23b12e22-2fbe-4310-adb6-74a9f3033f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85538
7633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.855387633
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3660954897
Short name T54
Test name
Test status
Simulation time 49768765675 ps
CPU time 409.24 seconds
Started Jun 06 03:13:27 PM PDT 24
Finished Jun 06 03:20:17 PM PDT 24
Peak memory 257000 kb
Host smart-acec1ad2-494e-4f76-b592-795a120f1775
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660954897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3660954897
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.3092240399
Short name T326
Test name
Test status
Simulation time 16136670959 ps
CPU time 1430.59 seconds
Started Jun 06 03:21:16 PM PDT 24
Finished Jun 06 03:45:08 PM PDT 24
Peak memory 273444 kb
Host smart-6dd5f61a-6088-4c7d-b2b6-3f428a8c81a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092240399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3092240399
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.960637161
Short name T292
Test name
Test status
Simulation time 46908727731 ps
CPU time 492.8 seconds
Started Jun 06 03:21:15 PM PDT 24
Finished Jun 06 03:29:29 PM PDT 24
Peak memory 256360 kb
Host smart-11a17405-afc7-428e-92a0-ec46a0116b4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960637161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.960637161
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.153426248
Short name T277
Test name
Test status
Simulation time 43895157663 ps
CPU time 1031.93 seconds
Started Jun 06 03:23:47 PM PDT 24
Finished Jun 06 03:41:00 PM PDT 24
Peak memory 282404 kb
Host smart-90b713bd-248b-4def-bde9-deceac9ae79c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153426248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.153426248
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.2559319645
Short name T276
Test name
Test status
Simulation time 23458294621 ps
CPU time 1485.76 seconds
Started Jun 06 03:25:22 PM PDT 24
Finished Jun 06 03:50:09 PM PDT 24
Peak memory 266252 kb
Host smart-8a4882d3-082d-433a-825a-03bd753c5ba0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559319645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.2559319645
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.260634728
Short name T323
Test name
Test status
Simulation time 27516460151 ps
CPU time 709.04 seconds
Started Jun 06 03:25:38 PM PDT 24
Finished Jun 06 03:37:28 PM PDT 24
Peak memory 265204 kb
Host smart-8d68c29c-a824-455a-b867-22189692dc36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260634728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.260634728
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2494646021
Short name T257
Test name
Test status
Simulation time 129740757 ps
CPU time 8.57 seconds
Started Jun 06 03:26:13 PM PDT 24
Finished Jun 06 03:26:23 PM PDT 24
Peak memory 247464 kb
Host smart-ec3b9837-bde6-4df4-8466-f7ef80529f15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24946
46021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2494646021
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2438977069
Short name T179
Test name
Test status
Simulation time 6048750706 ps
CPU time 400.73 seconds
Started Jun 06 03:15:18 PM PDT 24
Finished Jun 06 03:22:01 PM PDT 24
Peak memory 257212 kb
Host smart-26d4a0a8-06b0-410c-b3cb-b4c60bc54a19
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438977069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.2438977069
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1852584707
Short name T274
Test name
Test status
Simulation time 2571408986 ps
CPU time 42.58 seconds
Started Jun 06 03:16:49 PM PDT 24
Finished Jun 06 03:17:33 PM PDT 24
Peak memory 255404 kb
Host smart-15b7827d-f8c3-430a-a0af-b42d7bdbedb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18525
84707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1852584707
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1700436417
Short name T166
Test name
Test status
Simulation time 63973597 ps
CPU time 5.09 seconds
Started Jun 06 03:16:47 PM PDT 24
Finished Jun 06 03:16:53 PM PDT 24
Peak memory 237064 kb
Host smart-a74e6404-d93c-45b2-a4f3-edd904bb92db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1700436417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.1700436417
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3314617466
Short name T164
Test name
Test status
Simulation time 91811586 ps
CPU time 3.21 seconds
Started Jun 06 03:17:13 PM PDT 24
Finished Jun 06 03:17:18 PM PDT 24
Peak memory 237012 kb
Host smart-cf1e7196-aa67-453d-a2d4-43a71944e26c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3314617466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3314617466
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.4170850052
Short name T167
Test name
Test status
Simulation time 111052731 ps
CPU time 4.85 seconds
Started Jun 06 03:12:22 PM PDT 24
Finished Jun 06 03:12:28 PM PDT 24
Peak memory 237020 kb
Host smart-67972bf4-f85d-4d10-a55c-f58f6d7ef6c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4170850052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.4170850052
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3682695205
Short name T142
Test name
Test status
Simulation time 886974269 ps
CPU time 91.21 seconds
Started Jun 06 03:10:40 PM PDT 24
Finished Jun 06 03:12:12 PM PDT 24
Peak memory 265388 kb
Host smart-004428b4-79d1-4ba4-88d5-30876c142d22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3682695205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3682695205
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2738291310
Short name T168
Test name
Test status
Simulation time 44728083 ps
CPU time 3.32 seconds
Started Jun 06 03:10:39 PM PDT 24
Finished Jun 06 03:10:44 PM PDT 24
Peak memory 237584 kb
Host smart-5a18a486-63ec-4bd3-a7e9-2a08fdeee3e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2738291310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.2738291310
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3339681662
Short name T169
Test name
Test status
Simulation time 2322853777 ps
CPU time 31.25 seconds
Started Jun 06 03:14:20 PM PDT 24
Finished Jun 06 03:14:53 PM PDT 24
Peak memory 248796 kb
Host smart-ee73a268-2243-41ca-b28f-1538fa284f1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3339681662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3339681662
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3014296900
Short name T172
Test name
Test status
Simulation time 943088964 ps
CPU time 72.95 seconds
Started Jun 06 03:15:06 PM PDT 24
Finished Jun 06 03:16:21 PM PDT 24
Peak memory 239728 kb
Host smart-b54f5503-376e-464f-8ebb-791f4b5dc21e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3014296900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3014296900
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3621419237
Short name T151
Test name
Test status
Simulation time 1360775663 ps
CPU time 128.5 seconds
Started Jun 06 03:16:32 PM PDT 24
Finished Jun 06 03:18:42 PM PDT 24
Peak memory 266164 kb
Host smart-15d94d2c-9513-4a4d-90c6-c25bd78e59f0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3621419237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3621419237
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3412149120
Short name T177
Test name
Test status
Simulation time 1768219374 ps
CPU time 32.62 seconds
Started Jun 06 03:15:30 PM PDT 24
Finished Jun 06 03:16:04 PM PDT 24
Peak memory 240508 kb
Host smart-e23707a3-d661-48b2-b2cd-0d893df72914
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3412149120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3412149120
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3864296295
Short name T175
Test name
Test status
Simulation time 89254461 ps
CPU time 3.93 seconds
Started Jun 06 03:16:01 PM PDT 24
Finished Jun 06 03:16:07 PM PDT 24
Peak memory 237016 kb
Host smart-c8e4e037-a9c7-47dd-a908-e952be69637f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3864296295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3864296295
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2676008365
Short name T165
Test name
Test status
Simulation time 23149540 ps
CPU time 2.36 seconds
Started Jun 06 03:11:01 PM PDT 24
Finished Jun 06 03:11:04 PM PDT 24
Peak memory 237148 kb
Host smart-8949abb6-0653-4d56-af26-56fe9969cc75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2676008365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2676008365
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2303912718
Short name T170
Test name
Test status
Simulation time 3693702761 ps
CPU time 83.22 seconds
Started Jun 06 03:11:37 PM PDT 24
Finished Jun 06 03:13:03 PM PDT 24
Peak memory 246492 kb
Host smart-92589346-4b7f-4e74-ba4a-169092e3cf4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2303912718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2303912718
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.4050435822
Short name T176
Test name
Test status
Simulation time 926607438 ps
CPU time 40.44 seconds
Started Jun 06 03:11:38 PM PDT 24
Finished Jun 06 03:12:21 PM PDT 24
Peak memory 245308 kb
Host smart-1e2f089c-715c-4fbf-be59-277f0d9e558c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4050435822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.4050435822
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1493654511
Short name T173
Test name
Test status
Simulation time 32941923 ps
CPU time 2.29 seconds
Started Jun 06 03:13:27 PM PDT 24
Finished Jun 06 03:13:30 PM PDT 24
Peak memory 236872 kb
Host smart-6e82e306-c447-4159-834d-afddbdd265b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1493654511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1493654511
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.269286642
Short name T21
Test name
Test status
Simulation time 429998089 ps
CPU time 27.6 seconds
Started Jun 06 03:24:54 PM PDT 24
Finished Jun 06 03:25:23 PM PDT 24
Peak memory 247824 kb
Host smart-298e641c-709c-4d1c-b47e-60bd692a00f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26928
6642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.269286642
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.4195472089
Short name T174
Test name
Test status
Simulation time 2294172304 ps
CPU time 168.18 seconds
Started Jun 06 03:10:26 PM PDT 24
Finished Jun 06 03:13:15 PM PDT 24
Peak memory 240528 kb
Host smart-b5607b48-fee1-40d1-bd16-7035aa1265a2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4195472089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.4195472089
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2682298478
Short name T798
Test name
Test status
Simulation time 22865154245 ps
CPU time 410.21 seconds
Started Jun 06 03:10:27 PM PDT 24
Finished Jun 06 03:17:19 PM PDT 24
Peak memory 237124 kb
Host smart-aeab6ac7-8327-49ec-9049-58ed81fb6acc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2682298478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2682298478
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2437056545
Short name T770
Test name
Test status
Simulation time 40379923 ps
CPU time 6.42 seconds
Started Jun 06 03:10:27 PM PDT 24
Finished Jun 06 03:10:35 PM PDT 24
Peak memory 240480 kb
Host smart-73ca63e1-f8af-4572-9340-cec5883e1dd5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2437056545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2437056545
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1499223490
Short name T342
Test name
Test status
Simulation time 110312441 ps
CPU time 5.73 seconds
Started Jun 06 03:10:40 PM PDT 24
Finished Jun 06 03:10:47 PM PDT 24
Peak memory 240516 kb
Host smart-460fe5c0-86ef-4cc9-8ede-d8b599414f17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499223490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1499223490
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2650443741
Short name T790
Test name
Test status
Simulation time 228140578 ps
CPU time 4.6 seconds
Started Jun 06 03:10:28 PM PDT 24
Finished Jun 06 03:10:33 PM PDT 24
Peak memory 235984 kb
Host smart-557a6898-eee5-43f2-8494-d3aa9311d86f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2650443741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2650443741
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.4165133010
Short name T809
Test name
Test status
Simulation time 7624797 ps
CPU time 1.44 seconds
Started Jun 06 03:10:26 PM PDT 24
Finished Jun 06 03:10:29 PM PDT 24
Peak memory 235076 kb
Host smart-dc13c655-ee00-4987-9474-2192fc16eb2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4165133010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.4165133010
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2768952253
Short name T191
Test name
Test status
Simulation time 1283775608 ps
CPU time 24.26 seconds
Started Jun 06 03:10:41 PM PDT 24
Finished Jun 06 03:11:07 PM PDT 24
Peak memory 245228 kb
Host smart-0faa54da-cc75-4eb9-88e4-413b65a189d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2768952253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.2768952253
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.466364699
Short name T150
Test name
Test status
Simulation time 7459094824 ps
CPU time 566.33 seconds
Started Jun 06 03:10:16 PM PDT 24
Finished Jun 06 03:19:43 PM PDT 24
Peak memory 265528 kb
Host smart-6bf7b7dd-8363-4dfa-992a-5ffab34b7961
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466364699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.466364699
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3355367065
Short name T241
Test name
Test status
Simulation time 540569645 ps
CPU time 21.06 seconds
Started Jun 06 03:10:17 PM PDT 24
Finished Jun 06 03:10:39 PM PDT 24
Peak memory 251056 kb
Host smart-7bde29ab-0903-4865-ad70-acd9d6004e62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3355367065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3355367065
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.55064639
Short name T158
Test name
Test status
Simulation time 320295997 ps
CPU time 26.94 seconds
Started Jun 06 03:10:18 PM PDT 24
Finished Jun 06 03:10:46 PM PDT 24
Peak memory 239920 kb
Host smart-8d9097fa-56a8-4b2e-888f-7a26fb20b965
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=55064639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.55064639
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1322954590
Short name T780
Test name
Test status
Simulation time 17302685173 ps
CPU time 291.02 seconds
Started Jun 06 03:11:03 PM PDT 24
Finished Jun 06 03:15:55 PM PDT 24
Peak memory 240124 kb
Host smart-df1b9796-48fa-4adb-9548-7cf595b96e8b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1322954590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.1322954590
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.465594316
Short name T722
Test name
Test status
Simulation time 1704927758 ps
CPU time 247.47 seconds
Started Jun 06 03:10:50 PM PDT 24
Finished Jun 06 03:14:59 PM PDT 24
Peak memory 236936 kb
Host smart-db52eb3b-917e-4fd9-907a-e8d7e7da80cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=465594316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.465594316
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2316979825
Short name T242
Test name
Test status
Simulation time 132768593 ps
CPU time 9.11 seconds
Started Jun 06 03:10:50 PM PDT 24
Finished Jun 06 03:11:00 PM PDT 24
Peak memory 240448 kb
Host smart-6de49396-ada3-4bb4-9153-26139c71f94b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2316979825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2316979825
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.982874129
Short name T775
Test name
Test status
Simulation time 63280180 ps
CPU time 6.98 seconds
Started Jun 06 03:11:01 PM PDT 24
Finished Jun 06 03:11:09 PM PDT 24
Peak memory 251084 kb
Host smart-e925aca8-c6b4-439e-a507-15852af31a59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982874129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.982874129
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.247780048
Short name T740
Test name
Test status
Simulation time 34089274 ps
CPU time 5.7 seconds
Started Jun 06 03:10:50 PM PDT 24
Finished Jun 06 03:10:57 PM PDT 24
Peak memory 240456 kb
Host smart-8ccb1e6a-3c5a-4871-acd6-bfe55418a89f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=247780048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.247780048
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3757365824
Short name T248
Test name
Test status
Simulation time 304087188 ps
CPU time 20.7 seconds
Started Jun 06 03:11:00 PM PDT 24
Finished Jun 06 03:11:22 PM PDT 24
Peak memory 244308 kb
Host smart-4e601ab4-d228-4392-86e6-9ecb9bb1fbcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3757365824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3757365824
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1953102209
Short name T121
Test name
Test status
Simulation time 6339465143 ps
CPU time 558.7 seconds
Started Jun 06 03:10:42 PM PDT 24
Finished Jun 06 03:20:02 PM PDT 24
Peak memory 265460 kb
Host smart-e917f759-a35e-44f5-be63-82451176c948
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953102209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1953102209
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3353759755
Short name T811
Test name
Test status
Simulation time 101480146 ps
CPU time 8.37 seconds
Started Jun 06 03:10:39 PM PDT 24
Finished Jun 06 03:10:48 PM PDT 24
Peak memory 248828 kb
Host smart-bafd96ca-4e7b-4285-bd48-f1800eec8240
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3353759755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3353759755
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2606998143
Short name T714
Test name
Test status
Simulation time 75011490 ps
CPU time 7.75 seconds
Started Jun 06 03:14:21 PM PDT 24
Finished Jun 06 03:14:30 PM PDT 24
Peak memory 239848 kb
Host smart-0fdf075c-089f-481c-8080-838283656b56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606998143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2606998143
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1201502675
Short name T728
Test name
Test status
Simulation time 176433159 ps
CPU time 6.19 seconds
Started Jun 06 03:13:57 PM PDT 24
Finished Jun 06 03:14:04 PM PDT 24
Peak memory 236804 kb
Host smart-5535a7f2-abea-41cd-adca-cb47d2e192b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1201502675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1201502675
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1912890460
Short name T720
Test name
Test status
Simulation time 12465837 ps
CPU time 1.37 seconds
Started Jun 06 03:13:58 PM PDT 24
Finished Jun 06 03:14:01 PM PDT 24
Peak memory 236128 kb
Host smart-27a24835-67e2-4111-b8b8-9be811dad654
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1912890460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1912890460
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1342442030
Short name T744
Test name
Test status
Simulation time 736358670 ps
CPU time 50.21 seconds
Started Jun 06 03:13:54 PM PDT 24
Finished Jun 06 03:14:46 PM PDT 24
Peak memory 245252 kb
Host smart-2292edda-42dc-4074-ae5d-ff2d82988702
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1342442030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.1342442030
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.4046358967
Short name T140
Test name
Test status
Simulation time 4122013744 ps
CPU time 275.13 seconds
Started Jun 06 03:13:48 PM PDT 24
Finished Jun 06 03:18:24 PM PDT 24
Peak memory 265424 kb
Host smart-89b4b45e-1a05-400b-8c6f-14ac2af9b13a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4046358967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.4046358967
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3147983834
Short name T734
Test name
Test status
Simulation time 120059010 ps
CPU time 10.76 seconds
Started Jun 06 03:13:47 PM PDT 24
Finished Jun 06 03:13:58 PM PDT 24
Peak memory 253028 kb
Host smart-b165d75b-650b-4aae-a191-073883e1fdda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3147983834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3147983834
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2299688195
Short name T341
Test name
Test status
Simulation time 63584153 ps
CPU time 11.17 seconds
Started Jun 06 03:14:19 PM PDT 24
Finished Jun 06 03:14:33 PM PDT 24
Peak memory 248748 kb
Host smart-488b6cbf-4de1-4ae2-adeb-9311172b749b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299688195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2299688195
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.599723921
Short name T721
Test name
Test status
Simulation time 49147029 ps
CPU time 5.84 seconds
Started Jun 06 03:14:22 PM PDT 24
Finished Jun 06 03:14:28 PM PDT 24
Peak memory 239616 kb
Host smart-cf741e6b-b901-4dfe-8c88-5e4fe85432eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=599723921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.599723921
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.549395683
Short name T817
Test name
Test status
Simulation time 12030754 ps
CPU time 1.33 seconds
Started Jun 06 03:14:19 PM PDT 24
Finished Jun 06 03:14:22 PM PDT 24
Peak memory 237068 kb
Host smart-38fb025b-3a52-4851-80c2-f9f214756eb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=549395683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.549395683
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2543339729
Short name T749
Test name
Test status
Simulation time 321159686 ps
CPU time 22.43 seconds
Started Jun 06 03:14:18 PM PDT 24
Finished Jun 06 03:14:43 PM PDT 24
Peak memory 244320 kb
Host smart-50201fff-93c7-4219-aeb9-801ed44c8a63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2543339729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.2543339729
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3749008249
Short name T760
Test name
Test status
Simulation time 54938102 ps
CPU time 8.96 seconds
Started Jun 06 03:14:07 PM PDT 24
Finished Jun 06 03:14:17 PM PDT 24
Peak memory 247864 kb
Host smart-033afe1d-e41d-4fb9-bff1-495008a0a04f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3749008249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3749008249
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1874266559
Short name T800
Test name
Test status
Simulation time 50388897 ps
CPU time 4.45 seconds
Started Jun 06 03:14:56 PM PDT 24
Finished Jun 06 03:15:02 PM PDT 24
Peak memory 238904 kb
Host smart-82d90cd3-f7de-4614-8bbf-49d6c50a20af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874266559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1874266559
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2307896319
Short name T754
Test name
Test status
Simulation time 64612687 ps
CPU time 5.49 seconds
Started Jun 06 03:14:57 PM PDT 24
Finished Jun 06 03:15:04 PM PDT 24
Peak memory 236952 kb
Host smart-763a40da-a6b7-4572-8cc7-3eceec2080c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2307896319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2307896319
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2596643694
Short name T789
Test name
Test status
Simulation time 15328750 ps
CPU time 1.3 seconds
Started Jun 06 03:14:56 PM PDT 24
Finished Jun 06 03:14:58 PM PDT 24
Peak memory 235120 kb
Host smart-517c6007-5447-4398-9ce3-f0cc957ba24c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2596643694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2596643694
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1112052773
Short name T193
Test name
Test status
Simulation time 331628252 ps
CPU time 22.9 seconds
Started Jun 06 03:14:58 PM PDT 24
Finished Jun 06 03:15:23 PM PDT 24
Peak memory 245244 kb
Host smart-8b2083ec-8a7a-4c29-bb6a-ba6b44b6e96b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1112052773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1112052773
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.111685300
Short name T143
Test name
Test status
Simulation time 2922429074 ps
CPU time 115.46 seconds
Started Jun 06 03:14:42 PM PDT 24
Finished Jun 06 03:16:39 PM PDT 24
Peak memory 257256 kb
Host smart-15dff33b-8ff5-490b-bbc6-f2ebd2113ff7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=111685300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro
rs.111685300
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.504321435
Short name T131
Test name
Test status
Simulation time 12548164798 ps
CPU time 1144.25 seconds
Started Jun 06 03:14:30 PM PDT 24
Finished Jun 06 03:33:35 PM PDT 24
Peak memory 265488 kb
Host smart-6b2d7967-9848-4283-804c-3046d3359ae6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504321435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.504321435
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1108334782
Short name T793
Test name
Test status
Simulation time 388078505 ps
CPU time 14.35 seconds
Started Jun 06 03:15:01 PM PDT 24
Finished Jun 06 03:15:17 PM PDT 24
Peak memory 248084 kb
Host smart-2eb36a55-0454-4c79-b4fb-0db9f3abcf78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1108334782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1108334782
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.892606231
Short name T787
Test name
Test status
Simulation time 454746462 ps
CPU time 10.74 seconds
Started Jun 06 03:15:18 PM PDT 24
Finished Jun 06 03:15:30 PM PDT 24
Peak memory 239664 kb
Host smart-f09bc549-334c-4ef4-af62-a976a7d6a441
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892606231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.892606231
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.996301185
Short name T245
Test name
Test status
Simulation time 123638175 ps
CPU time 9.36 seconds
Started Jun 06 03:15:05 PM PDT 24
Finished Jun 06 03:15:16 PM PDT 24
Peak memory 236024 kb
Host smart-e0de0633-457f-4cc7-852a-fa075da9bd84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=996301185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.996301185
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.505353797
Short name T736
Test name
Test status
Simulation time 12328903 ps
CPU time 1.64 seconds
Started Jun 06 03:15:06 PM PDT 24
Finished Jun 06 03:15:09 PM PDT 24
Peak memory 236132 kb
Host smart-6559c552-8dfb-4a80-92e9-74f993f51e28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=505353797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.505353797
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.4095478988
Short name T814
Test name
Test status
Simulation time 298911506 ps
CPU time 11.56 seconds
Started Jun 06 03:15:17 PM PDT 24
Finished Jun 06 03:15:31 PM PDT 24
Peak memory 248728 kb
Host smart-96e2462f-6529-448b-8437-50fd4ee8a125
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4095478988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.4095478988
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.4170279540
Short name T145
Test name
Test status
Simulation time 2494030810 ps
CPU time 162.9 seconds
Started Jun 06 03:14:58 PM PDT 24
Finished Jun 06 03:17:43 PM PDT 24
Peak memory 265448 kb
Host smart-482fd7d5-b7e7-49ef-a03c-b66eba05afc6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4170279540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.4170279540
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3639162691
Short name T727
Test name
Test status
Simulation time 282220280 ps
CPU time 6.9 seconds
Started Jun 06 03:15:07 PM PDT 24
Finished Jun 06 03:15:15 PM PDT 24
Peak memory 248064 kb
Host smart-de7438a2-e574-4f0b-8484-abbb2cfeb617
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3639162691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3639162691
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3427218049
Short name T807
Test name
Test status
Simulation time 753645957 ps
CPU time 4.76 seconds
Started Jun 06 03:15:43 PM PDT 24
Finished Jun 06 03:15:49 PM PDT 24
Peak memory 237084 kb
Host smart-22ab6eeb-a031-4c9c-a01b-114171bf3d3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427218049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3427218049
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1867574748
Short name T743
Test name
Test status
Simulation time 97110904 ps
CPU time 8 seconds
Started Jun 06 03:15:29 PM PDT 24
Finished Jun 06 03:15:39 PM PDT 24
Peak memory 236980 kb
Host smart-e1b8619b-2305-453c-b631-5b9342e45088
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1867574748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1867574748
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.268723251
Short name T718
Test name
Test status
Simulation time 12881192 ps
CPU time 1.82 seconds
Started Jun 06 03:15:33 PM PDT 24
Finished Jun 06 03:15:36 PM PDT 24
Peak memory 237072 kb
Host smart-9cbdc616-564e-498e-adf5-4058345c7e17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=268723251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.268723251
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.926801242
Short name T771
Test name
Test status
Simulation time 176940763 ps
CPU time 24.49 seconds
Started Jun 06 03:15:40 PM PDT 24
Finished Jun 06 03:16:05 PM PDT 24
Peak memory 248704 kb
Host smart-b1722438-6c75-4f49-8d46-c4bd984e042e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=926801242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.926801242
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.723607650
Short name T823
Test name
Test status
Simulation time 809892110 ps
CPU time 107.07 seconds
Started Jun 06 03:15:16 PM PDT 24
Finished Jun 06 03:17:04 PM PDT 24
Peak memory 256996 kb
Host smart-1b930f91-9deb-4af7-a38e-c31ffb996b5d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=723607650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_erro
rs.723607650
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.4077341566
Short name T816
Test name
Test status
Simulation time 1350521282 ps
CPU time 11.61 seconds
Started Jun 06 03:15:29 PM PDT 24
Finished Jun 06 03:15:42 PM PDT 24
Peak memory 253088 kb
Host smart-60061735-e9a5-4af8-8765-fd992084b8a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4077341566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.4077341566
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2044696374
Short name T716
Test name
Test status
Simulation time 53511562 ps
CPU time 5.35 seconds
Started Jun 06 03:15:51 PM PDT 24
Finished Jun 06 03:15:58 PM PDT 24
Peak memory 238104 kb
Host smart-80ace519-334c-46a1-a8d1-74ef95caaa92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044696374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2044696374
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3984804329
Short name T763
Test name
Test status
Simulation time 182887641 ps
CPU time 5.37 seconds
Started Jun 06 03:15:52 PM PDT 24
Finished Jun 06 03:15:59 PM PDT 24
Peak memory 239576 kb
Host smart-6e488440-397a-4d8a-8a67-c7a25ce354c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3984804329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3984804329
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1867868557
Short name T331
Test name
Test status
Simulation time 9627286 ps
CPU time 1.55 seconds
Started Jun 06 03:15:52 PM PDT 24
Finished Jun 06 03:15:56 PM PDT 24
Peak memory 236076 kb
Host smart-966f1ad0-ab30-45bb-9a41-a28fd5242daf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1867868557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1867868557
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2723107151
Short name T729
Test name
Test status
Simulation time 1129465950 ps
CPU time 21.07 seconds
Started Jun 06 03:15:52 PM PDT 24
Finished Jun 06 03:16:14 PM PDT 24
Peak memory 245244 kb
Host smart-04bde0ac-5260-4126-9b9f-6ddab7b2e7a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2723107151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2723107151
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.903661266
Short name T127
Test name
Test status
Simulation time 4120917006 ps
CPU time 223.24 seconds
Started Jun 06 03:15:40 PM PDT 24
Finished Jun 06 03:19:24 PM PDT 24
Peak memory 266512 kb
Host smart-dfad8d3c-69fd-4538-af32-6175d45cc8a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=903661266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_erro
rs.903661266
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3455884869
Short name T148
Test name
Test status
Simulation time 24752508884 ps
CPU time 549.21 seconds
Started Jun 06 03:15:42 PM PDT 24
Finished Jun 06 03:24:52 PM PDT 24
Peak memory 265464 kb
Host smart-1e839a47-df58-41a3-a866-2e13ce9e885e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455884869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3455884869
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2374603306
Short name T801
Test name
Test status
Simulation time 291875701 ps
CPU time 13.11 seconds
Started Jun 06 03:15:40 PM PDT 24
Finished Jun 06 03:15:55 PM PDT 24
Peak memory 248376 kb
Host smart-d20712fc-3d9f-44f2-90e9-68219ab3cf65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2374603306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2374603306
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2024219729
Short name T831
Test name
Test status
Simulation time 81313060 ps
CPU time 8.28 seconds
Started Jun 06 03:16:32 PM PDT 24
Finished Jun 06 03:16:41 PM PDT 24
Peak memory 240844 kb
Host smart-fffbebb1-60f8-4772-934d-ff836d96b2a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024219729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.2024219729
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.4111339614
Short name T781
Test name
Test status
Simulation time 34924700 ps
CPU time 3.62 seconds
Started Jun 06 03:16:18 PM PDT 24
Finished Jun 06 03:16:24 PM PDT 24
Peak memory 235968 kb
Host smart-9aa31789-a658-48ff-9a29-29ec1410bae6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4111339614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.4111339614
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2996057584
Short name T808
Test name
Test status
Simulation time 11483863 ps
CPU time 1.45 seconds
Started Jun 06 03:16:13 PM PDT 24
Finished Jun 06 03:16:15 PM PDT 24
Peak memory 237036 kb
Host smart-714c3505-71eb-44ec-9b33-3cc0bb88b343
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2996057584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2996057584
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1393977637
Short name T717
Test name
Test status
Simulation time 518762496 ps
CPU time 38.63 seconds
Started Jun 06 03:16:30 PM PDT 24
Finished Jun 06 03:17:10 PM PDT 24
Peak memory 245204 kb
Host smart-f0b52afb-c888-4b18-9606-8aa460ac8295
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1393977637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1393977637
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1808263818
Short name T154
Test name
Test status
Simulation time 7290442108 ps
CPU time 142.12 seconds
Started Jun 06 03:15:52 PM PDT 24
Finished Jun 06 03:18:16 PM PDT 24
Peak memory 257292 kb
Host smart-c9843f4d-5cd4-4c02-bddf-f719e880e3b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1808263818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1808263818
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1620960168
Short name T133
Test name
Test status
Simulation time 4473121329 ps
CPU time 779.97 seconds
Started Jun 06 03:15:53 PM PDT 24
Finished Jun 06 03:28:55 PM PDT 24
Peak memory 265464 kb
Host smart-c402a2d7-ec7d-4991-bd69-e1be783471df
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620960168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.1620960168
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.683783275
Short name T715
Test name
Test status
Simulation time 262914237 ps
CPU time 10.47 seconds
Started Jun 06 03:16:02 PM PDT 24
Finished Jun 06 03:16:14 PM PDT 24
Peak memory 248452 kb
Host smart-efaae1df-0969-4b9d-a247-b2062c4ec09b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=683783275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.683783275
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.4063802406
Short name T337
Test name
Test status
Simulation time 55496913 ps
CPU time 5.79 seconds
Started Jun 06 03:17:06 PM PDT 24
Finished Jun 06 03:17:13 PM PDT 24
Peak memory 240592 kb
Host smart-6d880892-0a1c-4aee-a715-e94d534ab64c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063802406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.4063802406
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.856798667
Short name T821
Test name
Test status
Simulation time 111152926 ps
CPU time 6.11 seconds
Started Jun 06 03:16:45 PM PDT 24
Finished Jun 06 03:16:52 PM PDT 24
Peak memory 236972 kb
Host smart-f3f3c206-e58e-48e6-b9be-c3ca0b3b3b15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=856798667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.856798667
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.744611011
Short name T335
Test name
Test status
Simulation time 13452412 ps
CPU time 1.65 seconds
Started Jun 06 03:16:47 PM PDT 24
Finished Jun 06 03:16:50 PM PDT 24
Peak memory 236104 kb
Host smart-857d4a56-6c19-4c46-a6ac-5bd83936a5f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=744611011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.744611011
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1678444196
Short name T733
Test name
Test status
Simulation time 1408892921 ps
CPU time 45.37 seconds
Started Jun 06 03:16:47 PM PDT 24
Finished Jun 06 03:17:35 PM PDT 24
Peak memory 245200 kb
Host smart-5ef0fd30-ab50-448e-a7d5-f2136b9694fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1678444196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.1678444196
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.62559561
Short name T132
Test name
Test status
Simulation time 4331675527 ps
CPU time 581.23 seconds
Started Jun 06 03:16:32 PM PDT 24
Finished Jun 06 03:26:14 PM PDT 24
Peak memory 265444 kb
Host smart-32fc385c-acb0-49df-84aa-6413431fc485
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62559561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.62559561
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3412102024
Short name T244
Test name
Test status
Simulation time 234393643 ps
CPU time 19.64 seconds
Started Jun 06 03:16:47 PM PDT 24
Finished Jun 06 03:17:07 PM PDT 24
Peak memory 256612 kb
Host smart-2f7a3f20-2ac8-431d-a35e-aa0d5c78a537
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3412102024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3412102024
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1209044106
Short name T830
Test name
Test status
Simulation time 270927690 ps
CPU time 11.3 seconds
Started Jun 06 03:16:59 PM PDT 24
Finished Jun 06 03:17:12 PM PDT 24
Peak memory 250024 kb
Host smart-9d52b578-846d-44cb-bb4d-8497f2232317
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209044106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.1209044106
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3375461881
Short name T750
Test name
Test status
Simulation time 51756071 ps
CPU time 5.71 seconds
Started Jun 06 03:16:59 PM PDT 24
Finished Jun 06 03:17:06 PM PDT 24
Peak memory 236904 kb
Host smart-17b8692d-eff9-4f84-baca-7a1ff31dcc98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3375461881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3375461881
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.1301283341
Short name T162
Test name
Test status
Simulation time 17599405 ps
CPU time 1.31 seconds
Started Jun 06 03:16:55 PM PDT 24
Finished Jun 06 03:16:57 PM PDT 24
Peak memory 237020 kb
Host smart-570201db-cb11-4692-9c18-c8e0639d2286
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1301283341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.1301283341
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3502183566
Short name T799
Test name
Test status
Simulation time 95366293 ps
CPU time 14.2 seconds
Started Jun 06 03:16:57 PM PDT 24
Finished Jun 06 03:17:13 PM PDT 24
Peak memory 245216 kb
Host smart-baf2d8e9-fc77-48f6-a676-83c231ebe992
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3502183566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3502183566
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3267297083
Short name T139
Test name
Test status
Simulation time 6676300856 ps
CPU time 187.7 seconds
Started Jun 06 03:16:55 PM PDT 24
Finished Jun 06 03:20:04 PM PDT 24
Peak memory 273580 kb
Host smart-286096ae-eba6-4182-9021-6aa9e800b65a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3267297083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3267297083
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3875313167
Short name T805
Test name
Test status
Simulation time 466320626 ps
CPU time 32.42 seconds
Started Jun 06 03:16:51 PM PDT 24
Finished Jun 06 03:17:25 PM PDT 24
Peak memory 248608 kb
Host smart-58b62adf-17fd-4a57-a96a-c96f00c68e64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3875313167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3875313167
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2368970348
Short name T737
Test name
Test status
Simulation time 22932995 ps
CPU time 2.45 seconds
Started Jun 06 03:16:55 PM PDT 24
Finished Jun 06 03:16:58 PM PDT 24
Peak memory 237000 kb
Host smart-1ee528fe-bf98-4900-9e79-d1a209392208
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2368970348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2368970348
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1719443406
Short name T741
Test name
Test status
Simulation time 221642258 ps
CPU time 5.44 seconds
Started Jun 06 03:17:22 PM PDT 24
Finished Jun 06 03:17:29 PM PDT 24
Peak memory 238104 kb
Host smart-98090467-be08-4eea-9e1e-10c40475e55e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719443406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.1719443406
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3163111471
Short name T243
Test name
Test status
Simulation time 284053490 ps
CPU time 9.05 seconds
Started Jun 06 03:17:11 PM PDT 24
Finished Jun 06 03:17:22 PM PDT 24
Peak memory 236040 kb
Host smart-f55722df-8e5d-4920-8eff-c57125085ecc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3163111471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3163111471
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3924758048
Short name T774
Test name
Test status
Simulation time 379660788 ps
CPU time 12.49 seconds
Started Jun 06 03:17:16 PM PDT 24
Finished Jun 06 03:17:30 PM PDT 24
Peak memory 248664 kb
Host smart-7c5ffcd6-6f19-42bf-a76b-fdfa8495417f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3924758048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3924758048
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.990729537
Short name T812
Test name
Test status
Simulation time 1043305676 ps
CPU time 21.25 seconds
Started Jun 06 03:17:01 PM PDT 24
Finished Jun 06 03:17:24 PM PDT 24
Peak memory 248788 kb
Host smart-e1b06fa7-2856-433d-bf5e-20a9b9c31201
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=990729537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.990729537
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.979776904
Short name T192
Test name
Test status
Simulation time 1085995970 ps
CPU time 193.76 seconds
Started Jun 06 03:11:25 PM PDT 24
Finished Jun 06 03:14:40 PM PDT 24
Peak memory 240396 kb
Host smart-901fa70a-758c-4570-b5c7-3403f0c467da
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=979776904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.979776904
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2827965559
Short name T769
Test name
Test status
Simulation time 17813105914 ps
CPU time 519.3 seconds
Started Jun 06 03:11:23 PM PDT 24
Finished Jun 06 03:20:03 PM PDT 24
Peak memory 240516 kb
Host smart-86ceb2e5-9ce4-41ae-b65e-ab980dd1d219
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2827965559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2827965559
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.4156322818
Short name T797
Test name
Test status
Simulation time 123063607 ps
CPU time 4.86 seconds
Started Jun 06 03:11:03 PM PDT 24
Finished Jun 06 03:11:09 PM PDT 24
Peak memory 240452 kb
Host smart-7e4ef394-df38-4bde-b4a9-bf1fccacc1bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4156322818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.4156322818
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2745700516
Short name T338
Test name
Test status
Simulation time 75726097 ps
CPU time 6.77 seconds
Started Jun 06 03:11:23 PM PDT 24
Finished Jun 06 03:11:31 PM PDT 24
Peak memory 240580 kb
Host smart-14357f90-cf19-4588-ae1e-6f30c3d706c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745700516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2745700516
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2765858381
Short name T785
Test name
Test status
Simulation time 183223466 ps
CPU time 7.18 seconds
Started Jun 06 03:11:23 PM PDT 24
Finished Jun 06 03:11:32 PM PDT 24
Peak memory 240392 kb
Host smart-cac26bfe-7817-400a-83dc-0afac5ef1e35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2765858381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2765858381
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3429001974
Short name T783
Test name
Test status
Simulation time 10473003 ps
CPU time 1.64 seconds
Started Jun 06 03:11:03 PM PDT 24
Finished Jun 06 03:11:06 PM PDT 24
Peak memory 236988 kb
Host smart-0e277196-fefa-46c2-9b7b-e12bb20257f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3429001974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3429001974
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2084533949
Short name T747
Test name
Test status
Simulation time 2812516546 ps
CPU time 51.21 seconds
Started Jun 06 03:11:23 PM PDT 24
Finished Jun 06 03:12:15 PM PDT 24
Peak memory 245380 kb
Host smart-4bc5d88b-9280-4cc3-92c2-ae42bcbd228b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2084533949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2084533949
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1240835864
Short name T137
Test name
Test status
Simulation time 17960689111 ps
CPU time 195.64 seconds
Started Jun 06 03:11:00 PM PDT 24
Finished Jun 06 03:14:17 PM PDT 24
Peak memory 265672 kb
Host smart-283162d0-4964-4f97-a1db-400eba9e6299
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1240835864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1240835864
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.4237675408
Short name T157
Test name
Test status
Simulation time 25398965914 ps
CPU time 556.41 seconds
Started Jun 06 03:11:01 PM PDT 24
Finished Jun 06 03:20:19 PM PDT 24
Peak memory 266524 kb
Host smart-3fd88bd0-9473-405b-b63c-7d602dba75ca
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237675408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.4237675408
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.660576365
Short name T723
Test name
Test status
Simulation time 1505267353 ps
CPU time 10.92 seconds
Started Jun 06 03:11:01 PM PDT 24
Finished Jun 06 03:11:13 PM PDT 24
Peak memory 247788 kb
Host smart-d7260146-f8e7-4aeb-a8cb-1edc0b663216
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=660576365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.660576365
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1378038985
Short name T719
Test name
Test status
Simulation time 10875754 ps
CPU time 1.31 seconds
Started Jun 06 03:17:20 PM PDT 24
Finished Jun 06 03:17:23 PM PDT 24
Peak memory 237064 kb
Host smart-e29ec85b-a7f9-4f14-aae0-d5a1f1814cc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1378038985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.1378038985
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.4293682435
Short name T725
Test name
Test status
Simulation time 12277109 ps
CPU time 1.73 seconds
Started Jun 06 03:17:35 PM PDT 24
Finished Jun 06 03:17:38 PM PDT 24
Peak memory 237072 kb
Host smart-2409eaac-5328-469c-8e03-e56d05df4c68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4293682435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.4293682435
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2314584259
Short name T822
Test name
Test status
Simulation time 45311701 ps
CPU time 1.34 seconds
Started Jun 06 03:17:34 PM PDT 24
Finished Jun 06 03:17:37 PM PDT 24
Peak memory 234980 kb
Host smart-d067011d-f42d-4e29-b72a-fcc1a7282416
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2314584259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2314584259
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.188568342
Short name T777
Test name
Test status
Simulation time 12339485 ps
CPU time 1.67 seconds
Started Jun 06 03:17:35 PM PDT 24
Finished Jun 06 03:17:39 PM PDT 24
Peak memory 236148 kb
Host smart-2a0dcf25-0c2d-46ca-ad8b-b2187e75157c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=188568342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.188568342
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1821849226
Short name T828
Test name
Test status
Simulation time 14073005 ps
CPU time 1.41 seconds
Started Jun 06 03:17:35 PM PDT 24
Finished Jun 06 03:17:39 PM PDT 24
Peak memory 237276 kb
Host smart-7f0fa041-8175-4fc0-beb4-e1c0b80da641
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1821849226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1821849226
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.316691642
Short name T336
Test name
Test status
Simulation time 9983024 ps
CPU time 1.36 seconds
Started Jun 06 03:17:48 PM PDT 24
Finished Jun 06 03:17:51 PM PDT 24
Peak memory 237080 kb
Host smart-3afde588-b39b-46eb-b612-d28a660aa127
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=316691642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.316691642
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.113024366
Short name T738
Test name
Test status
Simulation time 12728807 ps
CPU time 1.42 seconds
Started Jun 06 03:17:49 PM PDT 24
Finished Jun 06 03:17:53 PM PDT 24
Peak memory 237052 kb
Host smart-5a5284da-5454-4df7-b916-a48d9ee0e8d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=113024366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.113024366
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.284506771
Short name T794
Test name
Test status
Simulation time 12758486 ps
CPU time 1.55 seconds
Started Jun 06 03:17:50 PM PDT 24
Finished Jun 06 03:17:53 PM PDT 24
Peak memory 236152 kb
Host smart-ed53de1a-440c-4e2d-ab87-9bfd9aa47245
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=284506771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.284506771
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.657744363
Short name T329
Test name
Test status
Simulation time 10798525 ps
CPU time 1.36 seconds
Started Jun 06 03:18:00 PM PDT 24
Finished Jun 06 03:18:04 PM PDT 24
Peak memory 236148 kb
Host smart-f4e11e97-9968-4640-9d8b-ced72d1761bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=657744363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.657744363
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1709534011
Short name T796
Test name
Test status
Simulation time 27004824 ps
CPU time 1.42 seconds
Started Jun 06 03:18:00 PM PDT 24
Finished Jun 06 03:18:03 PM PDT 24
Peak memory 237084 kb
Host smart-f7e6c466-1dda-48f1-804d-598d899ba682
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1709534011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.1709534011
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3738967148
Short name T757
Test name
Test status
Simulation time 1122401192 ps
CPU time 61.32 seconds
Started Jun 06 03:11:40 PM PDT 24
Finished Jun 06 03:12:44 PM PDT 24
Peak memory 240436 kb
Host smart-3048cd3b-0fe4-4d78-a505-3cc9ad1b5505
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3738967148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3738967148
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.208550739
Short name T773
Test name
Test status
Simulation time 8920639327 ps
CPU time 460.36 seconds
Started Jun 06 03:11:37 PM PDT 24
Finished Jun 06 03:19:21 PM PDT 24
Peak memory 237012 kb
Host smart-0f97dc83-04f7-4729-a5c0-04c0bc962610
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=208550739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.208550739
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2794954278
Short name T766
Test name
Test status
Simulation time 100242899 ps
CPU time 5.08 seconds
Started Jun 06 03:11:37 PM PDT 24
Finished Jun 06 03:11:46 PM PDT 24
Peak memory 240428 kb
Host smart-852ca3a3-5593-4622-8c28-be5f6ade56b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2794954278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2794954278
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2492142351
Short name T762
Test name
Test status
Simulation time 124267046 ps
CPU time 13.17 seconds
Started Jun 06 03:11:39 PM PDT 24
Finished Jun 06 03:11:55 PM PDT 24
Peak memory 250784 kb
Host smart-5d929754-6981-4160-96b4-b8d154f766fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492142351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2492142351
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2680371679
Short name T776
Test name
Test status
Simulation time 188307507 ps
CPU time 5.24 seconds
Started Jun 06 03:11:44 PM PDT 24
Finished Jun 06 03:11:51 PM PDT 24
Peak memory 236932 kb
Host smart-8482dfc4-c212-496a-986a-4a3cdd5e8a78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2680371679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2680371679
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2174287711
Short name T815
Test name
Test status
Simulation time 7812879 ps
CPU time 1.39 seconds
Started Jun 06 03:11:39 PM PDT 24
Finished Jun 06 03:11:43 PM PDT 24
Peak memory 237064 kb
Host smart-88fb8470-e5e5-4284-bf74-9393edaaab73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2174287711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2174287711
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.534374195
Short name T755
Test name
Test status
Simulation time 212254981 ps
CPU time 30.15 seconds
Started Jun 06 03:11:38 PM PDT 24
Finished Jun 06 03:12:11 PM PDT 24
Peak memory 244316 kb
Host smart-6a1796fc-803f-4d3d-b9fc-9aa40b21d3fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=534374195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outs
tanding.534374195
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1942208444
Short name T156
Test name
Test status
Simulation time 6421828108 ps
CPU time 432.81 seconds
Started Jun 06 03:11:23 PM PDT 24
Finished Jun 06 03:18:37 PM PDT 24
Peak memory 265440 kb
Host smart-fa10b3bf-1862-45bf-b03b-6d92967c1f59
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1942208444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1942208444
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2555330698
Short name T125
Test name
Test status
Simulation time 12312900323 ps
CPU time 508.08 seconds
Started Jun 06 03:11:23 PM PDT 24
Finished Jun 06 03:19:52 PM PDT 24
Peak memory 265708 kb
Host smart-4354abf9-7585-4deb-87b2-479413609f71
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555330698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2555330698
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.398588807
Short name T786
Test name
Test status
Simulation time 110847410 ps
CPU time 4.34 seconds
Started Jun 06 03:11:22 PM PDT 24
Finished Jun 06 03:11:27 PM PDT 24
Peak memory 250176 kb
Host smart-2edeca5d-6cee-46a5-97dd-ac1dd9c6060b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=398588807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.398588807
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1867610490
Short name T788
Test name
Test status
Simulation time 6357372 ps
CPU time 1.37 seconds
Started Jun 06 03:17:59 PM PDT 24
Finished Jun 06 03:18:03 PM PDT 24
Peak memory 237048 kb
Host smart-c7327c60-c2d7-45a2-b856-248f7877bbbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1867610490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1867610490
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2726564631
Short name T806
Test name
Test status
Simulation time 10250081 ps
CPU time 1.72 seconds
Started Jun 06 03:17:59 PM PDT 24
Finished Jun 06 03:18:03 PM PDT 24
Peak memory 237072 kb
Host smart-4b0fe991-0be9-47b7-9612-7f702dd6f8b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2726564631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2726564631
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3057246140
Short name T818
Test name
Test status
Simulation time 21871632 ps
CPU time 1.38 seconds
Started Jun 06 03:17:59 PM PDT 24
Finished Jun 06 03:18:02 PM PDT 24
Peak memory 235116 kb
Host smart-ad2e3b1c-ec90-4487-84a3-fa3092fd23a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3057246140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3057246140
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.4240347392
Short name T235
Test name
Test status
Simulation time 11903142 ps
CPU time 1.73 seconds
Started Jun 06 03:18:00 PM PDT 24
Finished Jun 06 03:18:04 PM PDT 24
Peak memory 236120 kb
Host smart-d2de28ae-ab20-4fc5-b52c-98a6d25cf9e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4240347392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.4240347392
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.4281404805
Short name T332
Test name
Test status
Simulation time 15086085 ps
CPU time 1.22 seconds
Started Jun 06 03:18:11 PM PDT 24
Finished Jun 06 03:18:14 PM PDT 24
Peak memory 236116 kb
Host smart-d7e39dfc-4f52-4981-b1e7-c952b670da0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4281404805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.4281404805
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1287530612
Short name T803
Test name
Test status
Simulation time 11305422 ps
CPU time 1.68 seconds
Started Jun 06 03:18:10 PM PDT 24
Finished Jun 06 03:18:14 PM PDT 24
Peak memory 237056 kb
Host smart-9ba4b5d7-0bc7-4ff0-b1e1-0b7940f473eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1287530612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1287530612
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2392740217
Short name T768
Test name
Test status
Simulation time 12927348 ps
CPU time 1.71 seconds
Started Jun 06 03:18:10 PM PDT 24
Finished Jun 06 03:18:15 PM PDT 24
Peak memory 237068 kb
Host smart-fd87f8b9-6053-46c3-b106-d7fc0c445f2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2392740217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.2392740217
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2524107637
Short name T756
Test name
Test status
Simulation time 19070613 ps
CPU time 1.5 seconds
Started Jun 06 03:18:10 PM PDT 24
Finished Jun 06 03:18:14 PM PDT 24
Peak memory 236116 kb
Host smart-4dad2133-f486-4365-a658-090ca7b47ff7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2524107637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.2524107637
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.4279685682
Short name T746
Test name
Test status
Simulation time 11524317 ps
CPU time 1.38 seconds
Started Jun 06 03:18:24 PM PDT 24
Finished Jun 06 03:18:27 PM PDT 24
Peak memory 236140 kb
Host smart-e1a94507-17a5-47cd-9551-2489bd393fd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4279685682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.4279685682
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.4121559867
Short name T765
Test name
Test status
Simulation time 4566421710 ps
CPU time 298.22 seconds
Started Jun 06 03:11:49 PM PDT 24
Finished Jun 06 03:16:49 PM PDT 24
Peak memory 240744 kb
Host smart-a1fa4a91-356b-437d-8223-4a528d9eb1d2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4121559867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.4121559867
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1806443120
Short name T732
Test name
Test status
Simulation time 3714883720 ps
CPU time 87.12 seconds
Started Jun 06 03:11:48 PM PDT 24
Finished Jun 06 03:13:16 PM PDT 24
Peak memory 236092 kb
Host smart-7e36ab29-d40e-427e-937b-793b835813ff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1806443120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1806443120
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1919496015
Short name T161
Test name
Test status
Simulation time 75813493 ps
CPU time 4.51 seconds
Started Jun 06 03:11:37 PM PDT 24
Finished Jun 06 03:11:45 PM PDT 24
Peak memory 240428 kb
Host smart-ef75fc6e-5272-4013-ad39-dcbd91416a81
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1919496015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1919496015
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1354061782
Short name T791
Test name
Test status
Simulation time 63450554 ps
CPU time 5.02 seconds
Started Jun 06 03:11:47 PM PDT 24
Finished Jun 06 03:11:53 PM PDT 24
Peak memory 256964 kb
Host smart-34626bf3-3463-4f5e-a60a-1d9837aa86de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354061782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.1354061782
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3630967136
Short name T751
Test name
Test status
Simulation time 266387183 ps
CPU time 5.6 seconds
Started Jun 06 03:11:38 PM PDT 24
Finished Jun 06 03:11:46 PM PDT 24
Peak memory 236884 kb
Host smart-1e6183e5-1174-44ba-8ccf-3002c0a7ffc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3630967136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3630967136
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2463248929
Short name T795
Test name
Test status
Simulation time 12077786 ps
CPU time 1.4 seconds
Started Jun 06 03:11:41 PM PDT 24
Finished Jun 06 03:11:44 PM PDT 24
Peak memory 236148 kb
Host smart-7c45952c-8f8e-409d-9d2b-d91e745e24fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2463248929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2463248929
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3442227780
Short name T802
Test name
Test status
Simulation time 619506835 ps
CPU time 25.43 seconds
Started Jun 06 03:11:50 PM PDT 24
Finished Jun 06 03:12:17 PM PDT 24
Peak memory 245208 kb
Host smart-18251d42-bb39-4be5-a7cf-297ddcdd566a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3442227780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3442227780
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3568862922
Short name T123
Test name
Test status
Simulation time 59795297219 ps
CPU time 1170.88 seconds
Started Jun 06 03:11:38 PM PDT 24
Finished Jun 06 03:31:12 PM PDT 24
Peak memory 265632 kb
Host smart-5f6f29cf-b209-49a4-846c-e61368c1ae93
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568862922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.3568862922
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1092368095
Short name T826
Test name
Test status
Simulation time 55248467 ps
CPU time 7.85 seconds
Started Jun 06 03:11:41 PM PDT 24
Finished Jun 06 03:11:51 PM PDT 24
Peak memory 252352 kb
Host smart-97d0a736-11b7-4635-b1ec-7a8fc9a861e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1092368095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1092368095
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.1038546502
Short name T163
Test name
Test status
Simulation time 6815182 ps
CPU time 1.41 seconds
Started Jun 06 03:18:24 PM PDT 24
Finished Jun 06 03:18:27 PM PDT 24
Peak memory 236272 kb
Host smart-9b3aca76-0691-4bd5-aec9-3ec6718457ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1038546502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.1038546502
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1383726794
Short name T761
Test name
Test status
Simulation time 14673556 ps
CPU time 1.34 seconds
Started Jun 06 03:18:26 PM PDT 24
Finished Jun 06 03:18:28 PM PDT 24
Peak memory 235056 kb
Host smart-ba6e93d8-7883-4ec2-818e-0adbaa3e29d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1383726794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1383726794
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2145547467
Short name T334
Test name
Test status
Simulation time 17579307 ps
CPU time 1.23 seconds
Started Jun 06 03:19:04 PM PDT 24
Finished Jun 06 03:19:06 PM PDT 24
Peak memory 235100 kb
Host smart-893785f0-64bb-47f3-9afb-9c6bdb3dade5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2145547467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2145547467
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2300782450
Short name T236
Test name
Test status
Simulation time 20438193 ps
CPU time 1.38 seconds
Started Jun 06 03:18:36 PM PDT 24
Finished Jun 06 03:18:38 PM PDT 24
Peak memory 237076 kb
Host smart-46792654-4e36-4c55-869f-9c14da45a3f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2300782450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2300782450
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2759759611
Short name T784
Test name
Test status
Simulation time 30491586 ps
CPU time 1.44 seconds
Started Jun 06 03:18:40 PM PDT 24
Finished Jun 06 03:18:43 PM PDT 24
Peak memory 236096 kb
Host smart-9b77b4fa-72f5-4167-b464-c690771812cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2759759611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2759759611
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.467294183
Short name T819
Test name
Test status
Simulation time 16414887 ps
CPU time 1.35 seconds
Started Jun 06 03:18:41 PM PDT 24
Finished Jun 06 03:18:43 PM PDT 24
Peak memory 235080 kb
Host smart-79768f1b-ad65-4c5f-a8a4-8a2c97b83c9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=467294183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.467294183
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1344868181
Short name T804
Test name
Test status
Simulation time 8109925 ps
CPU time 1.53 seconds
Started Jun 06 03:18:36 PM PDT 24
Finished Jun 06 03:18:39 PM PDT 24
Peak memory 237036 kb
Host smart-4d0299d8-190e-4f95-8fbb-9b0bbbd0d909
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1344868181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.1344868181
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2237674327
Short name T813
Test name
Test status
Simulation time 7501014 ps
CPU time 1.48 seconds
Started Jun 06 03:18:36 PM PDT 24
Finished Jun 06 03:18:39 PM PDT 24
Peak memory 236096 kb
Host smart-9ab8d91c-30b5-4f09-ae9d-443861b1bcc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2237674327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2237674327
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1678389250
Short name T731
Test name
Test status
Simulation time 24883962 ps
CPU time 1.46 seconds
Started Jun 06 03:18:49 PM PDT 24
Finished Jun 06 03:18:53 PM PDT 24
Peak memory 235096 kb
Host smart-9bd38df5-d7c6-4b42-9074-07c71d16e6fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1678389250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1678389250
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.4175862174
Short name T824
Test name
Test status
Simulation time 6707506 ps
CPU time 1.46 seconds
Started Jun 06 03:18:50 PM PDT 24
Finished Jun 06 03:18:53 PM PDT 24
Peak memory 236176 kb
Host smart-c0828de0-0c0b-4a17-81d1-5c8c1b88b83a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4175862174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.4175862174
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.258795097
Short name T778
Test name
Test status
Simulation time 732347067 ps
CPU time 14.12 seconds
Started Jun 06 03:12:14 PM PDT 24
Finished Jun 06 03:12:30 PM PDT 24
Peak memory 251348 kb
Host smart-55a3a9a8-caed-4249-ab78-3bc77404ca18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258795097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.258795097
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3367070254
Short name T764
Test name
Test status
Simulation time 727047706 ps
CPU time 5.13 seconds
Started Jun 06 03:12:12 PM PDT 24
Finished Jun 06 03:12:18 PM PDT 24
Peak memory 236956 kb
Host smart-36fabe5d-8809-4405-a389-5132e17839fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3367070254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3367070254
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2413166616
Short name T739
Test name
Test status
Simulation time 14208182 ps
CPU time 1.29 seconds
Started Jun 06 03:11:59 PM PDT 24
Finished Jun 06 03:12:01 PM PDT 24
Peak memory 237044 kb
Host smart-b5d9b109-91ce-4ea0-a6e6-5db287494c81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2413166616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2413166616
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.897556939
Short name T820
Test name
Test status
Simulation time 1471525519 ps
CPU time 17.38 seconds
Started Jun 06 03:12:12 PM PDT 24
Finished Jun 06 03:12:30 PM PDT 24
Peak memory 248664 kb
Host smart-d14ea600-0e87-4cc8-a0bb-e8b696b799d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=897556939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.897556939
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1457978472
Short name T152
Test name
Test status
Simulation time 20684935867 ps
CPU time 401.15 seconds
Started Jun 06 03:11:51 PM PDT 24
Finished Jun 06 03:18:33 PM PDT 24
Peak memory 273324 kb
Host smart-8abf6c67-d789-41d7-93a7-07e433223691
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1457978472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.1457978472
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.410352851
Short name T724
Test name
Test status
Simulation time 117596740 ps
CPU time 12.07 seconds
Started Jun 06 03:11:58 PM PDT 24
Finished Jun 06 03:12:12 PM PDT 24
Peak memory 253380 kb
Host smart-d92a49ae-e39d-4612-813e-ede4beae66c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=410352851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.410352851
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3752765939
Short name T194
Test name
Test status
Simulation time 96551678 ps
CPU time 4.21 seconds
Started Jun 06 03:11:58 PM PDT 24
Finished Jun 06 03:12:03 PM PDT 24
Peak memory 237200 kb
Host smart-8b584bd2-e987-4ca6-b907-76d748286ac0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3752765939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3752765939
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1576588630
Short name T748
Test name
Test status
Simulation time 120566840 ps
CPU time 5.65 seconds
Started Jun 06 03:12:23 PM PDT 24
Finished Jun 06 03:12:29 PM PDT 24
Peak memory 251420 kb
Host smart-98994560-10df-4acd-a133-71f8dafcb6b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576588630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1576588630
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1742493890
Short name T829
Test name
Test status
Simulation time 184618981 ps
CPU time 8.09 seconds
Started Jun 06 03:12:22 PM PDT 24
Finished Jun 06 03:12:31 PM PDT 24
Peak memory 236968 kb
Host smart-47e7630f-38a0-4a60-94ed-269a80b17e8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1742493890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1742493890
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3710164834
Short name T792
Test name
Test status
Simulation time 6816180 ps
CPU time 1.49 seconds
Started Jun 06 03:12:24 PM PDT 24
Finished Jun 06 03:12:26 PM PDT 24
Peak memory 237076 kb
Host smart-778a7f77-404a-4e43-9c2d-cd08ca7732b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3710164834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3710164834
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.70897159
Short name T753
Test name
Test status
Simulation time 1015807783 ps
CPU time 36.87 seconds
Started Jun 06 03:12:22 PM PDT 24
Finished Jun 06 03:12:59 PM PDT 24
Peak memory 248684 kb
Host smart-d223d597-ed2d-4d41-a505-de2882c6afaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=70897159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outst
anding.70897159
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2678977837
Short name T130
Test name
Test status
Simulation time 15431526848 ps
CPU time 595.18 seconds
Started Jun 06 03:12:13 PM PDT 24
Finished Jun 06 03:22:09 PM PDT 24
Peak memory 265476 kb
Host smart-b4e1feb4-bca0-40f2-a6b0-1bbadd84aa26
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678977837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2678977837
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1495904974
Short name T247
Test name
Test status
Simulation time 266204533 ps
CPU time 9.92 seconds
Started Jun 06 03:12:12 PM PDT 24
Finished Jun 06 03:12:23 PM PDT 24
Peak memory 248844 kb
Host smart-560211a4-63ab-4db5-ade4-e5a80cd305b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1495904974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1495904974
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1664571916
Short name T246
Test name
Test status
Simulation time 130724525 ps
CPU time 6.24 seconds
Started Jun 06 03:12:52 PM PDT 24
Finished Jun 06 03:12:59 PM PDT 24
Peak memory 240540 kb
Host smart-3d66a370-5e30-42df-8f0d-57e1b4ad54ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664571916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.1664571916
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1672554117
Short name T752
Test name
Test status
Simulation time 68369009 ps
CPU time 4.16 seconds
Started Jun 06 03:12:45 PM PDT 24
Finished Jun 06 03:12:50 PM PDT 24
Peak memory 239592 kb
Host smart-909c3836-5115-4e28-87dd-1b0b0e7ab50f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1672554117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1672554117
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1827308869
Short name T726
Test name
Test status
Simulation time 8306487 ps
CPU time 1.55 seconds
Started Jun 06 03:12:45 PM PDT 24
Finished Jun 06 03:12:48 PM PDT 24
Peak memory 236080 kb
Host smart-ae79d1f0-c539-4ea4-b58c-05556b2d8b4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1827308869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1827308869
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.920258247
Short name T810
Test name
Test status
Simulation time 177339235 ps
CPU time 26.95 seconds
Started Jun 06 03:12:47 PM PDT 24
Finished Jun 06 03:13:14 PM PDT 24
Peak memory 245264 kb
Host smart-081b0acc-a33a-4485-b827-45c4b723f9a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=920258247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outs
tanding.920258247
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3919677864
Short name T147
Test name
Test status
Simulation time 2224996297 ps
CPU time 245.99 seconds
Started Jun 06 03:12:31 PM PDT 24
Finished Jun 06 03:16:38 PM PDT 24
Peak memory 265512 kb
Host smart-3d85669a-9fb3-422a-90fb-7f7206a25c1d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3919677864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3919677864
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.631840767
Short name T141
Test name
Test status
Simulation time 12490002374 ps
CPU time 469.14 seconds
Started Jun 06 03:12:32 PM PDT 24
Finished Jun 06 03:20:22 PM PDT 24
Peak memory 265544 kb
Host smart-82f64796-b9d9-4df9-86cf-9b8b2af45aad
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631840767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.631840767
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1159074503
Short name T782
Test name
Test status
Simulation time 1364524681 ps
CPU time 14.4 seconds
Started Jun 06 03:12:58 PM PDT 24
Finished Jun 06 03:13:14 PM PDT 24
Peak memory 248604 kb
Host smart-9890d62a-0fac-4fa7-99be-4c7f9455992c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1159074503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1159074503
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.4093151905
Short name T827
Test name
Test status
Simulation time 24434246 ps
CPU time 2.38 seconds
Started Jun 06 03:12:32 PM PDT 24
Finished Jun 06 03:12:36 PM PDT 24
Peak memory 236096 kb
Host smart-d432d258-5f25-4aa7-b35c-caee4cc308e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4093151905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.4093151905
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2840881261
Short name T779
Test name
Test status
Simulation time 184792337 ps
CPU time 14.65 seconds
Started Jun 06 03:13:16 PM PDT 24
Finished Jun 06 03:13:32 PM PDT 24
Peak memory 250996 kb
Host smart-af1091f4-9e73-40f4-8628-5b65155729dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840881261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.2840881261
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2883071
Short name T339
Test name
Test status
Simulation time 71225859 ps
CPU time 5.18 seconds
Started Jun 06 03:13:17 PM PDT 24
Finished Jun 06 03:13:24 PM PDT 24
Peak memory 236956 kb
Host smart-8b9dd3f2-79fc-43ef-a0a4-5da3928fb951
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2883071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2883071
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.767186814
Short name T758
Test name
Test status
Simulation time 11561594 ps
CPU time 1.38 seconds
Started Jun 06 03:13:03 PM PDT 24
Finished Jun 06 03:13:06 PM PDT 24
Peak memory 237028 kb
Host smart-f6653b01-8c0d-4004-b584-cf45187c0133
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=767186814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.767186814
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.127455519
Short name T730
Test name
Test status
Simulation time 710031670 ps
CPU time 25.93 seconds
Started Jun 06 03:13:18 PM PDT 24
Finished Jun 06 03:13:45 PM PDT 24
Peak memory 248736 kb
Host smart-fa492e79-4393-42a9-9d95-85aadd7f6b5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=127455519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.127455519
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1649124099
Short name T136
Test name
Test status
Simulation time 3597396117 ps
CPU time 448.73 seconds
Started Jun 06 03:12:50 PM PDT 24
Finished Jun 06 03:20:21 PM PDT 24
Peak memory 265456 kb
Host smart-1b351a60-c8a8-401f-96fb-b367da6acb62
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649124099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.1649124099
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3954900729
Short name T745
Test name
Test status
Simulation time 37163803 ps
CPU time 7.42 seconds
Started Jun 06 03:13:03 PM PDT 24
Finished Jun 06 03:13:11 PM PDT 24
Peak memory 248432 kb
Host smart-65335a04-0391-4c45-ad19-07958d883f5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3954900729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3954900729
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1327878526
Short name T195
Test name
Test status
Simulation time 34441808 ps
CPU time 3.06 seconds
Started Jun 06 03:13:04 PM PDT 24
Finished Jun 06 03:13:08 PM PDT 24
Peak memory 236100 kb
Host smart-94c503dc-d2ec-44d0-b37f-8866995fcfbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1327878526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1327878526
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3971417881
Short name T742
Test name
Test status
Simulation time 114277666 ps
CPU time 4.99 seconds
Started Jun 06 03:13:40 PM PDT 24
Finished Jun 06 03:13:46 PM PDT 24
Peak memory 248832 kb
Host smart-85339489-923e-4512-9d6b-da1daa5ef29d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971417881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3971417881
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2722442790
Short name T772
Test name
Test status
Simulation time 110052782 ps
CPU time 6.61 seconds
Started Jun 06 03:13:28 PM PDT 24
Finished Jun 06 03:13:36 PM PDT 24
Peak memory 240428 kb
Host smart-7aae8842-5b49-4851-8773-a27d583aa05c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2722442790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2722442790
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1441001492
Short name T767
Test name
Test status
Simulation time 15851453 ps
CPU time 1.53 seconds
Started Jun 06 03:13:28 PM PDT 24
Finished Jun 06 03:13:30 PM PDT 24
Peak memory 236124 kb
Host smart-293c8e62-aeb2-4c10-86bc-a0d14ed1ce98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1441001492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1441001492
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.637896928
Short name T759
Test name
Test status
Simulation time 692570275 ps
CPU time 21.15 seconds
Started Jun 06 03:13:31 PM PDT 24
Finished Jun 06 03:13:53 PM PDT 24
Peak memory 244088 kb
Host smart-511ed9fa-a5f8-4df0-83a4-63cc8d0d9166
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=637896928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outs
tanding.637896928
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2292417144
Short name T153
Test name
Test status
Simulation time 14507100906 ps
CPU time 152.86 seconds
Started Jun 06 03:13:18 PM PDT 24
Finished Jun 06 03:15:52 PM PDT 24
Peak memory 265448 kb
Host smart-cdc5b355-5b31-421a-8a1b-aebd26302f73
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2292417144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.2292417144
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3940936810
Short name T825
Test name
Test status
Simulation time 229917672 ps
CPU time 20.44 seconds
Started Jun 06 03:13:27 PM PDT 24
Finished Jun 06 03:13:49 PM PDT 24
Peak memory 248752 kb
Host smart-892171d6-2d4d-44cc-beb2-c795e45a624f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3940936810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3940936810
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3013225135
Short name T34
Test name
Test status
Simulation time 32762660609 ps
CPU time 1381.35 seconds
Started Jun 06 03:12:00 PM PDT 24
Finished Jun 06 03:35:03 PM PDT 24
Peak memory 288292 kb
Host smart-91e773b1-ca23-4033-83ba-6a577b706295
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013225135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3013225135
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.214074715
Short name T579
Test name
Test status
Simulation time 706036522 ps
CPU time 11.76 seconds
Started Jun 06 03:12:11 PM PDT 24
Finished Jun 06 03:12:23 PM PDT 24
Peak memory 240556 kb
Host smart-d18ba851-e889-43e7-823b-67514d29bc91
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=214074715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.214074715
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.326842982
Short name T546
Test name
Test status
Simulation time 12939084814 ps
CPU time 225.24 seconds
Started Jun 06 03:11:48 PM PDT 24
Finished Jun 06 03:15:34 PM PDT 24
Peak memory 249836 kb
Host smart-395a7e4f-047c-4336-9802-c762a1b92b85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32684
2982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.326842982
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1936815917
Short name T433
Test name
Test status
Simulation time 398936798 ps
CPU time 25.34 seconds
Started Jun 06 03:11:49 PM PDT 24
Finished Jun 06 03:12:16 PM PDT 24
Peak memory 248768 kb
Host smart-20d35cea-6a33-4a7f-bec7-70e32a68da9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19368
15917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1936815917
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.3540178182
Short name T521
Test name
Test status
Simulation time 39820864740 ps
CPU time 2278.47 seconds
Started Jun 06 03:11:58 PM PDT 24
Finished Jun 06 03:49:58 PM PDT 24
Peak memory 271352 kb
Host smart-e31486fa-744c-4664-a177-bd02c0d45467
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540178182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.3540178182
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.218721457
Short name T701
Test name
Test status
Simulation time 144842961920 ps
CPU time 2089.65 seconds
Started Jun 06 03:11:58 PM PDT 24
Finished Jun 06 03:46:49 PM PDT 24
Peak memory 273364 kb
Host smart-641632aa-518c-490c-a26d-57f7f95de707
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218721457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.218721457
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.876372518
Short name T229
Test name
Test status
Simulation time 37901306828 ps
CPU time 202.02 seconds
Started Jun 06 03:11:58 PM PDT 24
Finished Jun 06 03:15:21 PM PDT 24
Peak memory 248952 kb
Host smart-731b90d8-d412-4dcc-80b2-7c457de43b86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876372518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.876372518
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.2429794704
Short name T518
Test name
Test status
Simulation time 5940437765 ps
CPU time 28.89 seconds
Started Jun 06 03:11:39 PM PDT 24
Finished Jun 06 03:12:11 PM PDT 24
Peak memory 248828 kb
Host smart-43227ad7-e202-4807-a738-9b7c9309e669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24297
94704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2429794704
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.2198140213
Short name T25
Test name
Test status
Simulation time 2728552260 ps
CPU time 17 seconds
Started Jun 06 03:11:41 PM PDT 24
Finished Jun 06 03:12:00 PM PDT 24
Peak memory 248828 kb
Host smart-72ed964b-e6d9-43ab-919b-c74107ab5270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21981
40213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2198140213
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.2223151574
Short name T31
Test name
Test status
Simulation time 208670611 ps
CPU time 13.85 seconds
Started Jun 06 03:12:35 PM PDT 24
Finished Jun 06 03:12:51 PM PDT 24
Peak memory 277608 kb
Host smart-196e3ae0-92b3-4e06-ba01-29f8cf5284ac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2223151574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2223151574
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.3257788459
Short name T413
Test name
Test status
Simulation time 153669428 ps
CPU time 12.63 seconds
Started Jun 06 03:11:52 PM PDT 24
Finished Jun 06 03:12:05 PM PDT 24
Peak memory 247624 kb
Host smart-b926bb2a-251c-4be7-8718-bb8b172f4bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32577
88459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.3257788459
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.565796482
Short name T678
Test name
Test status
Simulation time 325594928 ps
CPU time 21.88 seconds
Started Jun 06 03:11:41 PM PDT 24
Finished Jun 06 03:12:05 PM PDT 24
Peak memory 248768 kb
Host smart-dd7cdc87-1e6b-4c0c-93a0-1ade0c4a5462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56579
6482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.565796482
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.427079137
Short name T73
Test name
Test status
Simulation time 29879374607 ps
CPU time 1722.34 seconds
Started Jun 06 03:12:32 PM PDT 24
Finished Jun 06 03:41:16 PM PDT 24
Peak memory 273412 kb
Host smart-40889832-d59b-46f1-aa81-981a8850299a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427079137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_hand
ler_stress_all.427079137
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.1357533274
Short name T251
Test name
Test status
Simulation time 24099678341 ps
CPU time 2867.84 seconds
Started Jun 06 03:12:34 PM PDT 24
Finished Jun 06 04:00:25 PM PDT 24
Peak memory 314452 kb
Host smart-7683caf4-af03-4a1f-a3df-4da2b85c3881
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357533274 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.1357533274
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.4154900707
Short name T209
Test name
Test status
Simulation time 82002522 ps
CPU time 3.73 seconds
Started Jun 06 03:13:18 PM PDT 24
Finished Jun 06 03:13:23 PM PDT 24
Peak memory 248916 kb
Host smart-6dd60ef0-be1a-478c-887c-16db057d97ad
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4154900707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.4154900707
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1565880147
Short name T468
Test name
Test status
Simulation time 194562868627 ps
CPU time 2839.92 seconds
Started Jun 06 03:12:55 PM PDT 24
Finished Jun 06 04:00:16 PM PDT 24
Peak memory 289408 kb
Host smart-57eadbb7-34c5-4c25-979b-a38f44f6cb11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565880147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1565880147
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1418769200
Short name T516
Test name
Test status
Simulation time 2428859886 ps
CPU time 25.43 seconds
Started Jun 06 03:13:03 PM PDT 24
Finished Jun 06 03:13:30 PM PDT 24
Peak memory 248872 kb
Host smart-abbca94a-cd9e-4b91-b55c-9c670f6ee563
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1418769200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1418769200
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1405606735
Short name T707
Test name
Test status
Simulation time 13056249646 ps
CPU time 199.11 seconds
Started Jun 06 03:12:51 PM PDT 24
Finished Jun 06 03:16:12 PM PDT 24
Peak memory 256984 kb
Host smart-6be613cc-6140-45e9-bb48-2aece6407ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14056
06735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1405606735
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.2574608615
Short name T578
Test name
Test status
Simulation time 2836418042 ps
CPU time 42.43 seconds
Started Jun 06 03:12:50 PM PDT 24
Finished Jun 06 03:13:34 PM PDT 24
Peak memory 249260 kb
Host smart-f05cd281-6761-4f33-ac41-62d673adbd55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25746
08615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2574608615
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.439912142
Short name T321
Test name
Test status
Simulation time 118925992610 ps
CPU time 2020.41 seconds
Started Jun 06 03:13:04 PM PDT 24
Finished Jun 06 03:46:46 PM PDT 24
Peak memory 289020 kb
Host smart-a4da61b7-a73d-4104-9c53-57e1905d4048
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439912142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.439912142
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1692351465
Short name T283
Test name
Test status
Simulation time 72794565705 ps
CPU time 1516.32 seconds
Started Jun 06 03:13:04 PM PDT 24
Finished Jun 06 03:38:22 PM PDT 24
Peak memory 273444 kb
Host smart-0ff8e8bc-a36e-4aed-9597-e33599610f1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692351465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1692351465
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.1774660395
Short name T296
Test name
Test status
Simulation time 9345026093 ps
CPU time 385.7 seconds
Started Jun 06 03:13:06 PM PDT 24
Finished Jun 06 03:19:32 PM PDT 24
Peak memory 248020 kb
Host smart-f82f6961-cd66-4b85-b8b3-b5f7d84a125d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774660395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1774660395
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.710239919
Short name T386
Test name
Test status
Simulation time 539188651 ps
CPU time 10.91 seconds
Started Jun 06 03:12:47 PM PDT 24
Finished Jun 06 03:13:00 PM PDT 24
Peak memory 248828 kb
Host smart-59984b5a-3598-4872-aa34-82474e7210c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71023
9919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.710239919
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.3146407684
Short name T41
Test name
Test status
Simulation time 310281946 ps
CPU time 15.44 seconds
Started Jun 06 03:12:46 PM PDT 24
Finished Jun 06 03:13:03 PM PDT 24
Peak memory 255288 kb
Host smart-3b14485a-d3f1-407a-b89d-576fb86bc784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31464
07684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3146407684
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3271146527
Short name T32
Test name
Test status
Simulation time 1164642865 ps
CPU time 52.74 seconds
Started Jun 06 03:13:19 PM PDT 24
Finished Jun 06 03:14:13 PM PDT 24
Peak memory 265276 kb
Host smart-deb4e507-e0d1-4112-ba7a-f25d73555b46
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3271146527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3271146527
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.4120780450
Short name T613
Test name
Test status
Simulation time 1177745466 ps
CPU time 25.55 seconds
Started Jun 06 03:12:49 PM PDT 24
Finished Jun 06 03:13:16 PM PDT 24
Peak memory 248772 kb
Host smart-46c5357e-d07e-4f25-825c-18f54f2cfa53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41207
80450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.4120780450
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.1970764738
Short name T487
Test name
Test status
Simulation time 2186446962 ps
CPU time 38.78 seconds
Started Jun 06 03:12:30 PM PDT 24
Finished Jun 06 03:13:10 PM PDT 24
Peak memory 248820 kb
Host smart-aa01dfc8-41e4-435e-933f-ebc2a22482ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19707
64738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1970764738
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.1028310760
Short name T462
Test name
Test status
Simulation time 22463115859 ps
CPU time 1561.98 seconds
Started Jun 06 03:17:13 PM PDT 24
Finished Jun 06 03:43:17 PM PDT 24
Peak memory 273388 kb
Host smart-23732264-4a10-4d54-a750-ed7172bf92c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028310760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1028310760
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3622882989
Short name T576
Test name
Test status
Simulation time 733391482 ps
CPU time 33.65 seconds
Started Jun 06 03:17:49 PM PDT 24
Finished Jun 06 03:18:24 PM PDT 24
Peak memory 240560 kb
Host smart-05571eb0-72a6-4967-b330-2e8fe49b20d0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3622882989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3622882989
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2454196394
Short name T459
Test name
Test status
Simulation time 462621380 ps
CPU time 9.79 seconds
Started Jun 06 03:17:09 PM PDT 24
Finished Jun 06 03:17:21 PM PDT 24
Peak memory 249220 kb
Host smart-dc285dc9-3281-498d-8131-95be977bef84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24541
96394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2454196394
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.1289725232
Short name T420
Test name
Test status
Simulation time 218233097 ps
CPU time 10.2 seconds
Started Jun 06 03:17:12 PM PDT 24
Finished Jun 06 03:17:24 PM PDT 24
Peak memory 252492 kb
Host smart-8e492be8-59cd-4cd7-8d94-7e53b117ed14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12897
25232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.1289725232
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.4122847356
Short name T311
Test name
Test status
Simulation time 67971081845 ps
CPU time 2235.41 seconds
Started Jun 06 03:17:20 PM PDT 24
Finished Jun 06 03:54:38 PM PDT 24
Peak memory 288936 kb
Host smart-d0336160-d66f-498b-bd91-9a19baea66f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122847356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.4122847356
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1156044119
Short name T431
Test name
Test status
Simulation time 22179875558 ps
CPU time 993.52 seconds
Started Jun 06 03:17:20 PM PDT 24
Finished Jun 06 03:33:55 PM PDT 24
Peak memory 282420 kb
Host smart-2fde48b8-f856-4f68-9a97-9e14a52740b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156044119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1156044119
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2315585236
Short name T625
Test name
Test status
Simulation time 4988787443 ps
CPU time 64.23 seconds
Started Jun 06 03:17:10 PM PDT 24
Finished Jun 06 03:18:16 PM PDT 24
Peak memory 248796 kb
Host smart-892af520-9849-4687-a1f6-60a59813b618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23155
85236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2315585236
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.1872065290
Short name T571
Test name
Test status
Simulation time 479066011 ps
CPU time 29.62 seconds
Started Jun 06 03:17:11 PM PDT 24
Finished Jun 06 03:17:42 PM PDT 24
Peak memory 256056 kb
Host smart-853d5be1-1c0b-4bc3-951b-0fd24881b23f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18720
65290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1872065290
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.551104908
Short name T264
Test name
Test status
Simulation time 213431459 ps
CPU time 25.41 seconds
Started Jun 06 03:17:17 PM PDT 24
Finished Jun 06 03:17:44 PM PDT 24
Peak memory 247500 kb
Host smart-791fc98a-931d-4b21-a301-c3f54362b7f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55110
4908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.551104908
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.2449331030
Short name T697
Test name
Test status
Simulation time 1756819480 ps
CPU time 34.21 seconds
Started Jun 06 03:17:03 PM PDT 24
Finished Jun 06 03:17:38 PM PDT 24
Peak memory 248776 kb
Host smart-a4344eee-3592-4933-bc69-9b1f9a0a9496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24493
31030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2449331030
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2378215353
Short name T205
Test name
Test status
Simulation time 603350231 ps
CPU time 4.17 seconds
Started Jun 06 03:17:48 PM PDT 24
Finished Jun 06 03:17:54 PM PDT 24
Peak memory 248872 kb
Host smart-dfd26bd0-71cf-4915-b5fa-6a6333a83a51
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2378215353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2378215353
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.2556378377
Short name T37
Test name
Test status
Simulation time 66482454172 ps
CPU time 1400.21 seconds
Started Jun 06 03:17:49 PM PDT 24
Finished Jun 06 03:41:11 PM PDT 24
Peak memory 272188 kb
Host smart-f1b86b01-8d9a-41d6-9405-3d750e1256dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556378377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2556378377
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.873607617
Short name T503
Test name
Test status
Simulation time 675011265 ps
CPU time 15.87 seconds
Started Jun 06 03:17:50 PM PDT 24
Finished Jun 06 03:18:08 PM PDT 24
Peak memory 248724 kb
Host smart-8c42e681-b809-41b4-9740-7590e266123e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=873607617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.873607617
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.767079667
Short name T249
Test name
Test status
Simulation time 2035711180 ps
CPU time 139.07 seconds
Started Jun 06 03:17:37 PM PDT 24
Finished Jun 06 03:19:57 PM PDT 24
Peak memory 256936 kb
Host smart-cec211e7-8dfc-44a8-835f-074d38ca728e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76707
9667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.767079667
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2972905989
Short name T636
Test name
Test status
Simulation time 1289383487 ps
CPU time 42.08 seconds
Started Jun 06 03:17:36 PM PDT 24
Finished Jun 06 03:18:20 PM PDT 24
Peak memory 255360 kb
Host smart-7bb2ac12-3f51-45bc-a722-5abef2997502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29729
05989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2972905989
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2469869325
Short name T415
Test name
Test status
Simulation time 39879907800 ps
CPU time 2330.17 seconds
Started Jun 06 03:17:49 PM PDT 24
Finished Jun 06 03:56:41 PM PDT 24
Peak memory 289788 kb
Host smart-0a8bb1d5-6fa7-44c8-a7f7-2d94ec3105f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469869325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2469869325
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.856825146
Short name T618
Test name
Test status
Simulation time 25200691959 ps
CPU time 282.11 seconds
Started Jun 06 03:17:49 PM PDT 24
Finished Jun 06 03:22:33 PM PDT 24
Peak memory 248776 kb
Host smart-8b4bffd3-ed64-4ab0-81f4-fdb2684ddd12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856825146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.856825146
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.3265987496
Short name T582
Test name
Test status
Simulation time 335736379 ps
CPU time 26.59 seconds
Started Jun 06 03:17:37 PM PDT 24
Finished Jun 06 03:18:05 PM PDT 24
Peak memory 248752 kb
Host smart-2ee6d526-1c29-4e7b-9b96-60c2b5f2f900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32659
87496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3265987496
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.3716663809
Short name T551
Test name
Test status
Simulation time 1543003141 ps
CPU time 71.5 seconds
Started Jun 06 03:17:35 PM PDT 24
Finished Jun 06 03:18:49 PM PDT 24
Peak memory 256784 kb
Host smart-94e58245-4810-4e5b-8f84-453d556dbfae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37166
63809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3716663809
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.577209473
Short name T557
Test name
Test status
Simulation time 1034810060 ps
CPU time 26.87 seconds
Started Jun 06 03:17:50 PM PDT 24
Finished Jun 06 03:18:18 PM PDT 24
Peak memory 256688 kb
Host smart-9b58ae73-0e55-4d92-bf29-f870d8219d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57720
9473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.577209473
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.729966701
Short name T50
Test name
Test status
Simulation time 1457259586 ps
CPU time 40.84 seconds
Started Jun 06 03:17:36 PM PDT 24
Finished Jun 06 03:18:19 PM PDT 24
Peak memory 248748 kb
Host smart-fc0578c4-7bb9-48fe-8095-e8e5ed6c3384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72996
6701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.729966701
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1650890958
Short name T285
Test name
Test status
Simulation time 124452051612 ps
CPU time 3152.78 seconds
Started Jun 06 03:17:49 PM PDT 24
Finished Jun 06 04:10:25 PM PDT 24
Peak memory 301064 kb
Host smart-6a643d6a-af47-463f-b7d8-a8466ff2a1ce
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650890958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1650890958
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2030767143
Short name T119
Test name
Test status
Simulation time 61630373 ps
CPU time 3.16 seconds
Started Jun 06 03:18:10 PM PDT 24
Finished Jun 06 03:18:15 PM PDT 24
Peak memory 249004 kb
Host smart-670ae78d-0543-48ce-b64b-521d210e142a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2030767143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2030767143
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3310565884
Short name T87
Test name
Test status
Simulation time 19527885716 ps
CPU time 594.9 seconds
Started Jun 06 03:18:01 PM PDT 24
Finished Jun 06 03:27:58 PM PDT 24
Peak memory 265240 kb
Host smart-672ca99d-34ec-4919-882e-5c72d5e4e42c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310565884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3310565884
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.4189006586
Short name T222
Test name
Test status
Simulation time 188922447 ps
CPU time 10.87 seconds
Started Jun 06 03:18:11 PM PDT 24
Finished Jun 06 03:18:24 PM PDT 24
Peak memory 248756 kb
Host smart-f0574cff-e718-42ff-b3d4-9ee353138064
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4189006586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.4189006586
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.1502607235
Short name T456
Test name
Test status
Simulation time 44004450370 ps
CPU time 308.89 seconds
Started Jun 06 03:17:59 PM PDT 24
Finished Jun 06 03:23:10 PM PDT 24
Peak memory 256924 kb
Host smart-9e598780-fc41-49b9-bf09-e99c19b48e89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15026
07235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1502607235
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2939020067
Short name T74
Test name
Test status
Simulation time 31527757 ps
CPU time 4.15 seconds
Started Jun 06 03:18:01 PM PDT 24
Finished Jun 06 03:18:07 PM PDT 24
Peak memory 248764 kb
Host smart-5348c4d8-15c9-4a06-b3dd-719ed491798c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29390
20067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2939020067
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3118855788
Short name T547
Test name
Test status
Simulation time 9127734272 ps
CPU time 725.61 seconds
Started Jun 06 03:18:00 PM PDT 24
Finished Jun 06 03:30:08 PM PDT 24
Peak memory 265200 kb
Host smart-3c723039-bdb0-488e-9bb5-dc1d94e561c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118855788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3118855788
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.3094656163
Short name T573
Test name
Test status
Simulation time 21343481172 ps
CPU time 1013.89 seconds
Started Jun 06 03:17:59 PM PDT 24
Finished Jun 06 03:34:55 PM PDT 24
Peak memory 272972 kb
Host smart-795e051e-806f-4b85-80fe-e293d32c736e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094656163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3094656163
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.3851336985
Short name T102
Test name
Test status
Simulation time 29862611485 ps
CPU time 319.97 seconds
Started Jun 06 03:17:59 PM PDT 24
Finished Jun 06 03:23:21 PM PDT 24
Peak memory 247872 kb
Host smart-32704feb-3347-4b06-a22f-5ea05b6e8531
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851336985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3851336985
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2729275467
Short name T216
Test name
Test status
Simulation time 2049148541 ps
CPU time 55.92 seconds
Started Jun 06 03:18:00 PM PDT 24
Finished Jun 06 03:18:58 PM PDT 24
Peak memory 248828 kb
Host smart-fb4e2471-7adc-418a-ad22-d52d44cc0dae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27292
75467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2729275467
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.4292333645
Short name T56
Test name
Test status
Simulation time 181232161 ps
CPU time 22.81 seconds
Started Jun 06 03:17:58 PM PDT 24
Finished Jun 06 03:18:23 PM PDT 24
Peak memory 256036 kb
Host smart-06788fcd-9734-4325-aac7-d4b78c923112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42923
33645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.4292333645
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3924235127
Short name T669
Test name
Test status
Simulation time 547007254 ps
CPU time 18.03 seconds
Started Jun 06 03:18:01 PM PDT 24
Finished Jun 06 03:18:21 PM PDT 24
Peak memory 255628 kb
Host smart-b79aadd7-4ece-408e-a78b-71611dcafe1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39242
35127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3924235127
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.1821873492
Short name T530
Test name
Test status
Simulation time 169832037 ps
CPU time 9.04 seconds
Started Jun 06 03:17:58 PM PDT 24
Finished Jun 06 03:18:09 PM PDT 24
Peak memory 254300 kb
Host smart-c179949e-49fb-49a1-9268-589e0bd81ecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18218
73492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1821873492
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.1979174064
Short name T255
Test name
Test status
Simulation time 31877139530 ps
CPU time 1986.88 seconds
Started Jun 06 03:18:11 PM PDT 24
Finished Jun 06 03:51:20 PM PDT 24
Peak memory 273464 kb
Host smart-50e030dd-4a4e-49f9-893c-8b310915b1ca
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979174064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.1979174064
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.88422840
Short name T196
Test name
Test status
Simulation time 134005858 ps
CPU time 3.31 seconds
Started Jun 06 03:18:37 PM PDT 24
Finished Jun 06 03:18:41 PM PDT 24
Peak memory 248896 kb
Host smart-b51f80e4-2994-4a73-933c-c7b04e20ce49
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=88422840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.88422840
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.407622489
Short name T398
Test name
Test status
Simulation time 93844849308 ps
CPU time 2757.97 seconds
Started Jun 06 03:18:24 PM PDT 24
Finished Jun 06 04:04:24 PM PDT 24
Peak memory 289084 kb
Host smart-af3c6a72-ff26-4744-a1ff-ed3e0e7189cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407622489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.407622489
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2117167632
Short name T585
Test name
Test status
Simulation time 3415205825 ps
CPU time 52.61 seconds
Started Jun 06 03:18:10 PM PDT 24
Finished Jun 06 03:19:05 PM PDT 24
Peak memory 256908 kb
Host smart-bd94b159-5106-4b87-9ec9-0dc1463ba747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21171
67632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2117167632
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.1813871458
Short name T506
Test name
Test status
Simulation time 1357318417 ps
CPU time 21.58 seconds
Started Jun 06 03:18:10 PM PDT 24
Finished Jun 06 03:18:34 PM PDT 24
Peak memory 249084 kb
Host smart-6609f670-e212-4b19-9bdf-2de1006729df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18138
71458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.1813871458
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.1669447761
Short name T603
Test name
Test status
Simulation time 99896424612 ps
CPU time 1606.06 seconds
Started Jun 06 03:18:25 PM PDT 24
Finished Jun 06 03:45:12 PM PDT 24
Peak memory 270380 kb
Host smart-bd51706f-d3d3-4bb5-a722-fb489771539d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669447761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.1669447761
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.3039035291
Short name T298
Test name
Test status
Simulation time 3109002330 ps
CPU time 109.47 seconds
Started Jun 06 03:18:26 PM PDT 24
Finished Jun 06 03:20:16 PM PDT 24
Peak memory 247948 kb
Host smart-4c33c07d-8b93-4397-aae1-914c72bd7e4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039035291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3039035291
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2296431750
Short name T535
Test name
Test status
Simulation time 682952080 ps
CPU time 27.01 seconds
Started Jun 06 03:18:10 PM PDT 24
Finished Jun 06 03:18:40 PM PDT 24
Peak memory 248760 kb
Host smart-6058c4a4-262a-4bba-a91f-0e80e1c2322b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22964
31750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2296431750
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2701199996
Short name T488
Test name
Test status
Simulation time 324602730 ps
CPU time 31.49 seconds
Started Jun 06 03:18:09 PM PDT 24
Finished Jun 06 03:18:42 PM PDT 24
Peak memory 248796 kb
Host smart-6992b3f2-b4c0-416a-bc9d-2d50f5afa058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27011
99996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2701199996
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.4159781142
Short name T18
Test name
Test status
Simulation time 207000764 ps
CPU time 16.32 seconds
Started Jun 06 03:18:24 PM PDT 24
Finished Jun 06 03:18:41 PM PDT 24
Peak memory 248720 kb
Host smart-657fc558-badd-42da-b93a-cceef8b7602f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41597
81142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.4159781142
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1945248193
Short name T504
Test name
Test status
Simulation time 296637104 ps
CPU time 20.49 seconds
Started Jun 06 03:18:10 PM PDT 24
Finished Jun 06 03:18:33 PM PDT 24
Peak memory 248756 kb
Host smart-78b08929-4422-4483-8990-c9396a979f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19452
48193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1945248193
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.568280431
Short name T30
Test name
Test status
Simulation time 85653687811 ps
CPU time 2062.37 seconds
Started Jun 06 03:18:38 PM PDT 24
Finished Jun 06 03:53:02 PM PDT 24
Peak memory 305880 kb
Host smart-fc919f39-223a-48a3-8d21-81eca9c28292
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568280431 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.568280431
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3681169877
Short name T206
Test name
Test status
Simulation time 87011855 ps
CPU time 4.08 seconds
Started Jun 06 03:18:48 PM PDT 24
Finished Jun 06 03:18:54 PM PDT 24
Peak memory 248948 kb
Host smart-234f31d6-3278-4feb-8f10-c09198fb37bb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3681169877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3681169877
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3133943745
Short name T409
Test name
Test status
Simulation time 28371073246 ps
CPU time 1652.53 seconds
Started Jun 06 03:18:40 PM PDT 24
Finished Jun 06 03:46:14 PM PDT 24
Peak memory 266192 kb
Host smart-06c6434b-b34c-42c2-985a-75a6ee590907
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133943745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3133943745
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.780167197
Short name T443
Test name
Test status
Simulation time 3522175576 ps
CPU time 32.29 seconds
Started Jun 06 03:18:47 PM PDT 24
Finished Jun 06 03:19:21 PM PDT 24
Peak memory 248816 kb
Host smart-8abcbf94-b6bf-4da5-a6eb-d93546f0c77a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=780167197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.780167197
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.3613980281
Short name T684
Test name
Test status
Simulation time 9476581874 ps
CPU time 155.12 seconds
Started Jun 06 03:18:40 PM PDT 24
Finished Jun 06 03:21:17 PM PDT 24
Peak memory 256820 kb
Host smart-fdbd3201-a77f-4744-be24-0fd111fe50a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36139
80281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3613980281
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3691907768
Short name T564
Test name
Test status
Simulation time 91261596 ps
CPU time 7.39 seconds
Started Jun 06 03:18:38 PM PDT 24
Finished Jun 06 03:18:47 PM PDT 24
Peak memory 249052 kb
Host smart-afa58a82-0119-4659-b95b-6d5b161528ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36919
07768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3691907768
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1291049664
Short name T460
Test name
Test status
Simulation time 9079456660 ps
CPU time 712.18 seconds
Started Jun 06 03:18:40 PM PDT 24
Finished Jun 06 03:30:34 PM PDT 24
Peak memory 272556 kb
Host smart-0afd384c-5308-4513-ae37-9b11f6fe6a75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291049664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1291049664
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1995648778
Short name T623
Test name
Test status
Simulation time 206962992628 ps
CPU time 3324.19 seconds
Started Jun 06 03:18:48 PM PDT 24
Finished Jun 06 04:14:14 PM PDT 24
Peak memory 289276 kb
Host smart-9797936f-01d0-49d6-a808-7fafb0d102a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995648778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1995648778
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3462457655
Short name T67
Test name
Test status
Simulation time 23871838641 ps
CPU time 227.73 seconds
Started Jun 06 03:18:38 PM PDT 24
Finished Jun 06 03:22:27 PM PDT 24
Peak memory 256288 kb
Host smart-dcf817af-7176-48c0-ae14-c56487f7bc97
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462457655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3462457655
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.3267502580
Short name T642
Test name
Test status
Simulation time 17807072264 ps
CPU time 61.21 seconds
Started Jun 06 03:18:39 PM PDT 24
Finished Jun 06 03:19:42 PM PDT 24
Peak memory 256948 kb
Host smart-1c4ff61a-5d70-4561-be8e-10c77ac6fe65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32675
02580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3267502580
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1994502522
Short name T555
Test name
Test status
Simulation time 1074186169 ps
CPU time 35.73 seconds
Started Jun 06 03:18:40 PM PDT 24
Finished Jun 06 03:19:18 PM PDT 24
Peak memory 255820 kb
Host smart-eeead5d1-8206-428d-a8d0-09eb0adf8d3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19945
02522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1994502522
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.1350371730
Short name T647
Test name
Test status
Simulation time 60606369 ps
CPU time 7.53 seconds
Started Jun 06 03:18:38 PM PDT 24
Finished Jun 06 03:18:48 PM PDT 24
Peak memory 248760 kb
Host smart-05301c5c-27c8-4a15-abd3-7d68ac24113a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13503
71730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1350371730
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.149707266
Short name T406
Test name
Test status
Simulation time 35928235482 ps
CPU time 573.54 seconds
Started Jun 06 03:18:47 PM PDT 24
Finished Jun 06 03:28:22 PM PDT 24
Peak memory 257004 kb
Host smart-8dae9ee1-5bf3-49d7-83ed-13215e8e77a4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149707266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_han
dler_stress_all.149707266
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.1959322387
Short name T399
Test name
Test status
Simulation time 9505268958 ps
CPU time 993.55 seconds
Started Jun 06 03:18:49 PM PDT 24
Finished Jun 06 03:35:25 PM PDT 24
Peak memory 289316 kb
Host smart-ed3affc8-8e9b-4bbe-9fc3-94bb5830a709
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959322387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1959322387
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1496710336
Short name T709
Test name
Test status
Simulation time 453228133 ps
CPU time 22.3 seconds
Started Jun 06 03:19:03 PM PDT 24
Finished Jun 06 03:19:27 PM PDT 24
Peak memory 248744 kb
Host smart-b4ea8996-56a5-4f1e-8352-3e4505c5a099
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1496710336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1496710336
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3826286381
Short name T253
Test name
Test status
Simulation time 19026640532 ps
CPU time 242.36 seconds
Started Jun 06 03:18:50 PM PDT 24
Finished Jun 06 03:22:54 PM PDT 24
Peak memory 250996 kb
Host smart-72523a10-de7d-4b65-9bb7-862b39835227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38262
86381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3826286381
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.2176710613
Short name T223
Test name
Test status
Simulation time 148588171 ps
CPU time 11.14 seconds
Started Jun 06 03:18:48 PM PDT 24
Finished Jun 06 03:19:01 PM PDT 24
Peak memory 248776 kb
Host smart-fd14a808-3098-4f68-b8e0-d9b74819bd83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21767
10613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2176710613
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.1911954869
Short name T401
Test name
Test status
Simulation time 13356157483 ps
CPU time 1489.2 seconds
Started Jun 06 03:19:02 PM PDT 24
Finished Jun 06 03:43:53 PM PDT 24
Peak memory 289796 kb
Host smart-a73bb8df-315a-4d33-9675-0dee27620d91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911954869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1911954869
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3676519303
Short name T674
Test name
Test status
Simulation time 16046429920 ps
CPU time 1280.85 seconds
Started Jun 06 03:19:02 PM PDT 24
Finished Jun 06 03:40:25 PM PDT 24
Peak memory 265212 kb
Host smart-a2412877-1233-40fa-a652-e5749072e50e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676519303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3676519303
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.375581874
Short name T635
Test name
Test status
Simulation time 675058186 ps
CPU time 47.08 seconds
Started Jun 06 03:18:49 PM PDT 24
Finished Jun 06 03:19:38 PM PDT 24
Peak memory 255484 kb
Host smart-0379c87c-2500-41a3-baec-c52b564f5357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37558
1874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.375581874
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1589130619
Short name T227
Test name
Test status
Simulation time 410801294 ps
CPU time 16.12 seconds
Started Jun 06 03:18:49 PM PDT 24
Finished Jun 06 03:19:07 PM PDT 24
Peak memory 248720 kb
Host smart-16dbf954-880c-470e-8d6c-002efdd1b98b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15891
30619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1589130619
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1577376404
Short name T565
Test name
Test status
Simulation time 3744441530 ps
CPU time 57.7 seconds
Started Jun 06 03:18:50 PM PDT 24
Finished Jun 06 03:19:49 PM PDT 24
Peak memory 256064 kb
Host smart-d9fcb055-fbb2-4c95-9a78-a291e9d404a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15773
76404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1577376404
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.1595534362
Short name T489
Test name
Test status
Simulation time 871837992 ps
CPU time 53.19 seconds
Started Jun 06 03:19:01 PM PDT 24
Finished Jun 06 03:19:56 PM PDT 24
Peak memory 248748 kb
Host smart-b87ea71b-456e-4c14-bfc4-648235c9453e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595534362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.1595534362
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1571478068
Short name T200
Test name
Test status
Simulation time 610105725 ps
CPU time 3.58 seconds
Started Jun 06 03:19:14 PM PDT 24
Finished Jun 06 03:19:19 PM PDT 24
Peak memory 248908 kb
Host smart-92e4c331-198b-49cc-a657-59e2098ce27c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1571478068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1571478068
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1212651968
Short name T706
Test name
Test status
Simulation time 99772155869 ps
CPU time 1240.74 seconds
Started Jun 06 03:19:01 PM PDT 24
Finished Jun 06 03:39:44 PM PDT 24
Peak memory 273404 kb
Host smart-1864e229-326b-428e-964a-c79f0bbfb239
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212651968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1212651968
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.577570806
Short name T442
Test name
Test status
Simulation time 2379136203 ps
CPU time 42.37 seconds
Started Jun 06 03:19:16 PM PDT 24
Finished Jun 06 03:20:00 PM PDT 24
Peak memory 248860 kb
Host smart-875f9598-b78f-4cdf-9101-b46af4570793
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=577570806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.577570806
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.1682118594
Short name T228
Test name
Test status
Simulation time 31700901601 ps
CPU time 216.76 seconds
Started Jun 06 03:19:01 PM PDT 24
Finished Jun 06 03:22:40 PM PDT 24
Peak memory 256864 kb
Host smart-610b0250-643a-47e0-8c48-38f65b449661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16821
18594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1682118594
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2507376627
Short name T181
Test name
Test status
Simulation time 317450266 ps
CPU time 24.84 seconds
Started Jun 06 03:19:01 PM PDT 24
Finished Jun 06 03:19:28 PM PDT 24
Peak memory 254936 kb
Host smart-1229d25c-ded6-46a0-890b-242c726e7392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25073
76627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2507376627
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.2666291111
Short name T284
Test name
Test status
Simulation time 17874341550 ps
CPU time 923.16 seconds
Started Jun 06 03:19:14 PM PDT 24
Finished Jun 06 03:34:39 PM PDT 24
Peak memory 265256 kb
Host smart-4c78c596-9003-48b6-88f9-ad3dcf8c98bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666291111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2666291111
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2418696092
Short name T3
Test name
Test status
Simulation time 48635319747 ps
CPU time 1296.87 seconds
Started Jun 06 03:19:13 PM PDT 24
Finished Jun 06 03:40:52 PM PDT 24
Peak memory 289560 kb
Host smart-06ad61c2-4532-4af4-9bdc-2e7579fcad91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418696092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2418696092
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2166932967
Short name T230
Test name
Test status
Simulation time 559116109 ps
CPU time 27.41 seconds
Started Jun 06 03:19:01 PM PDT 24
Finished Jun 06 03:19:30 PM PDT 24
Peak memory 248764 kb
Host smart-dede97a7-0d8c-4a45-be2e-cc767e3c6ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21669
32967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2166932967
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3319301742
Short name T713
Test name
Test status
Simulation time 4287771789 ps
CPU time 70.4 seconds
Started Jun 06 03:19:02 PM PDT 24
Finished Jun 06 03:20:14 PM PDT 24
Peak memory 248884 kb
Host smart-3db744af-02bd-4f66-a3ca-0472ce2cde47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33193
01742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3319301742
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3589761199
Short name T440
Test name
Test status
Simulation time 12076339802 ps
CPU time 70.69 seconds
Started Jun 06 03:19:01 PM PDT 24
Finished Jun 06 03:20:13 PM PDT 24
Peak memory 248792 kb
Host smart-896c1352-88cb-4eae-962b-28ba0fff92c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35897
61199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3589761199
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.576185826
Short name T390
Test name
Test status
Simulation time 378746241 ps
CPU time 23.05 seconds
Started Jun 06 03:19:02 PM PDT 24
Finished Jun 06 03:19:27 PM PDT 24
Peak memory 248800 kb
Host smart-92a887b2-2c94-4289-b36f-04ba2bcb469f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57618
5826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.576185826
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2798029262
Short name T259
Test name
Test status
Simulation time 21410949943 ps
CPU time 1639.11 seconds
Started Jun 06 03:19:13 PM PDT 24
Finished Jun 06 03:46:34 PM PDT 24
Peak memory 270380 kb
Host smart-8c385f24-9ed9-4f16-b58a-a7562f72bca8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798029262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2798029262
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3989762684
Short name T204
Test name
Test status
Simulation time 56283637 ps
CPU time 2.51 seconds
Started Jun 06 03:19:29 PM PDT 24
Finished Jun 06 03:19:32 PM PDT 24
Peak memory 248896 kb
Host smart-b9bfd893-51d6-4c23-bb26-a6696df05d31
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3989762684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3989762684
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.2461536661
Short name T591
Test name
Test status
Simulation time 10349214326 ps
CPU time 1089.9 seconds
Started Jun 06 03:19:21 PM PDT 24
Finished Jun 06 03:37:33 PM PDT 24
Peak memory 283916 kb
Host smart-fb18a733-6198-4279-b947-37c77e937d86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461536661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2461536661
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1748972004
Short name T447
Test name
Test status
Simulation time 12666606758 ps
CPU time 61.44 seconds
Started Jun 06 03:19:27 PM PDT 24
Finished Jun 06 03:20:29 PM PDT 24
Peak memory 248792 kb
Host smart-2a2dbc9f-6efa-4b61-ae08-d727f252bb03
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1748972004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1748972004
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.3692370162
Short name T486
Test name
Test status
Simulation time 2538798984 ps
CPU time 152.77 seconds
Started Jun 06 03:19:12 PM PDT 24
Finished Jun 06 03:21:47 PM PDT 24
Peak memory 256888 kb
Host smart-41f05b0f-7a5b-4003-868a-af481e6a1729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36923
70162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.3692370162
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3512877043
Short name T455
Test name
Test status
Simulation time 4402392889 ps
CPU time 37.89 seconds
Started Jun 06 03:19:15 PM PDT 24
Finished Jun 06 03:19:54 PM PDT 24
Peak memory 248828 kb
Host smart-79017794-3c6f-479e-a56d-cb493c3cc0af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35128
77043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3512877043
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.2506319683
Short name T563
Test name
Test status
Simulation time 65494757854 ps
CPU time 876.46 seconds
Started Jun 06 03:19:28 PM PDT 24
Finished Jun 06 03:34:06 PM PDT 24
Peak memory 282284 kb
Host smart-7a75f394-58ea-426e-8276-3d8a3fceff7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506319683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2506319683
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1426530935
Short name T280
Test name
Test status
Simulation time 85642475685 ps
CPU time 378.02 seconds
Started Jun 06 03:19:13 PM PDT 24
Finished Jun 06 03:25:33 PM PDT 24
Peak memory 254708 kb
Host smart-8ee78e3d-4d4d-43a3-958e-fd5764446070
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426530935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1426530935
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.2462266998
Short name T512
Test name
Test status
Simulation time 903888450 ps
CPU time 34.32 seconds
Started Jun 06 03:19:16 PM PDT 24
Finished Jun 06 03:19:51 PM PDT 24
Peak memory 248784 kb
Host smart-83b9cb02-4234-4d24-beca-ebced9063f4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24622
66998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.2462266998
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.149914735
Short name T544
Test name
Test status
Simulation time 681712423 ps
CPU time 37.08 seconds
Started Jun 06 03:19:12 PM PDT 24
Finished Jun 06 03:19:51 PM PDT 24
Peak memory 256616 kb
Host smart-05a21f73-7a71-4730-9e23-310da5d9573f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14991
4735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.149914735
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1569010853
Short name T256
Test name
Test status
Simulation time 2745358131 ps
CPU time 40.75 seconds
Started Jun 06 03:19:18 PM PDT 24
Finished Jun 06 03:20:01 PM PDT 24
Peak memory 255596 kb
Host smart-2aec8c0d-a0b9-4b2c-a8fb-fa5ecf80b027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15690
10853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1569010853
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3445924077
Short name T694
Test name
Test status
Simulation time 1459670105 ps
CPU time 30.72 seconds
Started Jun 06 03:19:12 PM PDT 24
Finished Jun 06 03:19:44 PM PDT 24
Peak memory 248964 kb
Host smart-b958420c-b202-4b8e-a65a-ce150381146a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34459
24077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3445924077
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.2972920745
Short name T186
Test name
Test status
Simulation time 36228626929 ps
CPU time 4328.64 seconds
Started Jun 06 03:19:29 PM PDT 24
Finished Jun 06 04:31:39 PM PDT 24
Peak memory 338796 kb
Host smart-80b3ce87-5c2f-499b-aeef-afcaa8586538
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972920745 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.2972920745
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2483754522
Short name T212
Test name
Test status
Simulation time 182846982 ps
CPU time 2.87 seconds
Started Jun 06 03:19:40 PM PDT 24
Finished Jun 06 03:19:45 PM PDT 24
Peak memory 248872 kb
Host smart-35958ed8-8a46-4ee4-ba67-d7a6f0473e4a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2483754522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2483754522
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2282633768
Short name T550
Test name
Test status
Simulation time 261634070326 ps
CPU time 1995.28 seconds
Started Jun 06 03:19:26 PM PDT 24
Finished Jun 06 03:52:43 PM PDT 24
Peak memory 273404 kb
Host smart-7bd1b313-31e7-4a8f-abe9-2d10f21e62a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282633768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2282633768
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.2777122078
Short name T681
Test name
Test status
Simulation time 144569114 ps
CPU time 5.89 seconds
Started Jun 06 03:19:40 PM PDT 24
Finished Jun 06 03:19:48 PM PDT 24
Peak memory 248728 kb
Host smart-91791f0a-d441-4636-95db-daffcb7509a8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2777122078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2777122078
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.708763289
Short name T44
Test name
Test status
Simulation time 3182944532 ps
CPU time 116.28 seconds
Started Jun 06 03:19:28 PM PDT 24
Finished Jun 06 03:21:25 PM PDT 24
Peak memory 249852 kb
Host smart-295f42cf-1d8d-4959-9a4d-ddcfd0beda74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70876
3289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.708763289
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.1346448084
Short name T218
Test name
Test status
Simulation time 91518428 ps
CPU time 4.74 seconds
Started Jun 06 03:19:28 PM PDT 24
Finished Jun 06 03:19:34 PM PDT 24
Peak memory 239304 kb
Host smart-79718f87-122f-48a2-a334-dc9f61be7603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13464
48084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.1346448084
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1218496199
Short name T702
Test name
Test status
Simulation time 20739049080 ps
CPU time 1716.55 seconds
Started Jun 06 03:19:28 PM PDT 24
Finished Jun 06 03:48:06 PM PDT 24
Peak memory 289276 kb
Host smart-8152ef0c-ce86-4ce8-8f41-a0deecb53a2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218496199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1218496199
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3075964613
Short name T395
Test name
Test status
Simulation time 26336263098 ps
CPU time 1380.06 seconds
Started Jun 06 03:19:40 PM PDT 24
Finished Jun 06 03:42:43 PM PDT 24
Peak memory 268644 kb
Host smart-2c2a3ea5-134d-4cc9-8138-464825729335
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075964613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3075964613
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.212983574
Short name T381
Test name
Test status
Simulation time 2995270361 ps
CPU time 26.89 seconds
Started Jun 06 03:19:30 PM PDT 24
Finished Jun 06 03:19:57 PM PDT 24
Peak memory 248912 kb
Host smart-c03c99c5-e48f-4962-bd45-916b861a25f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21298
3574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.212983574
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.2815220028
Short name T577
Test name
Test status
Simulation time 3950009015 ps
CPU time 67.48 seconds
Started Jun 06 03:19:28 PM PDT 24
Finished Jun 06 03:20:37 PM PDT 24
Peak memory 255568 kb
Host smart-9de1a087-f179-4e57-8c51-f32688b20c6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28152
20028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2815220028
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.4166578192
Short name T529
Test name
Test status
Simulation time 134545985 ps
CPU time 16.11 seconds
Started Jun 06 03:19:29 PM PDT 24
Finished Jun 06 03:19:46 PM PDT 24
Peak memory 248752 kb
Host smart-b6ddc2ac-c2ee-49e4-994c-709f02f34a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41665
78192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.4166578192
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.1272931880
Short name T105
Test name
Test status
Simulation time 835675438 ps
CPU time 60.39 seconds
Started Jun 06 03:19:27 PM PDT 24
Finished Jun 06 03:20:28 PM PDT 24
Peak memory 248776 kb
Host smart-eafda069-f3a2-4629-8bcb-97be3e22ba4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12729
31880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.1272931880
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.1622909427
Short name T505
Test name
Test status
Simulation time 325031581098 ps
CPU time 2762.36 seconds
Started Jun 06 03:19:42 PM PDT 24
Finished Jun 06 04:05:46 PM PDT 24
Peak memory 289456 kb
Host smart-9cd3f138-b157-4684-a4ae-f2ee6de7df23
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622909427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.1622909427
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.2037070591
Short name T23
Test name
Test status
Simulation time 62883323924 ps
CPU time 1146.81 seconds
Started Jun 06 03:19:39 PM PDT 24
Finished Jun 06 03:38:48 PM PDT 24
Peak memory 289300 kb
Host smart-bcdd0fee-b0bf-4ce8-900f-326c5c0aba24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037070591 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.2037070591
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2004119703
Short name T104
Test name
Test status
Simulation time 94189582 ps
CPU time 2.86 seconds
Started Jun 06 03:19:48 PM PDT 24
Finished Jun 06 03:19:53 PM PDT 24
Peak memory 248940 kb
Host smart-9ee622ce-30cd-4bde-8d91-b9ed702300af
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2004119703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2004119703
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.552130140
Short name T700
Test name
Test status
Simulation time 65069430184 ps
CPU time 982.95 seconds
Started Jun 06 03:19:49 PM PDT 24
Finished Jun 06 03:36:14 PM PDT 24
Peak memory 268396 kb
Host smart-bc0afa6d-9272-4b96-9b0c-d1d9f86736a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552130140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.552130140
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.2428140199
Short name T64
Test name
Test status
Simulation time 718385270 ps
CPU time 28.91 seconds
Started Jun 06 03:19:50 PM PDT 24
Finished Jun 06 03:20:21 PM PDT 24
Peak memory 248760 kb
Host smart-45e5291a-d6cb-4b61-b092-3b985115ff7e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2428140199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2428140199
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.3788026309
Short name T596
Test name
Test status
Simulation time 5818460218 ps
CPU time 78.29 seconds
Started Jun 06 03:19:49 PM PDT 24
Finished Jun 06 03:21:09 PM PDT 24
Peak memory 248840 kb
Host smart-0729f7f9-c9a2-43a0-afb3-031355bab44b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37880
26309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.3788026309
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.1142047091
Short name T581
Test name
Test status
Simulation time 4592623813 ps
CPU time 40 seconds
Started Jun 06 03:19:48 PM PDT 24
Finished Jun 06 03:20:29 PM PDT 24
Peak memory 248828 kb
Host smart-5ac128b6-24c0-4641-8848-e5d8a6741a52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11420
47091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1142047091
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.1720847811
Short name T485
Test name
Test status
Simulation time 207825906722 ps
CPU time 2130.94 seconds
Started Jun 06 03:19:49 PM PDT 24
Finished Jun 06 03:55:22 PM PDT 24
Peak memory 282400 kb
Host smart-7cd65154-73ea-47e7-8fb1-39c647a6e71d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720847811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1720847811
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.3958462178
Short name T558
Test name
Test status
Simulation time 14255913955 ps
CPU time 1287.63 seconds
Started Jun 06 03:19:48 PM PDT 24
Finished Jun 06 03:41:17 PM PDT 24
Peak memory 281592 kb
Host smart-74040907-0253-466a-be40-c320140c7897
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958462178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3958462178
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3435311793
Short name T307
Test name
Test status
Simulation time 4543999462 ps
CPU time 206.84 seconds
Started Jun 06 03:19:49 PM PDT 24
Finished Jun 06 03:23:17 PM PDT 24
Peak memory 248100 kb
Host smart-47f84907-6100-40bf-97f9-279fb37f755b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435311793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3435311793
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2679317894
Short name T698
Test name
Test status
Simulation time 437755731 ps
CPU time 21.36 seconds
Started Jun 06 03:19:38 PM PDT 24
Finished Jun 06 03:20:01 PM PDT 24
Peak memory 256044 kb
Host smart-4c5a31c1-4079-4071-a7ad-eebc044d5ead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26793
17894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2679317894
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.4246632852
Short name T528
Test name
Test status
Simulation time 1542927817 ps
CPU time 22.96 seconds
Started Jun 06 03:19:48 PM PDT 24
Finished Jun 06 03:20:12 PM PDT 24
Peak memory 248848 kb
Host smart-12635520-d2e7-4f0f-9da1-6144d2baf70e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42466
32852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.4246632852
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.84676056
Short name T616
Test name
Test status
Simulation time 512324979 ps
CPU time 14.52 seconds
Started Jun 06 03:19:39 PM PDT 24
Finished Jun 06 03:19:56 PM PDT 24
Peak memory 248792 kb
Host smart-8a0c7862-7942-4f4b-8518-a4749b26b71b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84676
056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.84676056
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.1729921995
Short name T89
Test name
Test status
Simulation time 59648282040 ps
CPU time 2365.78 seconds
Started Jun 06 03:19:48 PM PDT 24
Finished Jun 06 03:59:15 PM PDT 24
Peak memory 289696 kb
Host smart-1fda89f4-da7f-495c-a886-40623a7fafd1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729921995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.1729921995
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1119903256
Short name T202
Test name
Test status
Simulation time 15983920 ps
CPU time 2.54 seconds
Started Jun 06 03:13:30 PM PDT 24
Finished Jun 06 03:13:33 PM PDT 24
Peak memory 248888 kb
Host smart-ecf7b193-1b6d-4026-880f-9bede20cb7d9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1119903256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1119903256
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2420201207
Short name T396
Test name
Test status
Simulation time 167091928902 ps
CPU time 2552.54 seconds
Started Jun 06 03:13:20 PM PDT 24
Finished Jun 06 03:55:53 PM PDT 24
Peak memory 287452 kb
Host smart-6861f176-a52f-4202-9baa-22fb8cd4b6c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420201207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2420201207
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3965772111
Short name T450
Test name
Test status
Simulation time 1153665877 ps
CPU time 16.47 seconds
Started Jun 06 03:13:27 PM PDT 24
Finished Jun 06 03:13:44 PM PDT 24
Peak memory 248796 kb
Host smart-6fd88fa5-9abc-43be-8a50-379a6b45e125
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3965772111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3965772111
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2040573352
Short name T282
Test name
Test status
Simulation time 4976065978 ps
CPU time 155.74 seconds
Started Jun 06 03:13:20 PM PDT 24
Finished Jun 06 03:15:57 PM PDT 24
Peak memory 257004 kb
Host smart-d2f84e98-eaa5-49ed-ae52-cabf7824d4da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20405
73352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2040573352
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.1331100733
Short name T630
Test name
Test status
Simulation time 779017137 ps
CPU time 46.73 seconds
Started Jun 06 03:13:18 PM PDT 24
Finished Jun 06 03:14:06 PM PDT 24
Peak memory 255992 kb
Host smart-78020f10-8d26-45ce-bad3-b1bef30d99b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13311
00733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1331100733
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1055422755
Short name T368
Test name
Test status
Simulation time 6819282049 ps
CPU time 727.47 seconds
Started Jun 06 03:13:28 PM PDT 24
Finished Jun 06 03:25:37 PM PDT 24
Peak memory 265248 kb
Host smart-bff13f7e-634d-4e76-a633-13e80494ed9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055422755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1055422755
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.4271034491
Short name T68
Test name
Test status
Simulation time 57844208026 ps
CPU time 3226.31 seconds
Started Jun 06 03:13:30 PM PDT 24
Finished Jun 06 04:07:17 PM PDT 24
Peak memory 289588 kb
Host smart-ae001d49-a028-4c0c-ac23-f5beca7a75f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271034491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.4271034491
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.4032826219
Short name T302
Test name
Test status
Simulation time 62829558538 ps
CPU time 343.81 seconds
Started Jun 06 03:13:26 PM PDT 24
Finished Jun 06 03:19:11 PM PDT 24
Peak memory 248276 kb
Host smart-b7fc43f7-63d0-451d-9367-7e5a0b10e31f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032826219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.4032826219
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.3897250444
Short name T351
Test name
Test status
Simulation time 645864187 ps
CPU time 33.33 seconds
Started Jun 06 03:13:18 PM PDT 24
Finished Jun 06 03:13:53 PM PDT 24
Peak memory 248792 kb
Host smart-3bfa30ad-9667-424b-ba7b-b17e491d987a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38972
50444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3897250444
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.204235893
Short name T373
Test name
Test status
Simulation time 964246869 ps
CPU time 51.37 seconds
Started Jun 06 03:13:17 PM PDT 24
Finished Jun 06 03:14:09 PM PDT 24
Peak memory 248844 kb
Host smart-cf32b737-afbb-4017-b6fd-3401b4a127ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20423
5893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.204235893
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2821567162
Short name T7
Test name
Test status
Simulation time 6341583556 ps
CPU time 26.07 seconds
Started Jun 06 03:13:39 PM PDT 24
Finished Jun 06 03:14:06 PM PDT 24
Peak memory 271784 kb
Host smart-85416660-e5d3-4751-aa80-2cf03bed84d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2821567162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2821567162
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.4265973721
Short name T545
Test name
Test status
Simulation time 571743036 ps
CPU time 21 seconds
Started Jun 06 03:13:17 PM PDT 24
Finished Jun 06 03:13:39 PM PDT 24
Peak memory 255696 kb
Host smart-828eb726-45a7-40fb-82d3-53417b47597e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42659
73721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.4265973721
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2362536457
Short name T699
Test name
Test status
Simulation time 3157307222 ps
CPU time 49.75 seconds
Started Jun 06 03:13:16 PM PDT 24
Finished Jun 06 03:14:07 PM PDT 24
Peak memory 248844 kb
Host smart-30f8356b-a18d-42c8-9225-5f7ba2e33630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23625
36457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2362536457
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.3791345207
Short name T665
Test name
Test status
Simulation time 23639124516 ps
CPU time 1496.95 seconds
Started Jun 06 03:20:01 PM PDT 24
Finished Jun 06 03:44:59 PM PDT 24
Peak memory 282108 kb
Host smart-5db60a10-125d-4fab-96a3-6b3b6e68a603
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791345207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3791345207
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.680179383
Short name T612
Test name
Test status
Simulation time 469981295 ps
CPU time 44.37 seconds
Started Jun 06 03:19:58 PM PDT 24
Finished Jun 06 03:20:43 PM PDT 24
Peak memory 257020 kb
Host smart-4902d587-360b-4c37-a7c9-9cf4b898e345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68017
9383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.680179383
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.635199504
Short name T83
Test name
Test status
Simulation time 3468412944 ps
CPU time 60.92 seconds
Started Jun 06 03:20:00 PM PDT 24
Finished Jun 06 03:21:02 PM PDT 24
Peak memory 248852 kb
Host smart-da0f26ae-f7cb-42b8-a40c-ac47d0ea4dca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63519
9504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.635199504
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.1004859470
Short name T403
Test name
Test status
Simulation time 41871349926 ps
CPU time 2166.17 seconds
Started Jun 06 03:19:59 PM PDT 24
Finished Jun 06 03:56:07 PM PDT 24
Peak memory 283716 kb
Host smart-c6610d02-3a96-48d6-b80e-b6a940bf4655
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004859470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.1004859470
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.267014224
Short name T507
Test name
Test status
Simulation time 40808559168 ps
CPU time 490.52 seconds
Started Jun 06 03:19:58 PM PDT 24
Finished Jun 06 03:28:10 PM PDT 24
Peak memory 247128 kb
Host smart-d1c7d708-9d25-4f4b-83f2-9b7ee9e8cff1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267014224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.267014224
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.3899386155
Short name T599
Test name
Test status
Simulation time 565860304 ps
CPU time 27.89 seconds
Started Jun 06 03:19:49 PM PDT 24
Finished Jun 06 03:20:19 PM PDT 24
Peak memory 248736 kb
Host smart-29ea1ae3-f560-4629-a947-16b22be9f3eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38993
86155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3899386155
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.204705532
Short name T426
Test name
Test status
Simulation time 172000926 ps
CPU time 16.83 seconds
Started Jun 06 03:19:50 PM PDT 24
Finished Jun 06 03:20:08 PM PDT 24
Peak memory 247332 kb
Host smart-1e154885-1f29-415b-bc50-2c7754bebb8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20470
5532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.204705532
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1380462825
Short name T676
Test name
Test status
Simulation time 786998466 ps
CPU time 33.83 seconds
Started Jun 06 03:20:00 PM PDT 24
Finished Jun 06 03:20:35 PM PDT 24
Peak memory 247688 kb
Host smart-9ebd3fc8-3a8c-4b8b-a3ed-d201f8ab62e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13804
62825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1380462825
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1366846810
Short name T520
Test name
Test status
Simulation time 81185499 ps
CPU time 6.75 seconds
Started Jun 06 03:19:49 PM PDT 24
Finished Jun 06 03:19:58 PM PDT 24
Peak memory 248720 kb
Host smart-eee4a6fc-1fc9-4afc-886a-4a59107e71fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13668
46810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1366846810
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.3057955879
Short name T634
Test name
Test status
Simulation time 60699171623 ps
CPU time 1461.93 seconds
Started Jun 06 03:20:04 PM PDT 24
Finished Jun 06 03:44:27 PM PDT 24
Peak memory 288432 kb
Host smart-eab23699-c56f-4f96-aae0-eefc736f7d24
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057955879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.3057955879
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.783230936
Short name T703
Test name
Test status
Simulation time 15834627352 ps
CPU time 1199.75 seconds
Started Jun 06 03:20:13 PM PDT 24
Finished Jun 06 03:40:14 PM PDT 24
Peak memory 281648 kb
Host smart-e697155a-5b5c-460e-bf05-4be5311d5bbe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783230936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.783230936
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2889300637
Short name T411
Test name
Test status
Simulation time 239255390 ps
CPU time 11.16 seconds
Started Jun 06 03:20:10 PM PDT 24
Finished Jun 06 03:20:23 PM PDT 24
Peak memory 248828 kb
Host smart-d2d2ddbf-8c3e-40c1-99aa-7729eca0887d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28893
00637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2889300637
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3638151514
Short name T354
Test name
Test status
Simulation time 1195870436 ps
CPU time 12.18 seconds
Started Jun 06 03:20:10 PM PDT 24
Finished Jun 06 03:20:24 PM PDT 24
Peak memory 256228 kb
Host smart-0f6ae1f2-0001-4bd1-b400-37b82cf6f9ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36381
51514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3638151514
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.349701910
Short name T95
Test name
Test status
Simulation time 33071502701 ps
CPU time 2138.14 seconds
Started Jun 06 03:20:13 PM PDT 24
Finished Jun 06 03:55:52 PM PDT 24
Peak memory 282196 kb
Host smart-d64b895e-e7fc-4799-8476-2bcaf2e718a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349701910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.349701910
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.591089030
Short name T473
Test name
Test status
Simulation time 31977716148 ps
CPU time 971.62 seconds
Started Jun 06 03:20:11 PM PDT 24
Finished Jun 06 03:36:24 PM PDT 24
Peak memory 281600 kb
Host smart-fe20ea4a-fc32-4ca1-9247-db0b65133ae3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591089030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.591089030
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.412763987
Short name T445
Test name
Test status
Simulation time 3830603465 ps
CPU time 164.22 seconds
Started Jun 06 03:20:10 PM PDT 24
Finished Jun 06 03:22:56 PM PDT 24
Peak memory 248020 kb
Host smart-de44a224-1a5a-40d0-9860-4c1e492eb93e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412763987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.412763987
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2673010600
Short name T444
Test name
Test status
Simulation time 733625064 ps
CPU time 13.79 seconds
Started Jun 06 03:20:11 PM PDT 24
Finished Jun 06 03:20:26 PM PDT 24
Peak memory 254432 kb
Host smart-be1a4e41-bb55-4b8f-91f8-c37f3bbfe33b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26730
10600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2673010600
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2656971465
Short name T289
Test name
Test status
Simulation time 95785274 ps
CPU time 5.48 seconds
Started Jun 06 03:20:09 PM PDT 24
Finished Jun 06 03:20:15 PM PDT 24
Peak memory 249960 kb
Host smart-2fcf5093-c84f-4496-b4c2-e810b9b32da0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26569
71465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2656971465
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.896153049
Short name T66
Test name
Test status
Simulation time 258809230 ps
CPU time 12.75 seconds
Started Jun 06 03:20:11 PM PDT 24
Finished Jun 06 03:20:25 PM PDT 24
Peak memory 247456 kb
Host smart-068ffc44-bc8d-4b2f-857e-80a245cf19a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89615
3049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.896153049
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2670984253
Short name T568
Test name
Test status
Simulation time 2184432281 ps
CPU time 72.84 seconds
Started Jun 06 03:20:10 PM PDT 24
Finished Jun 06 03:21:25 PM PDT 24
Peak memory 248860 kb
Host smart-392c39e7-58ab-4358-b7ff-651948e19db9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26709
84253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2670984253
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.4293524821
Short name T602
Test name
Test status
Simulation time 53110278864 ps
CPU time 3307.22 seconds
Started Jun 06 03:20:10 PM PDT 24
Finished Jun 06 04:15:18 PM PDT 24
Peak memory 289756 kb
Host smart-eb380f4f-73a3-47e0-9a8c-860e3cba9e7e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293524821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.4293524821
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.1311971934
Short name T627
Test name
Test status
Simulation time 62611530417 ps
CPU time 1591.89 seconds
Started Jun 06 03:20:22 PM PDT 24
Finished Jun 06 03:46:55 PM PDT 24
Peak memory 289424 kb
Host smart-12275ae1-be56-490d-844f-1a491b3cd11f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311971934 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.1311971934
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1289266634
Short name T279
Test name
Test status
Simulation time 53402336926 ps
CPU time 1706.47 seconds
Started Jun 06 03:20:31 PM PDT 24
Finished Jun 06 03:48:59 PM PDT 24
Peak memory 273436 kb
Host smart-52bef628-d533-4674-be2b-6cc30342da6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289266634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1289266634
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2385062393
Short name T604
Test name
Test status
Simulation time 195176584 ps
CPU time 16.99 seconds
Started Jun 06 03:20:20 PM PDT 24
Finished Jun 06 03:20:38 PM PDT 24
Peak memory 253660 kb
Host smart-16b79d77-e227-40a3-bc33-3c7bfe53c103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23850
62393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2385062393
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.770024677
Short name T436
Test name
Test status
Simulation time 1258639578 ps
CPU time 13.18 seconds
Started Jun 06 03:20:19 PM PDT 24
Finished Jun 06 03:20:34 PM PDT 24
Peak memory 255620 kb
Host smart-4fcb01a4-17d0-4751-8e94-45fbb04f5998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77002
4677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.770024677
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.596911225
Short name T315
Test name
Test status
Simulation time 43672074665 ps
CPU time 1442.75 seconds
Started Jun 06 03:20:31 PM PDT 24
Finished Jun 06 03:44:35 PM PDT 24
Peak memory 289072 kb
Host smart-fba27417-38cd-4ef7-a94d-2b9ed040a9b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596911225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.596911225
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1648373508
Short name T111
Test name
Test status
Simulation time 35024236747 ps
CPU time 1897.45 seconds
Started Jun 06 03:20:33 PM PDT 24
Finished Jun 06 03:52:12 PM PDT 24
Peak memory 289500 kb
Host smart-dcf90f20-ed36-4210-aa33-6c014774d5ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648373508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1648373508
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.3605778234
Short name T364
Test name
Test status
Simulation time 953293978 ps
CPU time 70.37 seconds
Started Jun 06 03:20:21 PM PDT 24
Finished Jun 06 03:21:32 PM PDT 24
Peak memory 248764 kb
Host smart-8c3e2205-f2db-4ee9-9813-7d32ef598238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36057
78234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3605778234
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.3879533509
Short name T687
Test name
Test status
Simulation time 78581392 ps
CPU time 7.48 seconds
Started Jun 06 03:20:30 PM PDT 24
Finished Jun 06 03:20:39 PM PDT 24
Peak memory 250936 kb
Host smart-6514b44b-ac38-4b9c-9855-27292ef839b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38795
33509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.3879533509
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.2809795791
Short name T500
Test name
Test status
Simulation time 1170270072 ps
CPU time 21.28 seconds
Started Jun 06 03:20:22 PM PDT 24
Finished Jun 06 03:20:45 PM PDT 24
Peak memory 257116 kb
Host smart-2693baa1-403e-47a4-b223-0528c73bdf46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28097
95791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.2809795791
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.4289036253
Short name T552
Test name
Test status
Simulation time 61990522 ps
CPU time 11 seconds
Started Jun 06 03:20:20 PM PDT 24
Finished Jun 06 03:20:32 PM PDT 24
Peak memory 248760 kb
Host smart-99e6be7e-aa19-4806-930c-a090637f0ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42890
36253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.4289036253
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.3201492444
Short name T262
Test name
Test status
Simulation time 56684727667 ps
CPU time 2804.55 seconds
Started Jun 06 03:20:32 PM PDT 24
Finished Jun 06 04:07:18 PM PDT 24
Peak memory 289744 kb
Host smart-7289a39e-68de-4cbc-95b1-207c379905de
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201492444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.3201492444
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.2537928814
Short name T62
Test name
Test status
Simulation time 52031570400 ps
CPU time 6247.1 seconds
Started Jun 06 03:20:31 PM PDT 24
Finished Jun 06 05:04:40 PM PDT 24
Peak memory 371400 kb
Host smart-42a58e23-8d36-4f64-b723-d68607edae73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537928814 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.2537928814
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2562793609
Short name T184
Test name
Test status
Simulation time 27769617652 ps
CPU time 1040.42 seconds
Started Jun 06 03:20:42 PM PDT 24
Finished Jun 06 03:38:04 PM PDT 24
Peak memory 288892 kb
Host smart-4e16b920-2e6f-4321-a600-2d5a04fa4433
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562793609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2562793609
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.96290049
Short name T185
Test name
Test status
Simulation time 140957974 ps
CPU time 15.14 seconds
Started Jun 06 03:20:32 PM PDT 24
Finished Jun 06 03:20:48 PM PDT 24
Peak memory 249116 kb
Host smart-5e4eeefa-de92-44c3-be71-38563329d6de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96290
049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.96290049
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.3419704386
Short name T407
Test name
Test status
Simulation time 1364336154 ps
CPU time 31.17 seconds
Started Jun 06 03:20:31 PM PDT 24
Finished Jun 06 03:21:04 PM PDT 24
Peak memory 248776 kb
Host smart-ce786ab1-8d98-4edb-8035-acb3d5cf0320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34197
04386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.3419704386
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.261870917
Short name T663
Test name
Test status
Simulation time 23716615633 ps
CPU time 1441.96 seconds
Started Jun 06 03:20:47 PM PDT 24
Finished Jun 06 03:44:50 PM PDT 24
Peak memory 273404 kb
Host smart-247bfe80-8d2c-4ceb-a0cb-02f3dc1f424c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261870917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.261870917
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.1630979350
Short name T484
Test name
Test status
Simulation time 4626629980 ps
CPU time 182.52 seconds
Started Jun 06 03:20:44 PM PDT 24
Finished Jun 06 03:23:48 PM PDT 24
Peak memory 248160 kb
Host smart-5866d293-c1f3-4b95-b8e7-95eb3f9a0c96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630979350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.1630979350
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.1060291628
Short name T374
Test name
Test status
Simulation time 3655855867 ps
CPU time 58.16 seconds
Started Jun 06 03:20:33 PM PDT 24
Finished Jun 06 03:21:33 PM PDT 24
Peak memory 248812 kb
Host smart-370b9136-bddb-423a-8f3e-7c36a76b78bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10602
91628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.1060291628
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.71996697
Short name T683
Test name
Test status
Simulation time 160222670 ps
CPU time 7.04 seconds
Started Jun 06 03:20:32 PM PDT 24
Finished Jun 06 03:20:40 PM PDT 24
Peak memory 252080 kb
Host smart-a2db10c8-f0f3-421e-ad7e-001e701d3e4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71996
697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.71996697
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.4049972563
Short name T265
Test name
Test status
Simulation time 1534825735 ps
CPU time 49.11 seconds
Started Jun 06 03:20:42 PM PDT 24
Finished Jun 06 03:21:33 PM PDT 24
Peak memory 248724 kb
Host smart-1ab3450b-aeac-4f31-9ed7-81d78cca39c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40499
72563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.4049972563
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.3149880064
Short name T392
Test name
Test status
Simulation time 644723124 ps
CPU time 15.43 seconds
Started Jun 06 03:20:31 PM PDT 24
Finished Jun 06 03:20:47 PM PDT 24
Peak memory 256908 kb
Host smart-20f950b5-4193-4b5f-b969-0c79ec9d0890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31498
80064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.3149880064
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1557118774
Short name T533
Test name
Test status
Simulation time 103779777069 ps
CPU time 3348.6 seconds
Started Jun 06 03:20:42 PM PDT 24
Finished Jun 06 04:16:32 PM PDT 24
Peak memory 289780 kb
Host smart-8581546d-f404-4b78-80eb-df04f03ff8bc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557118774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1557118774
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.672661634
Short name T110
Test name
Test status
Simulation time 163058955931 ps
CPU time 832.34 seconds
Started Jun 06 03:20:47 PM PDT 24
Finished Jun 06 03:34:40 PM PDT 24
Peak memory 273356 kb
Host smart-953b8da7-5ba7-4c3d-90dd-0169bc73bf97
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672661634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.672661634
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.887300791
Short name T419
Test name
Test status
Simulation time 6158399044 ps
CPU time 172.69 seconds
Started Jun 06 03:20:42 PM PDT 24
Finished Jun 06 03:23:35 PM PDT 24
Peak memory 256868 kb
Host smart-88925daa-b11f-4d31-bf94-cc4afa878702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88730
0791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.887300791
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.795725289
Short name T624
Test name
Test status
Simulation time 411951112 ps
CPU time 11.92 seconds
Started Jun 06 03:20:42 PM PDT 24
Finished Jun 06 03:20:54 PM PDT 24
Peak memory 254824 kb
Host smart-adf76bfb-9d75-468c-9347-81b2a5126762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79572
5289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.795725289
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1569164502
Short name T328
Test name
Test status
Simulation time 31241422165 ps
CPU time 1809.66 seconds
Started Jun 06 03:20:54 PM PDT 24
Finished Jun 06 03:51:05 PM PDT 24
Peak memory 273376 kb
Host smart-50bf5dcb-9e25-4dc0-bfeb-4fd13ef62dbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569164502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1569164502
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2486304338
Short name T295
Test name
Test status
Simulation time 17499478298 ps
CPU time 376.06 seconds
Started Jun 06 03:20:41 PM PDT 24
Finished Jun 06 03:26:58 PM PDT 24
Peak memory 248372 kb
Host smart-d437d462-b7b1-43a3-86d0-afb3c049a385
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486304338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2486304338
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.4067982003
Short name T215
Test name
Test status
Simulation time 259836321 ps
CPU time 24.75 seconds
Started Jun 06 03:20:48 PM PDT 24
Finished Jun 06 03:21:14 PM PDT 24
Peak memory 255892 kb
Host smart-ad2a9153-fb1c-4839-af22-301d66499200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40679
82003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.4067982003
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.3824549722
Short name T112
Test name
Test status
Simulation time 588332612 ps
CPU time 43.45 seconds
Started Jun 06 03:20:42 PM PDT 24
Finished Jun 06 03:21:27 PM PDT 24
Peak memory 248796 kb
Host smart-c6ff2fc9-45ed-4765-9dd0-468554f11914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38245
49722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.3824549722
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1553467962
Short name T589
Test name
Test status
Simulation time 704305811 ps
CPU time 17.92 seconds
Started Jun 06 03:20:43 PM PDT 24
Finished Jun 06 03:21:02 PM PDT 24
Peak memory 249008 kb
Host smart-3f1dc59d-a4dc-4e77-8cc4-27898a7a2cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15534
67962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1553467962
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.2790265013
Short name T470
Test name
Test status
Simulation time 899871597 ps
CPU time 43.49 seconds
Started Jun 06 03:20:45 PM PDT 24
Finished Jun 06 03:21:29 PM PDT 24
Peak memory 248724 kb
Host smart-03b66a44-b264-4762-95c9-085c5755dd4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27902
65013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2790265013
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.525548007
Short name T78
Test name
Test status
Simulation time 4616843807 ps
CPU time 83.31 seconds
Started Jun 06 03:20:54 PM PDT 24
Finished Jun 06 03:22:18 PM PDT 24
Peak memory 249836 kb
Host smart-4ffc5809-d851-4874-b5b6-c4acff5d277a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525548007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_han
dler_stress_all.525548007
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.4201037824
Short name T117
Test name
Test status
Simulation time 159667596559 ps
CPU time 5157.07 seconds
Started Jun 06 03:20:55 PM PDT 24
Finished Jun 06 04:46:54 PM PDT 24
Peak memory 322452 kb
Host smart-8c3ea78a-b21f-47b5-9181-683e14f499b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201037824 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.4201037824
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.2004464795
Short name T239
Test name
Test status
Simulation time 25992886265 ps
CPU time 1561.96 seconds
Started Jun 06 03:21:05 PM PDT 24
Finished Jun 06 03:47:08 PM PDT 24
Peak memory 273404 kb
Host smart-9e77be23-6a03-4e18-87d5-4c01c34be199
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004464795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.2004464795
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.2900034974
Short name T375
Test name
Test status
Simulation time 3528339395 ps
CPU time 64.53 seconds
Started Jun 06 03:21:05 PM PDT 24
Finished Jun 06 03:22:11 PM PDT 24
Peak memory 256836 kb
Host smart-b3ebf00e-1627-4cc9-88eb-8bd3b458ebcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29000
34974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.2900034974
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.3030869287
Short name T537
Test name
Test status
Simulation time 1131134894 ps
CPU time 62.85 seconds
Started Jun 06 03:20:53 PM PDT 24
Finished Jun 06 03:21:58 PM PDT 24
Peak memory 248768 kb
Host smart-c92f67e4-7ae9-4a3a-bec5-4778a2ba1ac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30308
69287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3030869287
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3415697592
Short name T231
Test name
Test status
Simulation time 492317911138 ps
CPU time 3027.76 seconds
Started Jun 06 03:21:05 PM PDT 24
Finished Jun 06 04:11:35 PM PDT 24
Peak memory 286028 kb
Host smart-8a88a086-4d97-48ff-98d0-2bf4f28a6e24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415697592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3415697592
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3549862814
Short name T389
Test name
Test status
Simulation time 74882578206 ps
CPU time 2326.96 seconds
Started Jun 06 03:21:04 PM PDT 24
Finished Jun 06 03:59:53 PM PDT 24
Peak memory 273408 kb
Host smart-95ced59b-e550-45f4-8f88-7a56fdaba918
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549862814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3549862814
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.862515614
Short name T677
Test name
Test status
Simulation time 6627227249 ps
CPU time 259.2 seconds
Started Jun 06 03:21:05 PM PDT 24
Finished Jun 06 03:25:26 PM PDT 24
Peak memory 248168 kb
Host smart-9beb3219-6580-4e48-a7d8-4f3500063580
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862515614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.862515614
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3378745871
Short name T515
Test name
Test status
Simulation time 276440559 ps
CPU time 19.75 seconds
Started Jun 06 03:20:53 PM PDT 24
Finished Jun 06 03:21:14 PM PDT 24
Peak memory 248832 kb
Host smart-62a0886a-1c9c-45d9-af04-13a5bf9783fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33787
45871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3378745871
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2758822205
Short name T345
Test name
Test status
Simulation time 19429045 ps
CPU time 3.11 seconds
Started Jun 06 03:20:51 PM PDT 24
Finished Jun 06 03:20:56 PM PDT 24
Peak memory 240560 kb
Host smart-a516ff43-a631-4638-87d3-2822c4275e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27588
22205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2758822205
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.4207307484
Short name T286
Test name
Test status
Simulation time 415846010 ps
CPU time 29.87 seconds
Started Jun 06 03:21:03 PM PDT 24
Finished Jun 06 03:21:35 PM PDT 24
Peak memory 255032 kb
Host smart-ace7cbb8-f497-41e3-9ec7-58afb964835d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42073
07484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.4207307484
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1425991112
Short name T524
Test name
Test status
Simulation time 989725002 ps
CPU time 24.62 seconds
Started Jun 06 03:20:53 PM PDT 24
Finished Jun 06 03:21:19 PM PDT 24
Peak memory 248708 kb
Host smart-c07e290e-b1e2-4ce3-93c1-f1525b4ae2d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14259
91112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1425991112
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.3224287560
Short name T252
Test name
Test status
Simulation time 33345214282 ps
CPU time 1624.24 seconds
Started Jun 06 03:21:05 PM PDT 24
Finished Jun 06 03:48:11 PM PDT 24
Peak memory 289344 kb
Host smart-ae277259-0e64-4d59-bee8-4a43a4fd438d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224287560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.3224287560
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.582418546
Short name T428
Test name
Test status
Simulation time 61619382144 ps
CPU time 1865.71 seconds
Started Jun 06 03:21:17 PM PDT 24
Finished Jun 06 03:52:24 PM PDT 24
Peak memory 273428 kb
Host smart-d6d5f4a3-1c6c-4767-8474-bb72113d4d57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582418546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.582418546
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2379278067
Short name T463
Test name
Test status
Simulation time 12205055055 ps
CPU time 114.29 seconds
Started Jun 06 03:21:05 PM PDT 24
Finished Jun 06 03:23:01 PM PDT 24
Peak memory 250152 kb
Host smart-7b5788ee-1896-42a6-8493-7a926e36587f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23792
78067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2379278067
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.122993020
Short name T527
Test name
Test status
Simulation time 933117677 ps
CPU time 57.17 seconds
Started Jun 06 03:21:19 PM PDT 24
Finished Jun 06 03:22:17 PM PDT 24
Peak memory 256036 kb
Host smart-36013da5-eb25-465d-987d-7a1ee5699ed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12299
3020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.122993020
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.2185771234
Short name T278
Test name
Test status
Simulation time 31721989471 ps
CPU time 1751.77 seconds
Started Jun 06 03:21:22 PM PDT 24
Finished Jun 06 03:50:34 PM PDT 24
Peak memory 273084 kb
Host smart-d066e3f1-e188-482a-b0c1-5ff41de38f82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185771234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.2185771234
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.88675314
Short name T240
Test name
Test status
Simulation time 20691563894 ps
CPU time 243.86 seconds
Started Jun 06 03:21:15 PM PDT 24
Finished Jun 06 03:25:20 PM PDT 24
Peak memory 247084 kb
Host smart-45d44f16-9f63-4067-a478-cb7688935e60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88675314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.88675314
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2650178688
Short name T287
Test name
Test status
Simulation time 212439863 ps
CPU time 29.13 seconds
Started Jun 06 03:21:05 PM PDT 24
Finished Jun 06 03:21:36 PM PDT 24
Peak memory 248764 kb
Host smart-edbe885e-74f7-425b-a503-5fb84fc3bb5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26501
78688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2650178688
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.3773894916
Short name T457
Test name
Test status
Simulation time 672581203 ps
CPU time 13.02 seconds
Started Jun 06 03:21:04 PM PDT 24
Finished Jun 06 03:21:19 PM PDT 24
Peak memory 248944 kb
Host smart-796a0384-85ea-4ef6-aa7f-8ebc7e00ac7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37738
94916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3773894916
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.2929751054
Short name T65
Test name
Test status
Simulation time 1343941336 ps
CPU time 9.45 seconds
Started Jun 06 03:21:04 PM PDT 24
Finished Jun 06 03:21:15 PM PDT 24
Peak memory 247480 kb
Host smart-0490eea3-b155-4933-99db-c29ee9c09045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29297
51054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2929751054
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2249256704
Short name T371
Test name
Test status
Simulation time 1633325074 ps
CPU time 22.41 seconds
Started Jun 06 03:21:04 PM PDT 24
Finished Jun 06 03:21:28 PM PDT 24
Peak memory 248740 kb
Host smart-3ec30ad9-0b0f-4a57-a239-24b12849a9dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22492
56704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2249256704
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.4095810674
Short name T590
Test name
Test status
Simulation time 184355726142 ps
CPU time 2614.64 seconds
Started Jun 06 03:21:17 PM PDT 24
Finished Jun 06 04:04:53 PM PDT 24
Peak memory 289308 kb
Host smart-82d5a122-691c-43cf-a349-21742b4aac2c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095810674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.4095810674
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.1273465148
Short name T453
Test name
Test status
Simulation time 3462239529 ps
CPU time 201.69 seconds
Started Jun 06 03:21:17 PM PDT 24
Finished Jun 06 03:24:40 PM PDT 24
Peak memory 256912 kb
Host smart-7e9e50fd-937e-4295-ba74-b40f7121f1a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12734
65148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1273465148
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2164669532
Short name T400
Test name
Test status
Simulation time 260809251 ps
CPU time 25.31 seconds
Started Jun 06 03:21:22 PM PDT 24
Finished Jun 06 03:21:49 PM PDT 24
Peak memory 248776 kb
Host smart-c75484bb-ed91-4a49-bf3f-d55ca531d361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21646
69532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2164669532
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.4089066392
Short name T237
Test name
Test status
Simulation time 14449421121 ps
CPU time 682.95 seconds
Started Jun 06 03:21:39 PM PDT 24
Finished Jun 06 03:33:03 PM PDT 24
Peak memory 265296 kb
Host smart-87ccbbd8-937d-4c4d-a963-147533558534
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089066392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.4089066392
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3938685269
Short name T376
Test name
Test status
Simulation time 13653863261 ps
CPU time 1345.55 seconds
Started Jun 06 03:21:17 PM PDT 24
Finished Jun 06 03:43:43 PM PDT 24
Peak memory 288652 kb
Host smart-4f3d4187-2d36-42ab-93f9-69c38ec2117f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938685269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3938685269
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3894588120
Short name T29
Test name
Test status
Simulation time 2401882124 ps
CPU time 33.41 seconds
Started Jun 06 03:21:15 PM PDT 24
Finished Jun 06 03:21:50 PM PDT 24
Peak memory 256344 kb
Host smart-b806ef7b-8b75-4e44-b49a-4c58d9d06b55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38945
88120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3894588120
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.1553818289
Short name T434
Test name
Test status
Simulation time 25661492 ps
CPU time 3.66 seconds
Started Jun 06 03:21:14 PM PDT 24
Finished Jun 06 03:21:19 PM PDT 24
Peak memory 239200 kb
Host smart-54f832fb-74f5-4eb9-a8a5-6b95db0c9faf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15538
18289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1553818289
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1233038752
Short name T360
Test name
Test status
Simulation time 649965512 ps
CPU time 49.28 seconds
Started Jun 06 03:21:21 PM PDT 24
Finished Jun 06 03:22:11 PM PDT 24
Peak memory 247624 kb
Host smart-b3ff6cf2-e9d9-4a80-ac28-7d07d4698353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12330
38752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1233038752
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.211437171
Short name T84
Test name
Test status
Simulation time 983771402 ps
CPU time 13.74 seconds
Started Jun 06 03:21:15 PM PDT 24
Finished Jun 06 03:21:29 PM PDT 24
Peak memory 254136 kb
Host smart-0d363b93-f4cc-495e-9585-c0bd43b6386a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21143
7171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.211437171
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.977860141
Short name T258
Test name
Test status
Simulation time 52361600204 ps
CPU time 3167.69 seconds
Started Jun 06 03:21:15 PM PDT 24
Finished Jun 06 04:14:04 PM PDT 24
Peak memory 301776 kb
Host smart-55535164-b733-43a6-a8b3-80e4014909f7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977860141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_han
dler_stress_all.977860141
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3833326574
Short name T666
Test name
Test status
Simulation time 141431851453 ps
CPU time 2535.57 seconds
Started Jun 06 03:21:24 PM PDT 24
Finished Jun 06 04:03:41 PM PDT 24
Peak memory 288972 kb
Host smart-ee9937d6-d24b-4bbb-8086-48bac493485b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833326574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3833326574
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1203207975
Short name T372
Test name
Test status
Simulation time 5196690792 ps
CPU time 91.35 seconds
Started Jun 06 03:21:26 PM PDT 24
Finished Jun 06 03:22:58 PM PDT 24
Peak memory 249964 kb
Host smart-97bcc7f3-02aa-40da-a5d0-627611d13829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12032
07975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1203207975
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.1589273711
Short name T437
Test name
Test status
Simulation time 227747430 ps
CPU time 10.13 seconds
Started Jun 06 03:21:25 PM PDT 24
Finished Jun 06 03:21:37 PM PDT 24
Peak memory 254988 kb
Host smart-36e6c011-0ae0-4f4f-98f7-73ba522e9d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15892
73711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1589273711
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.381309161
Short name T48
Test name
Test status
Simulation time 166160305801 ps
CPU time 1474.15 seconds
Started Jun 06 03:21:36 PM PDT 24
Finished Jun 06 03:46:11 PM PDT 24
Peak memory 270884 kb
Host smart-5037f7cb-6781-4b74-8266-1e1de2c6c302
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381309161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.381309161
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.273732493
Short name T502
Test name
Test status
Simulation time 105657819380 ps
CPU time 1668.02 seconds
Started Jun 06 03:21:37 PM PDT 24
Finished Jun 06 03:49:26 PM PDT 24
Peak memory 272672 kb
Host smart-9cf41981-910d-4a92-93d7-0762c8ad12c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273732493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.273732493
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.257745922
Short name T291
Test name
Test status
Simulation time 14181597129 ps
CPU time 417.64 seconds
Started Jun 06 03:21:37 PM PDT 24
Finished Jun 06 03:28:36 PM PDT 24
Peak memory 247176 kb
Host smart-be31d7e1-0582-4c62-a9f4-790fa35ba77b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257745922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.257745922
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.3684382255
Short name T385
Test name
Test status
Simulation time 2202867038 ps
CPU time 55.86 seconds
Started Jun 06 03:21:27 PM PDT 24
Finished Jun 06 03:22:24 PM PDT 24
Peak memory 248764 kb
Host smart-ac035ab4-e326-4a43-a4d2-116bd1f53689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36843
82255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.3684382255
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.371335328
Short name T631
Test name
Test status
Simulation time 414469246 ps
CPU time 27.71 seconds
Started Jun 06 03:21:27 PM PDT 24
Finished Jun 06 03:21:55 PM PDT 24
Peak memory 255964 kb
Host smart-2f05601e-582a-4060-a71a-f07a83d8bc1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37133
5328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.371335328
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.2273647022
Short name T472
Test name
Test status
Simulation time 133138996 ps
CPU time 5.26 seconds
Started Jun 06 03:21:26 PM PDT 24
Finished Jun 06 03:21:33 PM PDT 24
Peak memory 248764 kb
Host smart-ccf49e7e-e96a-4569-b028-b7ea41d07667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22736
47022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2273647022
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1634050856
Short name T594
Test name
Test status
Simulation time 215044838 ps
CPU time 9.86 seconds
Started Jun 06 03:21:26 PM PDT 24
Finished Jun 06 03:21:37 PM PDT 24
Peak memory 248760 kb
Host smart-e3268da8-3a37-4a65-a1e9-bba783e7ffa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16340
50856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1634050856
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.1127839102
Short name T214
Test name
Test status
Simulation time 3981499974 ps
CPU time 34.39 seconds
Started Jun 06 03:21:37 PM PDT 24
Finished Jun 06 03:22:13 PM PDT 24
Peak memory 256444 kb
Host smart-edc8dfcd-f864-43ca-8729-ec176ff429f4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127839102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.1127839102
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.3841560660
Short name T115
Test name
Test status
Simulation time 58470700154 ps
CPU time 4021.02 seconds
Started Jun 06 03:21:37 PM PDT 24
Finished Jun 06 04:28:40 PM PDT 24
Peak memory 305944 kb
Host smart-a2d6f06e-1938-4138-aab3-7db86d2b6c8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841560660 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.3841560660
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3773106274
Short name T90
Test name
Test status
Simulation time 25047976229 ps
CPU time 1798.84 seconds
Started Jun 06 03:21:52 PM PDT 24
Finished Jun 06 03:51:53 PM PDT 24
Peak memory 273468 kb
Host smart-724e768e-0e2a-4754-91c1-217bcd2ae88c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773106274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3773106274
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.3793078694
Short name T365
Test name
Test status
Simulation time 3534712173 ps
CPU time 154.78 seconds
Started Jun 06 03:21:51 PM PDT 24
Finished Jun 06 03:24:28 PM PDT 24
Peak memory 256948 kb
Host smart-41b3aeab-27bb-41ba-a148-e955d2a00149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37930
78694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3793078694
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3380121051
Short name T476
Test name
Test status
Simulation time 157449014 ps
CPU time 18.81 seconds
Started Jun 06 03:21:52 PM PDT 24
Finished Jun 06 03:22:13 PM PDT 24
Peak memory 255056 kb
Host smart-7c45eb0a-5350-42ff-921a-faf282e8f9ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33801
21051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3380121051
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1172325738
Short name T712
Test name
Test status
Simulation time 26385106513 ps
CPU time 1632.13 seconds
Started Jun 06 03:22:04 PM PDT 24
Finished Jun 06 03:49:17 PM PDT 24
Peak memory 282580 kb
Host smart-728d2d55-950b-4a8c-8c1a-b287cf8c3aa7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172325738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1172325738
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.2758779530
Short name T300
Test name
Test status
Simulation time 7417344586 ps
CPU time 303.52 seconds
Started Jun 06 03:21:52 PM PDT 24
Finished Jun 06 03:26:58 PM PDT 24
Peak memory 254628 kb
Host smart-c2c9fce7-0d9a-482a-8cef-8f7e860327c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758779530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.2758779530
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1764482864
Short name T379
Test name
Test status
Simulation time 1877356628 ps
CPU time 63.69 seconds
Started Jun 06 03:21:37 PM PDT 24
Finished Jun 06 03:22:42 PM PDT 24
Peak memory 256148 kb
Host smart-73b8060d-04b9-4065-a615-36e6d6565001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17644
82864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1764482864
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2618609250
Short name T606
Test name
Test status
Simulation time 1153209991 ps
CPU time 60.96 seconds
Started Jun 06 03:21:36 PM PDT 24
Finished Jun 06 03:22:38 PM PDT 24
Peak memory 248716 kb
Host smart-52e99f95-eac9-4b29-9a53-cf4eea2c7b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26186
09250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2618609250
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1195865950
Short name T92
Test name
Test status
Simulation time 426278396 ps
CPU time 41.3 seconds
Started Jun 06 03:21:51 PM PDT 24
Finished Jun 06 03:22:34 PM PDT 24
Peak memory 248844 kb
Host smart-29bdf553-98bd-4aae-88c5-ec3f62354447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11958
65950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1195865950
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.3963975452
Short name T424
Test name
Test status
Simulation time 3393872567 ps
CPU time 50.38 seconds
Started Jun 06 03:21:37 PM PDT 24
Finished Jun 06 03:22:29 PM PDT 24
Peak memory 248840 kb
Host smart-fc5006f7-efec-410a-9563-8bb447b09723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39639
75452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.3963975452
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.1995423744
Short name T272
Test name
Test status
Simulation time 466592957632 ps
CPU time 2624.92 seconds
Started Jun 06 03:22:03 PM PDT 24
Finished Jun 06 04:05:49 PM PDT 24
Peak memory 289816 kb
Host smart-03d61be8-2720-495d-beb4-5c09eeb29d70
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995423744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.1995423744
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.2316134124
Short name T213
Test name
Test status
Simulation time 35905027 ps
CPU time 3.38 seconds
Started Jun 06 03:13:56 PM PDT 24
Finished Jun 06 03:14:00 PM PDT 24
Peak memory 248952 kb
Host smart-da4f0e40-4025-4381-934a-b2983a297d18
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2316134124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2316134124
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.173632652
Short name T477
Test name
Test status
Simulation time 45173219976 ps
CPU time 2705.41 seconds
Started Jun 06 03:13:47 PM PDT 24
Finished Jun 06 03:58:53 PM PDT 24
Peak memory 288804 kb
Host smart-81b01019-6ad5-4881-be14-cf713cdaed3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173632652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.173632652
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2181933406
Short name T611
Test name
Test status
Simulation time 323166438 ps
CPU time 9.7 seconds
Started Jun 06 03:13:57 PM PDT 24
Finished Jun 06 03:14:08 PM PDT 24
Peak memory 248796 kb
Host smart-a4e1ec87-b38e-4d8e-8a31-291ca5a88184
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2181933406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2181933406
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.1286165441
Short name T526
Test name
Test status
Simulation time 1565737978 ps
CPU time 69.85 seconds
Started Jun 06 03:13:38 PM PDT 24
Finished Jun 06 03:14:49 PM PDT 24
Peak memory 256948 kb
Host smart-b3f1410e-f1e7-4df7-9329-173de07e9158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12861
65441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1286165441
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2462805489
Short name T429
Test name
Test status
Simulation time 1227427833 ps
CPU time 75.91 seconds
Started Jun 06 03:13:38 PM PDT 24
Finished Jun 06 03:14:55 PM PDT 24
Peak memory 256132 kb
Host smart-10bc3913-e12c-44cd-88fe-5b4dc0f92b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24628
05489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2462805489
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2344288736
Short name T644
Test name
Test status
Simulation time 41444712917 ps
CPU time 971.18 seconds
Started Jun 06 03:13:50 PM PDT 24
Finished Jun 06 03:30:02 PM PDT 24
Peak memory 271572 kb
Host smart-30c822eb-9a1a-4506-ad25-da17bf4e801f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344288736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2344288736
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.585542389
Short name T610
Test name
Test status
Simulation time 27916363809 ps
CPU time 1758.82 seconds
Started Jun 06 03:13:48 PM PDT 24
Finished Jun 06 03:43:08 PM PDT 24
Peak memory 273056 kb
Host smart-dba8efac-76e9-427a-bb77-3ea886ad02b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585542389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.585542389
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.1695441999
Short name T293
Test name
Test status
Simulation time 11058103467 ps
CPU time 424.29 seconds
Started Jun 06 03:13:46 PM PDT 24
Finished Jun 06 03:20:52 PM PDT 24
Peak memory 248220 kb
Host smart-cf587106-ce9a-42f2-8c89-74f42332a73d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695441999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1695441999
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.3097460442
Short name T541
Test name
Test status
Simulation time 865563615 ps
CPU time 53 seconds
Started Jun 06 03:13:39 PM PDT 24
Finished Jun 06 03:14:33 PM PDT 24
Peak memory 248832 kb
Host smart-9ed3b131-7357-460c-850d-c873449604c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30974
60442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.3097460442
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1520002061
Short name T519
Test name
Test status
Simulation time 736978366 ps
CPU time 43.26 seconds
Started Jun 06 03:13:38 PM PDT 24
Finished Jun 06 03:14:23 PM PDT 24
Peak memory 255608 kb
Host smart-634d8429-d8d1-46cc-b3d4-441f4daf3469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15200
02061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1520002061
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1589706402
Short name T49
Test name
Test status
Simulation time 870905511 ps
CPU time 28.96 seconds
Started Jun 06 03:13:50 PM PDT 24
Finished Jun 06 03:14:20 PM PDT 24
Peak memory 248772 kb
Host smart-b1539310-8ea6-470f-a19b-696a576a68a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15897
06402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1589706402
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3068993987
Short name T461
Test name
Test status
Simulation time 436126167 ps
CPU time 31.41 seconds
Started Jun 06 03:13:38 PM PDT 24
Finished Jun 06 03:14:10 PM PDT 24
Peak memory 249028 kb
Host smart-1a061f89-bef1-422a-94e9-77f21d1851b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30689
93987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3068993987
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.461167437
Short name T421
Test name
Test status
Simulation time 738275567926 ps
CPU time 6513.38 seconds
Started Jun 06 03:13:58 PM PDT 24
Finished Jun 06 05:02:33 PM PDT 24
Peak memory 321776 kb
Host smart-5770df5a-175b-46eb-9086-a120c557a63d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461167437 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.461167437
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.388685050
Short name T58
Test name
Test status
Simulation time 75292414135 ps
CPU time 2538.3 seconds
Started Jun 06 03:22:02 PM PDT 24
Finished Jun 06 04:04:22 PM PDT 24
Peak memory 289424 kb
Host smart-bf070c14-1ac8-4463-9ddb-2eca1d713cb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388685050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.388685050
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.3867505707
Short name T481
Test name
Test status
Simulation time 8232397423 ps
CPU time 141.88 seconds
Started Jun 06 03:22:01 PM PDT 24
Finished Jun 06 03:24:24 PM PDT 24
Peak memory 256960 kb
Host smart-b6ba5df2-bf71-472b-b823-5d3a06153e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38675
05707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3867505707
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.446584309
Short name T619
Test name
Test status
Simulation time 1782548767 ps
CPU time 61.07 seconds
Started Jun 06 03:22:02 PM PDT 24
Finished Jun 06 03:23:05 PM PDT 24
Peak memory 256184 kb
Host smart-bd4fb5f0-0cd3-45fc-9d0c-c18491ac7d7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44658
4309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.446584309
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.2789070508
Short name T324
Test name
Test status
Simulation time 270248641984 ps
CPU time 1485.03 seconds
Started Jun 06 03:22:03 PM PDT 24
Finished Jun 06 03:46:50 PM PDT 24
Peak memory 288040 kb
Host smart-4296bfe5-bc74-478b-96a6-45a87e4b5bc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789070508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2789070508
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.649346274
Short name T352
Test name
Test status
Simulation time 60831527580 ps
CPU time 2396.32 seconds
Started Jun 06 03:22:02 PM PDT 24
Finished Jun 06 04:02:00 PM PDT 24
Peak memory 289152 kb
Host smart-3f81e1ab-ea2a-44ca-9ed7-5103b2108251
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649346274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.649346274
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2487185494
Short name T232
Test name
Test status
Simulation time 13640806563 ps
CPU time 526.93 seconds
Started Jun 06 03:21:58 PM PDT 24
Finished Jun 06 03:30:46 PM PDT 24
Peak memory 248084 kb
Host smart-348b07b8-68b6-47a5-aa77-46d76c00492e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487185494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2487185494
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3586728071
Short name T510
Test name
Test status
Simulation time 1239494978 ps
CPU time 20.28 seconds
Started Jun 06 03:22:04 PM PDT 24
Finished Jun 06 03:22:25 PM PDT 24
Peak memory 256000 kb
Host smart-8c6b439d-ba9c-4840-8723-4d45feb2c5c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35867
28071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3586728071
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.3426657165
Short name T384
Test name
Test status
Simulation time 3375051914 ps
CPU time 38.71 seconds
Started Jun 06 03:22:03 PM PDT 24
Finished Jun 06 03:22:43 PM PDT 24
Peak memory 256788 kb
Host smart-2dd6ce44-bd22-4049-a8b1-6cbb29abe2ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34266
57165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3426657165
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.2827400571
Short name T448
Test name
Test status
Simulation time 608337101 ps
CPU time 36.79 seconds
Started Jun 06 03:22:02 PM PDT 24
Finished Jun 06 03:22:40 PM PDT 24
Peak memory 255424 kb
Host smart-06593cce-4fc5-4e58-839e-f64d8163681a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28274
00571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.2827400571
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.4010382238
Short name T567
Test name
Test status
Simulation time 1102071397 ps
CPU time 61.39 seconds
Started Jun 06 03:22:02 PM PDT 24
Finished Jun 06 03:23:04 PM PDT 24
Peak memory 248728 kb
Host smart-0fd5407d-1a59-4f29-b17a-054278c808fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40103
82238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.4010382238
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.914044116
Short name T98
Test name
Test status
Simulation time 30257348102 ps
CPU time 1589.63 seconds
Started Jun 06 03:22:02 PM PDT 24
Finished Jun 06 03:48:32 PM PDT 24
Peak memory 273088 kb
Host smart-e5a62560-1b70-432b-a3ea-1730fe01a64a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914044116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_han
dler_stress_all.914044116
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.1082892294
Short name T394
Test name
Test status
Simulation time 250455482452 ps
CPU time 2678.33 seconds
Started Jun 06 03:22:03 PM PDT 24
Finished Jun 06 04:06:43 PM PDT 24
Peak memory 313948 kb
Host smart-2a02ec6f-feec-4ef4-ac30-b1c496f7ff54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082892294 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.1082892294
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.4010873499
Short name T474
Test name
Test status
Simulation time 11194408689 ps
CPU time 1099.71 seconds
Started Jun 06 03:22:13 PM PDT 24
Finished Jun 06 03:40:34 PM PDT 24
Peak memory 272436 kb
Host smart-5f737bb8-6f68-44f9-b189-fd7bb33b8f84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010873499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.4010873499
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.1731567422
Short name T446
Test name
Test status
Simulation time 606508998 ps
CPU time 52 seconds
Started Jun 06 03:22:13 PM PDT 24
Finished Jun 06 03:23:06 PM PDT 24
Peak memory 256764 kb
Host smart-798b4d0b-c0f5-4d11-88c9-3776cbdd06d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17315
67422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.1731567422
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1074757312
Short name T479
Test name
Test status
Simulation time 447157658 ps
CPU time 9.24 seconds
Started Jun 06 03:22:13 PM PDT 24
Finished Jun 06 03:22:23 PM PDT 24
Peak memory 248776 kb
Host smart-f5b8a4da-5276-4f31-abe0-1f104bdfafec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10747
57312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1074757312
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2581811168
Short name T109
Test name
Test status
Simulation time 31478727384 ps
CPU time 2048.12 seconds
Started Jun 06 03:22:14 PM PDT 24
Finished Jun 06 03:56:24 PM PDT 24
Peak memory 288472 kb
Host smart-bad407d0-533f-48bc-b714-4d6a5749e887
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581811168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2581811168
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.207914518
Short name T308
Test name
Test status
Simulation time 15056872839 ps
CPU time 175.39 seconds
Started Jun 06 03:22:12 PM PDT 24
Finished Jun 06 03:25:09 PM PDT 24
Peak memory 247932 kb
Host smart-3e95e36e-9b04-446b-b327-50a1440c1475
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207914518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.207914518
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2717669187
Short name T70
Test name
Test status
Simulation time 3471362838 ps
CPU time 31.92 seconds
Started Jun 06 03:22:02 PM PDT 24
Finished Jun 06 03:22:36 PM PDT 24
Peak memory 248884 kb
Host smart-b68e24e4-0693-4400-9896-afe9bf30ed23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27176
69187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2717669187
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.925628296
Short name T539
Test name
Test status
Simulation time 232668766 ps
CPU time 13.54 seconds
Started Jun 06 03:22:12 PM PDT 24
Finished Jun 06 03:22:27 PM PDT 24
Peak memory 254676 kb
Host smart-fb4ae567-9d9f-41c3-9dfe-70791edd2212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92562
8296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.925628296
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.679437044
Short name T97
Test name
Test status
Simulation time 1084931822 ps
CPU time 25.11 seconds
Started Jun 06 03:22:12 PM PDT 24
Finished Jun 06 03:22:38 PM PDT 24
Peak memory 256796 kb
Host smart-c0608562-e5ee-41d7-8d5a-11e50ffeeb23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67943
7044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.679437044
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1947767169
Short name T641
Test name
Test status
Simulation time 3664666007 ps
CPU time 55.95 seconds
Started Jun 06 03:22:03 PM PDT 24
Finished Jun 06 03:23:00 PM PDT 24
Peak memory 248820 kb
Host smart-c17173a7-da57-45b7-b005-7ac6aa46cf40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19477
67169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1947767169
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.3552894002
Short name T408
Test name
Test status
Simulation time 2268276650 ps
CPU time 127.64 seconds
Started Jun 06 03:22:16 PM PDT 24
Finished Jun 06 03:24:25 PM PDT 24
Peak memory 256172 kb
Host smart-be26ab71-e25f-48af-ac6d-251489d18a40
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552894002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.3552894002
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.3204945887
Short name T82
Test name
Test status
Simulation time 88798116692 ps
CPU time 3446.68 seconds
Started Jun 06 03:22:27 PM PDT 24
Finished Jun 06 04:19:55 PM PDT 24
Peak memory 306056 kb
Host smart-8be56a37-2876-4e86-88e1-2f540e23fd98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204945887 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.3204945887
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.211356355
Short name T361
Test name
Test status
Simulation time 17032970448 ps
CPU time 1321.66 seconds
Started Jun 06 03:22:26 PM PDT 24
Finished Jun 06 03:44:29 PM PDT 24
Peak memory 284112 kb
Host smart-8e83bd81-7c4a-45c6-a58c-db8e348130a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211356355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.211356355
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1878848797
Short name T356
Test name
Test status
Simulation time 7331666951 ps
CPU time 146.62 seconds
Started Jun 06 03:22:25 PM PDT 24
Finished Jun 06 03:24:53 PM PDT 24
Peak memory 257004 kb
Host smart-b8e361bc-6651-4b18-92f3-5715230eb35c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18788
48797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1878848797
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1554187581
Short name T270
Test name
Test status
Simulation time 304430982 ps
CPU time 21.18 seconds
Started Jun 06 03:22:25 PM PDT 24
Finished Jun 06 03:22:48 PM PDT 24
Peak memory 248844 kb
Host smart-098cfc75-084e-4c7f-8875-0159a6b69cfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15541
87581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1554187581
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.2074257298
Short name T313
Test name
Test status
Simulation time 46044617774 ps
CPU time 2839.65 seconds
Started Jun 06 03:22:24 PM PDT 24
Finished Jun 06 04:09:45 PM PDT 24
Peak memory 280948 kb
Host smart-10f0adcc-d009-4c52-917b-6b76598c191f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074257298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.2074257298
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.4040332919
Short name T536
Test name
Test status
Simulation time 21991969611 ps
CPU time 1147.5 seconds
Started Jun 06 03:22:35 PM PDT 24
Finished Jun 06 03:41:44 PM PDT 24
Peak memory 286896 kb
Host smart-072fa0dd-e5c0-423c-91ac-77e69408d3a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040332919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.4040332919
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.2163606735
Short name T645
Test name
Test status
Simulation time 160804820 ps
CPU time 23.11 seconds
Started Jun 06 03:22:24 PM PDT 24
Finished Jun 06 03:22:48 PM PDT 24
Peak memory 255968 kb
Host smart-f81af37c-d148-43d2-b12f-3fffac460466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21636
06735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2163606735
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.222834022
Short name T637
Test name
Test status
Simulation time 695999559 ps
CPU time 44.64 seconds
Started Jun 06 03:22:25 PM PDT 24
Finished Jun 06 03:23:10 PM PDT 24
Peak memory 248724 kb
Host smart-85ab5713-9bed-4fbf-a29e-d1ebbec54f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22283
4022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.222834022
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.636215702
Short name T588
Test name
Test status
Simulation time 371281758 ps
CPU time 23.24 seconds
Started Jun 06 03:22:29 PM PDT 24
Finished Jun 06 03:22:53 PM PDT 24
Peak memory 248784 kb
Host smart-14623d54-0e22-4d82-9252-3856eb91a78f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63621
5702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.636215702
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2390966257
Short name T343
Test name
Test status
Simulation time 532549295 ps
CPU time 16.16 seconds
Started Jun 06 03:22:29 PM PDT 24
Finished Jun 06 03:22:46 PM PDT 24
Peak memory 248780 kb
Host smart-70492b40-913c-4c4f-a8c7-7ae5ae920a00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23909
66257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2390966257
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.3914748366
Short name T632
Test name
Test status
Simulation time 31659579757 ps
CPU time 856 seconds
Started Jun 06 03:22:37 PM PDT 24
Finished Jun 06 03:36:56 PM PDT 24
Peak memory 283164 kb
Host smart-996b3a87-5f6f-4651-a3c5-dd72ab7955ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914748366 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.3914748366
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2474990210
Short name T47
Test name
Test status
Simulation time 163835050982 ps
CPU time 2537.95 seconds
Started Jun 06 03:22:48 PM PDT 24
Finished Jun 06 04:05:07 PM PDT 24
Peak memory 289392 kb
Host smart-e7f61fc5-b38c-49fb-adc9-a5a5514854ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474990210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2474990210
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.4242343408
Short name T692
Test name
Test status
Simulation time 3816823258 ps
CPU time 226.43 seconds
Started Jun 06 03:22:36 PM PDT 24
Finished Jun 06 03:26:24 PM PDT 24
Peak memory 257212 kb
Host smart-4bc5792b-9056-430b-a426-8cf9f8aa4661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42423
43408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.4242343408
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2610024160
Short name T570
Test name
Test status
Simulation time 8897876381 ps
CPU time 51.12 seconds
Started Jun 06 03:22:36 PM PDT 24
Finished Jun 06 03:23:29 PM PDT 24
Peak memory 248832 kb
Host smart-f0232e7f-eed9-45ed-8df3-d747c3dea713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26100
24160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2610024160
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3296104791
Short name T317
Test name
Test status
Simulation time 33635364718 ps
CPU time 645.68 seconds
Started Jun 06 03:22:46 PM PDT 24
Finished Jun 06 03:33:33 PM PDT 24
Peak memory 272912 kb
Host smart-7513d0f9-cd74-4e10-ad13-95412354a34c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296104791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3296104791
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.2857698747
Short name T660
Test name
Test status
Simulation time 63647347 ps
CPU time 5.52 seconds
Started Jun 06 03:22:38 PM PDT 24
Finished Jun 06 03:22:46 PM PDT 24
Peak memory 240552 kb
Host smart-fd8235c4-d501-489c-a7fa-8be2c5edacfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28576
98747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2857698747
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.1306196251
Short name T542
Test name
Test status
Simulation time 470451983 ps
CPU time 34.12 seconds
Started Jun 06 03:22:36 PM PDT 24
Finished Jun 06 03:23:12 PM PDT 24
Peak memory 249028 kb
Host smart-1ce871bd-2f5a-4db2-ad5d-b48ea8ce3cd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13061
96251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1306196251
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3128364546
Short name T53
Test name
Test status
Simulation time 1051585056 ps
CPU time 35.39 seconds
Started Jun 06 03:22:38 PM PDT 24
Finished Jun 06 03:23:15 PM PDT 24
Peak memory 256160 kb
Host smart-71d16b74-0fb8-4cbc-88a8-6038be99ce6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31283
64546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3128364546
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2931761745
Short name T661
Test name
Test status
Simulation time 297695889 ps
CPU time 25.06 seconds
Started Jun 06 03:22:38 PM PDT 24
Finished Jun 06 03:23:06 PM PDT 24
Peak memory 248796 kb
Host smart-4d93106c-1b95-4265-949e-db9513178a8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29317
61745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2931761745
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3226604896
Short name T91
Test name
Test status
Simulation time 283877699825 ps
CPU time 4351.1 seconds
Started Jun 06 03:22:56 PM PDT 24
Finished Jun 06 04:35:29 PM PDT 24
Peak memory 299028 kb
Host smart-6d41af69-0a50-41e6-b63a-f0ace051a69a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226604896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3226604896
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.286189002
Short name T75
Test name
Test status
Simulation time 58132231929 ps
CPU time 674.28 seconds
Started Jun 06 03:22:56 PM PDT 24
Finished Jun 06 03:34:11 PM PDT 24
Peak memory 273016 kb
Host smart-dda7ebd6-a661-415a-9339-ac43be735bd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286189002 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.286189002
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.2116819597
Short name T649
Test name
Test status
Simulation time 131916567307 ps
CPU time 2338.49 seconds
Started Jun 06 03:23:09 PM PDT 24
Finished Jun 06 04:02:09 PM PDT 24
Peak memory 273408 kb
Host smart-f643c08e-3a57-4df6-86af-8be059204e09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116819597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2116819597
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.3483681514
Short name T657
Test name
Test status
Simulation time 4732854202 ps
CPU time 141.39 seconds
Started Jun 06 03:22:57 PM PDT 24
Finished Jun 06 03:25:19 PM PDT 24
Peak memory 256960 kb
Host smart-0a34018a-7f89-4144-9055-17f015fa63b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34836
81514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3483681514
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.467427149
Short name T680
Test name
Test status
Simulation time 1052180985 ps
CPU time 20.62 seconds
Started Jun 06 03:22:56 PM PDT 24
Finished Jun 06 03:23:18 PM PDT 24
Peak memory 254316 kb
Host smart-74232edb-c2a4-4d97-9dbc-762b32628c88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46742
7149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.467427149
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1361578786
Short name T288
Test name
Test status
Simulation time 97601499897 ps
CPU time 728 seconds
Started Jun 06 03:23:07 PM PDT 24
Finished Jun 06 03:35:16 PM PDT 24
Peak memory 265272 kb
Host smart-f3befe85-ba1f-4013-9483-26c94d63648f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361578786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1361578786
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1481700428
Short name T601
Test name
Test status
Simulation time 16238368477 ps
CPU time 1457.49 seconds
Started Jun 06 03:23:07 PM PDT 24
Finished Jun 06 03:47:25 PM PDT 24
Peak memory 289516 kb
Host smart-362f58dc-6a30-492a-bcef-91eff0e5c8a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481700428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1481700428
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3857522756
Short name T309
Test name
Test status
Simulation time 10569212419 ps
CPU time 450.56 seconds
Started Jun 06 03:23:08 PM PDT 24
Finished Jun 06 03:30:40 PM PDT 24
Peak memory 256324 kb
Host smart-f719b7ae-c593-4de2-8dbe-4d5ced08fe0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857522756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3857522756
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2282764878
Short name T587
Test name
Test status
Simulation time 275909845 ps
CPU time 10.59 seconds
Started Jun 06 03:23:00 PM PDT 24
Finished Jun 06 03:23:11 PM PDT 24
Peak memory 248772 kb
Host smart-41cb05ad-a905-4f12-a6ca-bc3f66141f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22827
64878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2282764878
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.257192307
Short name T607
Test name
Test status
Simulation time 365391050 ps
CPU time 28.44 seconds
Started Jun 06 03:22:55 PM PDT 24
Finished Jun 06 03:23:24 PM PDT 24
Peak memory 254940 kb
Host smart-045b3938-08d2-45c5-b495-da29745af421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25719
2307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.257192307
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.3025663682
Short name T467
Test name
Test status
Simulation time 1107460575 ps
CPU time 25.83 seconds
Started Jun 06 03:23:08 PM PDT 24
Finished Jun 06 03:23:35 PM PDT 24
Peak memory 248988 kb
Host smart-d27691a0-4d7c-49ef-a5ca-ef9be8078d44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30256
63682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.3025663682
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1414779534
Short name T656
Test name
Test status
Simulation time 776519309 ps
CPU time 10.62 seconds
Started Jun 06 03:22:56 PM PDT 24
Finished Jun 06 03:23:07 PM PDT 24
Peak memory 248760 kb
Host smart-226c99f3-dfc0-4015-93ac-520073f9b726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14147
79534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1414779534
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.4245214276
Short name T51
Test name
Test status
Simulation time 196772201713 ps
CPU time 7518.06 seconds
Started Jun 06 03:23:08 PM PDT 24
Finished Jun 06 05:28:28 PM PDT 24
Peak memory 322176 kb
Host smart-70119b99-395f-4c4c-b1e7-db642dff2306
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245214276 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.4245214276
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2855106384
Short name T11
Test name
Test status
Simulation time 45606483152 ps
CPU time 2525.39 seconds
Started Jun 06 03:23:14 PM PDT 24
Finished Jun 06 04:05:21 PM PDT 24
Peak memory 281788 kb
Host smart-19e20ca9-7126-408f-bb1f-e0f08d60adff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855106384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2855106384
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.3697617514
Short name T639
Test name
Test status
Simulation time 36812686658 ps
CPU time 272.29 seconds
Started Jun 06 03:23:15 PM PDT 24
Finished Jun 06 03:27:48 PM PDT 24
Peak memory 256332 kb
Host smart-6f4b6e86-b738-4a77-857b-9635bfd85ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36976
17514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.3697617514
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3469280697
Short name T532
Test name
Test status
Simulation time 553379599 ps
CPU time 8.61 seconds
Started Jun 06 03:23:15 PM PDT 24
Finished Jun 06 03:23:24 PM PDT 24
Peak memory 253056 kb
Host smart-3c8779c6-da34-4716-a5bc-958400447433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34692
80697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3469280697
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.2575084699
Short name T427
Test name
Test status
Simulation time 11133009852 ps
CPU time 940.97 seconds
Started Jun 06 03:23:25 PM PDT 24
Finished Jun 06 03:39:08 PM PDT 24
Peak memory 266364 kb
Host smart-af5819f2-a369-4572-a78f-76618d9f84fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575084699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2575084699
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.69526703
Short name T688
Test name
Test status
Simulation time 5462816019 ps
CPU time 203.98 seconds
Started Jun 06 03:23:15 PM PDT 24
Finished Jun 06 03:26:40 PM PDT 24
Peak memory 247092 kb
Host smart-39ebbdc4-54c3-432e-b9fb-91717686971f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69526703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.69526703
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3860162663
Short name T404
Test name
Test status
Simulation time 1464976718 ps
CPU time 27.17 seconds
Started Jun 06 03:23:15 PM PDT 24
Finished Jun 06 03:23:44 PM PDT 24
Peak memory 248708 kb
Host smart-e06860b1-437f-4af2-a2ee-ea06a24cced3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38601
62663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3860162663
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.3949407495
Short name T496
Test name
Test status
Simulation time 130925468 ps
CPU time 6.35 seconds
Started Jun 06 03:23:15 PM PDT 24
Finished Jun 06 03:23:22 PM PDT 24
Peak memory 247420 kb
Host smart-71b402a2-ac71-4113-9020-67c3e489abe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39494
07495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.3949407495
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.1696900666
Short name T397
Test name
Test status
Simulation time 1345631776 ps
CPU time 48.17 seconds
Started Jun 06 03:23:12 PM PDT 24
Finished Jun 06 03:24:01 PM PDT 24
Peak memory 248588 kb
Host smart-7549983d-dec0-4b4c-8e75-5c516258e91c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16969
00666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.1696900666
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1082185654
Short name T367
Test name
Test status
Simulation time 4291449729 ps
CPU time 58.74 seconds
Started Jun 06 03:23:05 PM PDT 24
Finished Jun 06 03:24:05 PM PDT 24
Peak memory 256876 kb
Host smart-8ec67f7b-9c03-42a0-a49f-342be17e3f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10821
85654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1082185654
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.1802362394
Short name T69
Test name
Test status
Simulation time 122252814717 ps
CPU time 3926.25 seconds
Started Jun 06 03:23:21 PM PDT 24
Finished Jun 06 04:28:49 PM PDT 24
Peak memory 305424 kb
Host smart-75f25620-3fc9-4953-a98b-cb409c4e940d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802362394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.1802362394
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.2926800039
Short name T106
Test name
Test status
Simulation time 79241368853 ps
CPU time 2170.47 seconds
Started Jun 06 03:23:25 PM PDT 24
Finished Jun 06 03:59:37 PM PDT 24
Peak memory 305772 kb
Host smart-092ce765-9383-4f45-a5b8-145c18eb0e53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926800039 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.2926800039
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2171208719
Short name T63
Test name
Test status
Simulation time 75554134638 ps
CPU time 2903.8 seconds
Started Jun 06 03:23:35 PM PDT 24
Finished Jun 06 04:12:00 PM PDT 24
Peak memory 289812 kb
Host smart-7780b9f5-95a2-4aa6-b11a-491348c6f0bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171208719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2171208719
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1084035094
Short name T614
Test name
Test status
Simulation time 1793926198 ps
CPU time 194.43 seconds
Started Jun 06 03:23:24 PM PDT 24
Finished Jun 06 03:26:39 PM PDT 24
Peak memory 256956 kb
Host smart-2dc93661-33b2-43d2-a149-b5231f3e816a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10840
35094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1084035094
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3085321825
Short name T609
Test name
Test status
Simulation time 260909089 ps
CPU time 12.09 seconds
Started Jun 06 03:23:26 PM PDT 24
Finished Jun 06 03:23:40 PM PDT 24
Peak memory 249076 kb
Host smart-6a1c5d13-a365-4510-9f15-bc32b5fc3bf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30853
21825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3085321825
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.4093483538
Short name T325
Test name
Test status
Simulation time 208962297510 ps
CPU time 1235.06 seconds
Started Jun 06 03:23:34 PM PDT 24
Finished Jun 06 03:44:10 PM PDT 24
Peak memory 265280 kb
Host smart-3b975120-f9e9-4ad8-a471-5d7cea44b78d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093483538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.4093483538
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2585790740
Short name T422
Test name
Test status
Simulation time 75711811656 ps
CPU time 2328.69 seconds
Started Jun 06 03:23:36 PM PDT 24
Finished Jun 06 04:02:26 PM PDT 24
Peak memory 273384 kb
Host smart-24accf3f-e9a2-4722-9cce-bc23e570af77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585790740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2585790740
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.1762696024
Short name T549
Test name
Test status
Simulation time 102076686411 ps
CPU time 548.06 seconds
Started Jun 06 03:23:36 PM PDT 24
Finished Jun 06 03:32:45 PM PDT 24
Peak memory 248160 kb
Host smart-b6d437c9-cee0-434b-be9c-aef2b2aef2d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762696024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1762696024
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.258019013
Short name T513
Test name
Test status
Simulation time 221276026 ps
CPU time 14.02 seconds
Started Jun 06 03:23:26 PM PDT 24
Finished Jun 06 03:23:42 PM PDT 24
Peak memory 254920 kb
Host smart-3dc967e0-f5a0-4b64-aaf4-dc6f0115ac23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25801
9013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.258019013
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.4070899777
Short name T355
Test name
Test status
Simulation time 1390015146 ps
CPU time 27.51 seconds
Started Jun 06 03:23:27 PM PDT 24
Finished Jun 06 03:23:56 PM PDT 24
Peak memory 255456 kb
Host smart-8fe9e36f-4bf6-436a-bc37-96dd35b16527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40708
99777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.4070899777
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.389225429
Short name T254
Test name
Test status
Simulation time 7282696925 ps
CPU time 37.9 seconds
Started Jun 06 03:23:36 PM PDT 24
Finished Jun 06 03:24:15 PM PDT 24
Peak memory 255276 kb
Host smart-7defb39b-4a3f-4031-8e0d-c557330c769f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38922
5429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.389225429
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.2095996750
Short name T629
Test name
Test status
Simulation time 233685252 ps
CPU time 5.52 seconds
Started Jun 06 03:23:24 PM PDT 24
Finished Jun 06 03:23:31 PM PDT 24
Peak memory 240564 kb
Host smart-5827ece9-4529-4821-a769-13d47ed83da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20959
96750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2095996750
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.619264478
Short name T454
Test name
Test status
Simulation time 2658005196 ps
CPU time 58.64 seconds
Started Jun 06 03:23:33 PM PDT 24
Finished Jun 06 03:24:33 PM PDT 24
Peak memory 255668 kb
Host smart-1a002272-8a5c-4408-bbca-138b1addb5e5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619264478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_han
dler_stress_all.619264478
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.2103896082
Short name T271
Test name
Test status
Simulation time 19767296810 ps
CPU time 1359.28 seconds
Started Jun 06 03:23:34 PM PDT 24
Finished Jun 06 03:46:15 PM PDT 24
Peak memory 283336 kb
Host smart-a8ff5db7-fc0f-442b-8454-65e1aa94e838
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103896082 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.2103896082
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1845200126
Short name T480
Test name
Test status
Simulation time 11221388856 ps
CPU time 177.7 seconds
Started Jun 06 03:24:01 PM PDT 24
Finished Jun 06 03:27:01 PM PDT 24
Peak memory 256856 kb
Host smart-0e7b8072-217a-428b-8cb9-4166c7a66246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18452
00126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1845200126
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.2767626769
Short name T435
Test name
Test status
Simulation time 3212579240 ps
CPU time 33.64 seconds
Started Jun 06 03:23:48 PM PDT 24
Finished Jun 06 03:24:23 PM PDT 24
Peak memory 256088 kb
Host smart-a94e2e32-5999-4998-b973-c3b2bbfe7e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27676
26769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.2767626769
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.62333781
Short name T312
Test name
Test status
Simulation time 31931051860 ps
CPU time 1914.65 seconds
Started Jun 06 03:24:01 PM PDT 24
Finished Jun 06 03:55:57 PM PDT 24
Peak memory 268252 kb
Host smart-6040082b-5da3-44f4-8fe4-4bdb194849f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62333781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.62333781
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.827367753
Short name T711
Test name
Test status
Simulation time 49910942383 ps
CPU time 1519.88 seconds
Started Jun 06 03:24:02 PM PDT 24
Finished Jun 06 03:49:24 PM PDT 24
Peak memory 288784 kb
Host smart-6b7926c7-42e0-46e7-8985-c761d900c8e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827367753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.827367753
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.417181740
Short name T301
Test name
Test status
Simulation time 40097360959 ps
CPU time 377.24 seconds
Started Jun 06 03:24:00 PM PDT 24
Finished Jun 06 03:30:19 PM PDT 24
Peak memory 248156 kb
Host smart-a5fd9a1f-3a3f-419f-a43d-f5f7ffb26e35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417181740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.417181740
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2922638369
Short name T595
Test name
Test status
Simulation time 468182137 ps
CPU time 22.51 seconds
Started Jun 06 03:23:34 PM PDT 24
Finished Jun 06 03:23:57 PM PDT 24
Peak memory 256588 kb
Host smart-d1d84e92-6271-4b32-aab2-e736a07f315e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29226
38369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2922638369
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.4062278094
Short name T88
Test name
Test status
Simulation time 50608473 ps
CPU time 6.83 seconds
Started Jun 06 03:23:48 PM PDT 24
Finished Jun 06 03:23:56 PM PDT 24
Peak memory 249236 kb
Host smart-9e58eb35-a15b-44f8-b225-bfd394be0f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40622
78094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.4062278094
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.4072464697
Short name T219
Test name
Test status
Simulation time 119036909 ps
CPU time 14.69 seconds
Started Jun 06 03:23:48 PM PDT 24
Finished Jun 06 03:24:04 PM PDT 24
Peak memory 248760 kb
Host smart-8eb00acf-2497-4ddc-b517-e9cc64ff1577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40724
64697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.4072464697
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.1189051320
Short name T347
Test name
Test status
Simulation time 381162552 ps
CPU time 35.28 seconds
Started Jun 06 03:23:34 PM PDT 24
Finished Jun 06 03:24:11 PM PDT 24
Peak memory 248752 kb
Host smart-dfab0eea-4849-4850-9e9c-804f039fca45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11890
51320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1189051320
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.3271442510
Short name T559
Test name
Test status
Simulation time 27573253982 ps
CPU time 1826.12 seconds
Started Jun 06 03:24:01 PM PDT 24
Finished Jun 06 03:54:29 PM PDT 24
Peak memory 286712 kb
Host smart-2656abad-1e68-46bc-9a23-cf0584b728bc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271442510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.3271442510
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.3428378913
Short name T189
Test name
Test status
Simulation time 172022316737 ps
CPU time 7628.84 seconds
Started Jun 06 03:24:02 PM PDT 24
Finished Jun 06 05:31:13 PM PDT 24
Peak memory 370696 kb
Host smart-2a645223-8889-483f-9c3d-155ffbedfbf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428378913 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.3428378913
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2873859664
Short name T113
Test name
Test status
Simulation time 11188900375 ps
CPU time 691.43 seconds
Started Jun 06 03:24:02 PM PDT 24
Finished Jun 06 03:35:35 PM PDT 24
Peak memory 265356 kb
Host smart-e404c168-f972-46ee-992a-a92eed072460
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873859664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2873859664
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3583491128
Short name T584
Test name
Test status
Simulation time 1005880161 ps
CPU time 21.12 seconds
Started Jun 06 03:24:02 PM PDT 24
Finished Jun 06 03:24:25 PM PDT 24
Peak memory 248784 kb
Host smart-38049335-bb04-4a50-91f3-672e20ae475a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35834
91128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3583491128
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3319327269
Short name T655
Test name
Test status
Simulation time 62453759 ps
CPU time 3.5 seconds
Started Jun 06 03:24:03 PM PDT 24
Finished Jun 06 03:24:08 PM PDT 24
Peak memory 240528 kb
Host smart-ad860efb-44a9-4c91-9fe6-69a637986f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33193
27269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3319327269
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1122070480
Short name T366
Test name
Test status
Simulation time 14038768188 ps
CPU time 1110.63 seconds
Started Jun 06 03:24:16 PM PDT 24
Finished Jun 06 03:42:48 PM PDT 24
Peak memory 288852 kb
Host smart-ddf38d8a-896e-4a23-b259-c5ca2b2ed21c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122070480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1122070480
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3365673440
Short name T654
Test name
Test status
Simulation time 4492061787 ps
CPU time 182.2 seconds
Started Jun 06 03:24:18 PM PDT 24
Finished Jun 06 03:27:23 PM PDT 24
Peak memory 248032 kb
Host smart-14bcce4c-ad44-4680-8d43-34aebf990bd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365673440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3365673440
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.188014963
Short name T234
Test name
Test status
Simulation time 1418300158 ps
CPU time 21.84 seconds
Started Jun 06 03:24:01 PM PDT 24
Finished Jun 06 03:24:24 PM PDT 24
Peak memory 248772 kb
Host smart-4efd56f2-28b6-4c4b-bb3d-e06543c2bfdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18801
4963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.188014963
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.1185973933
Short name T638
Test name
Test status
Simulation time 394009814 ps
CPU time 4.9 seconds
Started Jun 06 03:24:01 PM PDT 24
Finished Jun 06 03:24:07 PM PDT 24
Peak memory 239240 kb
Host smart-12313ffc-a98d-44e4-b416-3405533d4527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11859
73933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1185973933
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.2460436563
Short name T77
Test name
Test status
Simulation time 569796426 ps
CPU time 17.3 seconds
Started Jun 06 03:24:01 PM PDT 24
Finished Jun 06 03:24:20 PM PDT 24
Peak memory 255584 kb
Host smart-291ab250-45eb-4f1b-84bd-966757c1ce2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24604
36563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.2460436563
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.2634857014
Short name T233
Test name
Test status
Simulation time 405797481 ps
CPU time 12.52 seconds
Started Jun 06 03:24:00 PM PDT 24
Finished Jun 06 03:24:14 PM PDT 24
Peak memory 248776 kb
Host smart-1e971c42-b55a-4365-9580-ac3ffa222702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26348
57014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2634857014
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.699378490
Short name T221
Test name
Test status
Simulation time 30491389802 ps
CPU time 1771.8 seconds
Started Jun 06 03:24:16 PM PDT 24
Finished Jun 06 03:53:49 PM PDT 24
Peak memory 289788 kb
Host smart-ee33b7d6-b8b4-4e7a-b548-b3d18884b709
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699378490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.699378490
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1520089832
Short name T548
Test name
Test status
Simulation time 1514321855 ps
CPU time 76.44 seconds
Started Jun 06 03:24:14 PM PDT 24
Finished Jun 06 03:25:31 PM PDT 24
Peak memory 248848 kb
Host smart-ef84a8e5-d4d6-4377-9414-158df67754cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15200
89832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1520089832
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.214907807
Short name T469
Test name
Test status
Simulation time 44776437 ps
CPU time 3.76 seconds
Started Jun 06 03:24:14 PM PDT 24
Finished Jun 06 03:24:19 PM PDT 24
Peak memory 240572 kb
Host smart-dd0405f7-4b9b-4f22-b822-8c16f98798ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21490
7807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.214907807
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3502868771
Short name T598
Test name
Test status
Simulation time 44046985821 ps
CPU time 1300.66 seconds
Started Jun 06 03:24:30 PM PDT 24
Finished Jun 06 03:46:11 PM PDT 24
Peak memory 267296 kb
Host smart-505beed5-4040-438b-9467-e851e0703952
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502868771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3502868771
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1846842969
Short name T514
Test name
Test status
Simulation time 35409957038 ps
CPU time 2131.66 seconds
Started Jun 06 03:24:25 PM PDT 24
Finished Jun 06 03:59:58 PM PDT 24
Peak memory 288140 kb
Host smart-df383f06-eed0-4217-827c-5017b2dae2e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846842969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1846842969
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.2933339434
Short name T560
Test name
Test status
Simulation time 3375248364 ps
CPU time 143.27 seconds
Started Jun 06 03:24:24 PM PDT 24
Finished Jun 06 03:26:48 PM PDT 24
Peak memory 248472 kb
Host smart-4f9043b6-b24e-4e0d-9443-992a7fef8c4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933339434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.2933339434
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.957907656
Short name T667
Test name
Test status
Simulation time 141226433 ps
CPU time 15.29 seconds
Started Jun 06 03:24:19 PM PDT 24
Finished Jun 06 03:24:36 PM PDT 24
Peak memory 248768 kb
Host smart-3478bb8d-02e3-448e-ae14-668a824a60a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95790
7656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.957907656
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.700789734
Short name T183
Test name
Test status
Simulation time 1058840765 ps
CPU time 14.53 seconds
Started Jun 06 03:24:13 PM PDT 24
Finished Jun 06 03:24:28 PM PDT 24
Peak memory 253092 kb
Host smart-4235558a-bb73-4f7e-b6c1-3f09076f6720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70078
9734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.700789734
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.4275751325
Short name T458
Test name
Test status
Simulation time 96502508 ps
CPU time 6.21 seconds
Started Jun 06 03:24:29 PM PDT 24
Finished Jun 06 03:24:37 PM PDT 24
Peak memory 248796 kb
Host smart-a3601de2-e0f3-496c-b88c-9798bdff3dd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42757
51325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.4275751325
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.472919034
Short name T180
Test name
Test status
Simulation time 237673222 ps
CPU time 5.53 seconds
Started Jun 06 03:24:13 PM PDT 24
Finished Jun 06 03:24:19 PM PDT 24
Peak memory 240568 kb
Host smart-10397a91-9cab-4b04-ad77-e5b4cfaa079c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47291
9034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.472919034
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.75842303
Short name T659
Test name
Test status
Simulation time 3427150730 ps
CPU time 114.11 seconds
Started Jun 06 03:24:30 PM PDT 24
Finished Jun 06 03:26:25 PM PDT 24
Peak memory 256968 kb
Host smart-f1c4768c-2bbd-45eb-9dd0-ff83b39fb89c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75842303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_hand
ler_stress_all.75842303
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.1106369428
Short name T646
Test name
Test status
Simulation time 14469644200 ps
CPU time 932.32 seconds
Started Jun 06 03:14:19 PM PDT 24
Finished Jun 06 03:29:54 PM PDT 24
Peak memory 272640 kb
Host smart-e989ad59-bb8b-4d48-87d7-ff0e92853207
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106369428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1106369428
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.4259384367
Short name T693
Test name
Test status
Simulation time 709654374 ps
CPU time 9.92 seconds
Started Jun 06 03:14:17 PM PDT 24
Finished Jun 06 03:14:30 PM PDT 24
Peak memory 248744 kb
Host smart-e8a55a73-642f-4c97-aa0d-24dae110dd02
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4259384367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.4259384367
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.1130005113
Short name T543
Test name
Test status
Simulation time 20924906111 ps
CPU time 289.25 seconds
Started Jun 06 03:14:09 PM PDT 24
Finished Jun 06 03:18:59 PM PDT 24
Peak memory 255648 kb
Host smart-f6305d9b-8cf4-4824-9791-729efac6bbe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11300
05113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1130005113
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2907493392
Short name T658
Test name
Test status
Simulation time 6751317615 ps
CPU time 24.1 seconds
Started Jun 06 03:14:08 PM PDT 24
Finished Jun 06 03:14:33 PM PDT 24
Peak memory 248772 kb
Host smart-6d788190-be41-480f-9bb6-b77d907b205c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29074
93392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2907493392
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2715291642
Short name T320
Test name
Test status
Simulation time 40177670755 ps
CPU time 1686.9 seconds
Started Jun 06 03:14:19 PM PDT 24
Finished Jun 06 03:42:28 PM PDT 24
Peak memory 289040 kb
Host smart-72ee6196-d470-44f0-b3d3-f46240e2340e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715291642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2715291642
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.517977744
Short name T33
Test name
Test status
Simulation time 31492542545 ps
CPU time 1957.87 seconds
Started Jun 06 03:14:18 PM PDT 24
Finished Jun 06 03:46:59 PM PDT 24
Peak memory 281648 kb
Host smart-fe914e78-6468-49cb-bdc1-9ced45416022
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517977744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.517977744
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.572115080
Short name T633
Test name
Test status
Simulation time 23052451030 ps
CPU time 411.57 seconds
Started Jun 06 03:14:18 PM PDT 24
Finished Jun 06 03:21:12 PM PDT 24
Peak memory 248864 kb
Host smart-16ecd71b-4ea7-473a-88e1-91beb6978a3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572115080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.572115080
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.621676798
Short name T344
Test name
Test status
Simulation time 351885281 ps
CPU time 30.57 seconds
Started Jun 06 03:13:57 PM PDT 24
Finished Jun 06 03:14:29 PM PDT 24
Peak memory 256024 kb
Host smart-2f82800d-e7aa-4cb9-916c-5f619a1377df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62167
6798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.621676798
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.4136286882
Short name T449
Test name
Test status
Simulation time 862242405 ps
CPU time 14.82 seconds
Started Jun 06 03:14:10 PM PDT 24
Finished Jun 06 03:14:26 PM PDT 24
Peak memory 253180 kb
Host smart-cd369f24-0307-4ea2-aeed-003fda8c6c3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41362
86882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.4136286882
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1196741606
Short name T8
Test name
Test status
Simulation time 2283559366 ps
CPU time 25.69 seconds
Started Jun 06 03:14:28 PM PDT 24
Finished Jun 06 03:14:54 PM PDT 24
Peak memory 273640 kb
Host smart-8c1f6aad-cddf-4a1d-9e3d-a48c99b7dbfd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1196741606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1196741606
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.4068745460
Short name T383
Test name
Test status
Simulation time 2089788454 ps
CPU time 39.85 seconds
Started Jun 06 03:14:19 PM PDT 24
Finished Jun 06 03:15:01 PM PDT 24
Peak memory 249140 kb
Host smart-9f16018e-da2c-4fb1-a411-f0ebcdc80904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40687
45460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.4068745460
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1666795189
Short name T509
Test name
Test status
Simulation time 5064013396 ps
CPU time 71.75 seconds
Started Jun 06 03:13:57 PM PDT 24
Finished Jun 06 03:15:09 PM PDT 24
Peak memory 248836 kb
Host smart-e607807c-999e-4bfb-9c47-40c958853b4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16667
95189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1666795189
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.1271270742
Short name T418
Test name
Test status
Simulation time 43994816583 ps
CPU time 2672.87 seconds
Started Jun 06 03:14:19 PM PDT 24
Finished Jun 06 03:58:54 PM PDT 24
Peak memory 289656 kb
Host smart-7977998b-cfac-4bc8-b029-8a2810bb6a19
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271270742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.1271270742
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3230874445
Short name T382
Test name
Test status
Simulation time 34469008573 ps
CPU time 1938.65 seconds
Started Jun 06 03:24:51 PM PDT 24
Finished Jun 06 03:57:12 PM PDT 24
Peak memory 270596 kb
Host smart-e50506f1-f379-4ae9-967d-d8a9f53abc5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230874445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3230874445
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3015193398
Short name T391
Test name
Test status
Simulation time 2747058780 ps
CPU time 118.85 seconds
Started Jun 06 03:24:51 PM PDT 24
Finished Jun 06 03:26:52 PM PDT 24
Peak memory 256812 kb
Host smart-597f751f-79cb-4955-94f6-bd2adc0b8be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30151
93398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3015193398
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.3181887826
Short name T108
Test name
Test status
Simulation time 113027982 ps
CPU time 11.25 seconds
Started Jun 06 03:24:48 PM PDT 24
Finished Jun 06 03:25:00 PM PDT 24
Peak memory 248764 kb
Host smart-0c9c3368-69a3-46d7-8b3e-85bb685a7e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31818
87826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3181887826
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.1714024841
Short name T319
Test name
Test status
Simulation time 7906278764 ps
CPU time 628.77 seconds
Started Jun 06 03:24:49 PM PDT 24
Finished Jun 06 03:35:20 PM PDT 24
Peak memory 265220 kb
Host smart-1b0aeb5b-ae84-4840-aedd-0b9fe40a22ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714024841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1714024841
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.8004068
Short name T452
Test name
Test status
Simulation time 17792092028 ps
CPU time 1327.51 seconds
Started Jun 06 03:24:54 PM PDT 24
Finished Jun 06 03:47:04 PM PDT 24
Peak memory 283752 kb
Host smart-41d0215c-dcfc-4256-89b8-6c67a235d0ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8004068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.8004068
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1260828450
Short name T682
Test name
Test status
Simulation time 35091532930 ps
CPU time 228.18 seconds
Started Jun 06 03:24:50 PM PDT 24
Finished Jun 06 03:28:41 PM PDT 24
Peak memory 247120 kb
Host smart-ba9afd56-8674-49f7-9865-7fc2d308dbd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260828450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1260828450
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3625475472
Short name T377
Test name
Test status
Simulation time 782454251 ps
CPU time 21.24 seconds
Started Jun 06 03:24:35 PM PDT 24
Finished Jun 06 03:24:58 PM PDT 24
Peak memory 248860 kb
Host smart-6637bfd5-7bad-4be3-a6d0-8ae10347a0fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36254
75472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3625475472
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.2175040600
Short name T710
Test name
Test status
Simulation time 4145177294 ps
CPU time 51.93 seconds
Started Jun 06 03:24:38 PM PDT 24
Finished Jun 06 03:25:31 PM PDT 24
Peak memory 248616 kb
Host smart-99523de5-f858-4d8d-9911-a9965c230d66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21750
40600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.2175040600
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.2234110691
Short name T388
Test name
Test status
Simulation time 133786582 ps
CPU time 17.06 seconds
Started Jun 06 03:24:49 PM PDT 24
Finished Jun 06 03:25:09 PM PDT 24
Peak memory 255160 kb
Host smart-25667552-d01e-408b-a4fd-5d438291ad16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22341
10691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2234110691
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.131823490
Short name T517
Test name
Test status
Simulation time 524496211 ps
CPU time 32.82 seconds
Started Jun 06 03:24:34 PM PDT 24
Finished Jun 06 03:25:08 PM PDT 24
Peak memory 248748 kb
Host smart-8b88f400-4124-4ebc-b217-9ef1d44b2136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13182
3490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.131823490
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2964243124
Short name T671
Test name
Test status
Simulation time 19496704360 ps
CPU time 472.37 seconds
Started Jun 06 03:24:53 PM PDT 24
Finished Jun 06 03:32:47 PM PDT 24
Peak memory 267492 kb
Host smart-bac3599c-8669-47de-8a61-b8ace47e2094
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964243124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2964243124
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.1691736112
Short name T61
Test name
Test status
Simulation time 45685968507 ps
CPU time 841.19 seconds
Started Jun 06 03:24:56 PM PDT 24
Finished Jun 06 03:38:59 PM PDT 24
Peak memory 269368 kb
Host smart-1ebe9e29-9b94-40b7-990a-0abb1edc2bbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691736112 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.1691736112
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.535008131
Short name T617
Test name
Test status
Simulation time 28326409520 ps
CPU time 1712.66 seconds
Started Jun 06 03:25:09 PM PDT 24
Finished Jun 06 03:53:43 PM PDT 24
Peak memory 282084 kb
Host smart-31569b17-9d0a-4735-9040-0b532c457586
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535008131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.535008131
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.6864002
Short name T402
Test name
Test status
Simulation time 600669312 ps
CPU time 6.56 seconds
Started Jun 06 03:25:07 PM PDT 24
Finished Jun 06 03:25:15 PM PDT 24
Peak memory 250848 kb
Host smart-6a720af9-bd63-4544-b88b-f7c6a023b0b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68640
02 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.6864002
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.3725301330
Short name T358
Test name
Test status
Simulation time 2030046199 ps
CPU time 48.87 seconds
Started Jun 06 03:24:57 PM PDT 24
Finished Jun 06 03:25:47 PM PDT 24
Peak memory 249148 kb
Host smart-e2c514a3-dbed-4adf-9e4f-a3b1d881818f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37253
01330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3725301330
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2325792806
Short name T531
Test name
Test status
Simulation time 36916402912 ps
CPU time 2417.53 seconds
Started Jun 06 03:25:08 PM PDT 24
Finished Jun 06 04:05:28 PM PDT 24
Peak memory 289072 kb
Host smart-8b5f9d2f-1593-4dc7-84c5-c4ca843bef88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325792806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2325792806
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2553126795
Short name T640
Test name
Test status
Simulation time 92889028246 ps
CPU time 2421.63 seconds
Started Jun 06 03:25:09 PM PDT 24
Finished Jun 06 04:05:32 PM PDT 24
Peak memory 289260 kb
Host smart-1f10d696-955f-41b3-9bd3-8bf4d1acdfaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553126795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2553126795
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2411377375
Short name T294
Test name
Test status
Simulation time 13297642564 ps
CPU time 291.17 seconds
Started Jun 06 03:25:08 PM PDT 24
Finished Jun 06 03:30:01 PM PDT 24
Peak memory 248156 kb
Host smart-11382238-4866-420b-8c11-11a650d5dce5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411377375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2411377375
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1669990148
Short name T475
Test name
Test status
Simulation time 104556283 ps
CPU time 5.33 seconds
Started Jun 06 03:25:02 PM PDT 24
Finished Jun 06 03:25:09 PM PDT 24
Peak memory 248732 kb
Host smart-673d2ef2-41b7-4720-8404-65e167161c3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16699
90148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1669990148
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.3727500418
Short name T263
Test name
Test status
Simulation time 2486040933 ps
CPU time 51.02 seconds
Started Jun 06 03:25:07 PM PDT 24
Finished Jun 06 03:26:00 PM PDT 24
Peak memory 255412 kb
Host smart-ee5e36c6-b8be-4e85-a53b-73c078ffba2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37275
00418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3727500418
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2355158924
Short name T708
Test name
Test status
Simulation time 54894257 ps
CPU time 8.48 seconds
Started Jun 06 03:24:54 PM PDT 24
Finished Jun 06 03:25:04 PM PDT 24
Peak memory 248772 kb
Host smart-a0d878c4-e320-41eb-ae45-4cba97b77527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23551
58924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2355158924
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1352875832
Short name T522
Test name
Test status
Simulation time 10231943303 ps
CPU time 243.3 seconds
Started Jun 06 03:25:18 PM PDT 24
Finished Jun 06 03:29:24 PM PDT 24
Peak memory 256968 kb
Host smart-acca8ce3-9be1-4760-9479-aa7db80752f7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352875832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1352875832
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.4242008026
Short name T672
Test name
Test status
Simulation time 1044417732 ps
CPU time 37.7 seconds
Started Jun 06 03:25:20 PM PDT 24
Finished Jun 06 03:26:00 PM PDT 24
Peak memory 249176 kb
Host smart-84a1cf93-2b55-4b4c-80d3-bf03142c5c2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42420
08026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.4242008026
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.4224587267
Short name T538
Test name
Test status
Simulation time 631251901 ps
CPU time 39.89 seconds
Started Jun 06 03:25:18 PM PDT 24
Finished Jun 06 03:26:00 PM PDT 24
Peak memory 248784 kb
Host smart-0084b355-22c8-450a-94e2-ca6abcb8e0da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42245
87267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.4224587267
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.4058700424
Short name T103
Test name
Test status
Simulation time 15843680556 ps
CPU time 1006.15 seconds
Started Jun 06 03:25:20 PM PDT 24
Finished Jun 06 03:42:09 PM PDT 24
Peak memory 267384 kb
Host smart-16b209fd-63a2-48ff-bf78-018ab75f6535
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058700424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.4058700424
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.2510001309
Short name T621
Test name
Test status
Simulation time 125469448386 ps
CPU time 1234.15 seconds
Started Jun 06 03:25:19 PM PDT 24
Finished Jun 06 03:45:55 PM PDT 24
Peak memory 287276 kb
Host smart-5c66e311-a5d0-49a0-aa8f-dabd8d198a62
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510001309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2510001309
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.970242783
Short name T534
Test name
Test status
Simulation time 376764747 ps
CPU time 28.96 seconds
Started Jun 06 03:25:11 PM PDT 24
Finished Jun 06 03:25:42 PM PDT 24
Peak memory 248760 kb
Host smart-121c20f6-e8ea-4754-9834-a9377ef3df15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97024
2783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.970242783
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.161348906
Short name T620
Test name
Test status
Simulation time 1788339723 ps
CPU time 28.63 seconds
Started Jun 06 03:25:17 PM PDT 24
Finished Jun 06 03:25:47 PM PDT 24
Peak memory 255840 kb
Host smart-94081a87-23a7-47f5-872b-923d8a49cdda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16134
8906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.161348906
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.24879555
Short name T76
Test name
Test status
Simulation time 1079971866 ps
CPU time 44.09 seconds
Started Jun 06 03:25:21 PM PDT 24
Finished Jun 06 03:26:07 PM PDT 24
Peak memory 248716 kb
Host smart-51f7042f-d0d3-469a-b2f0-e95c70c2a646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24879
555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.24879555
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.3685954483
Short name T43
Test name
Test status
Simulation time 588248000 ps
CPU time 34.77 seconds
Started Jun 06 03:25:09 PM PDT 24
Finished Jun 06 03:25:45 PM PDT 24
Peak memory 248960 kb
Host smart-47dfd544-70ca-46e7-80f7-12a1a759d056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36859
54483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3685954483
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.4221540765
Short name T178
Test name
Test status
Simulation time 266274967912 ps
CPU time 6754.25 seconds
Started Jun 06 03:25:18 PM PDT 24
Finished Jun 06 05:17:56 PM PDT 24
Peak memory 370952 kb
Host smart-e5d3a23b-ad5d-4494-91ef-de4434bdfd17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221540765 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.4221540765
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.422185131
Short name T569
Test name
Test status
Simulation time 29802485741 ps
CPU time 1760.34 seconds
Started Jun 06 03:25:28 PM PDT 24
Finished Jun 06 03:54:50 PM PDT 24
Peak memory 289784 kb
Host smart-08e4cc45-da63-4182-a259-1afaad2d253f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422185131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.422185131
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.483394961
Short name T497
Test name
Test status
Simulation time 2006417094 ps
CPU time 49.86 seconds
Started Jun 06 03:25:30 PM PDT 24
Finished Jun 06 03:26:21 PM PDT 24
Peak memory 255952 kb
Host smart-c0ac3ef3-4394-4758-80d3-370c5582b2e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48339
4961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.483394961
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.600286253
Short name T72
Test name
Test status
Simulation time 335764619 ps
CPU time 20.12 seconds
Started Jun 06 03:25:29 PM PDT 24
Finished Jun 06 03:25:50 PM PDT 24
Peak memory 249068 kb
Host smart-d50cdc21-056a-4978-94fe-b53076e20ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60028
6253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.600286253
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3072506822
Short name T670
Test name
Test status
Simulation time 12800361673 ps
CPU time 1493.06 seconds
Started Jun 06 03:25:38 PM PDT 24
Finished Jun 06 03:50:33 PM PDT 24
Peak memory 289304 kb
Host smart-3f7352ae-06ba-4807-8c8b-52b29c31df96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072506822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3072506822
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.2933237456
Short name T465
Test name
Test status
Simulation time 14099092793 ps
CPU time 570.72 seconds
Started Jun 06 03:25:30 PM PDT 24
Finished Jun 06 03:35:02 PM PDT 24
Peak memory 247084 kb
Host smart-64e51f8b-8b56-411d-bd91-5d4b3fc455f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933237456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.2933237456
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.1332405972
Short name T553
Test name
Test status
Simulation time 750727902 ps
CPU time 12.57 seconds
Started Jun 06 03:25:20 PM PDT 24
Finished Jun 06 03:25:35 PM PDT 24
Peak memory 248788 kb
Host smart-ebdd4e3e-cf60-425e-b460-0cc8c2beea2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13324
05972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.1332405972
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.757403348
Short name T226
Test name
Test status
Simulation time 803207021 ps
CPU time 26.79 seconds
Started Jun 06 03:25:20 PM PDT 24
Finished Jun 06 03:25:49 PM PDT 24
Peak memory 248652 kb
Host smart-26682ea0-2717-4641-86a7-ab80211058bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75740
3348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.757403348
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1871616829
Short name T238
Test name
Test status
Simulation time 32133704 ps
CPU time 4.94 seconds
Started Jun 06 03:25:29 PM PDT 24
Finished Jun 06 03:25:35 PM PDT 24
Peak memory 240560 kb
Host smart-445a0336-d885-495f-a941-3a4cab8ab78f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18716
16829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1871616829
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.483002492
Short name T107
Test name
Test status
Simulation time 1118449529 ps
CPU time 10.44 seconds
Started Jun 06 03:25:19 PM PDT 24
Finished Jun 06 03:25:31 PM PDT 24
Peak memory 248740 kb
Host smart-0e4b49e0-3d33-448b-8cc0-45d16d392c8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48300
2492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.483002492
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3501469322
Short name T626
Test name
Test status
Simulation time 79742735051 ps
CPU time 2618.96 seconds
Started Jun 06 03:25:38 PM PDT 24
Finished Jun 06 04:09:18 PM PDT 24
Peak memory 289724 kb
Host smart-4c2377ab-a809-421d-adf3-74f5a1d6e906
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501469322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3501469322
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.3749943888
Short name T490
Test name
Test status
Simulation time 24954578707 ps
CPU time 2644.18 seconds
Started Jun 06 03:25:39 PM PDT 24
Finished Jun 06 04:09:45 PM PDT 24
Peak memory 306036 kb
Host smart-2c19c464-67a0-415f-92b3-808c3b30de6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749943888 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.3749943888
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.185430864
Short name T525
Test name
Test status
Simulation time 29830076506 ps
CPU time 1702.78 seconds
Started Jun 06 03:25:48 PM PDT 24
Finished Jun 06 03:54:12 PM PDT 24
Peak memory 273428 kb
Host smart-599afe96-6259-478a-8c23-756d42912cad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185430864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.185430864
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3715089529
Short name T575
Test name
Test status
Simulation time 8794646384 ps
CPU time 274.57 seconds
Started Jun 06 03:25:39 PM PDT 24
Finished Jun 06 03:30:14 PM PDT 24
Peak memory 257000 kb
Host smart-eb7c5554-7668-40ca-b9eb-d705b28136f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37150
89529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3715089529
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.4117785557
Short name T410
Test name
Test status
Simulation time 291903559 ps
CPU time 7.62 seconds
Started Jun 06 03:25:39 PM PDT 24
Finished Jun 06 03:25:47 PM PDT 24
Peak memory 250852 kb
Host smart-354aaef2-dab7-48a0-87a5-30fbca647ded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41177
85557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.4117785557
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1558947347
Short name T561
Test name
Test status
Simulation time 37457981093 ps
CPU time 1646.96 seconds
Started Jun 06 03:25:46 PM PDT 24
Finished Jun 06 03:53:15 PM PDT 24
Peak memory 272840 kb
Host smart-62935765-9d33-4a6d-aaf9-8e893d0c7f90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558947347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1558947347
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.2587266841
Short name T346
Test name
Test status
Simulation time 71929520632 ps
CPU time 1260.04 seconds
Started Jun 06 03:25:58 PM PDT 24
Finished Jun 06 03:47:01 PM PDT 24
Peak memory 273352 kb
Host smart-acb1fb56-3d03-44e9-adc4-d5fd2eedd868
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587266841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2587266841
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.3680406462
Short name T562
Test name
Test status
Simulation time 41767245894 ps
CPU time 395.35 seconds
Started Jun 06 03:25:47 PM PDT 24
Finished Jun 06 03:32:23 PM PDT 24
Peak memory 248252 kb
Host smart-0e17d5f3-20fb-4428-b3bf-711beb194fca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680406462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3680406462
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1121737906
Short name T432
Test name
Test status
Simulation time 798032453 ps
CPU time 53.09 seconds
Started Jun 06 03:25:37 PM PDT 24
Finished Jun 06 03:26:31 PM PDT 24
Peak memory 248836 kb
Host smart-60c5ef70-9235-4d5c-9242-ea0434338000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11217
37906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1121737906
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.3951446774
Short name T417
Test name
Test status
Simulation time 194414159 ps
CPU time 7.95 seconds
Started Jun 06 03:25:37 PM PDT 24
Finished Jun 06 03:25:46 PM PDT 24
Peak memory 248760 kb
Host smart-1c7617fa-bca7-4c22-bb99-8a2572b19bbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39514
46774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3951446774
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.1482356798
Short name T482
Test name
Test status
Simulation time 815124781 ps
CPU time 57.64 seconds
Started Jun 06 03:25:48 PM PDT 24
Finished Jun 06 03:26:47 PM PDT 24
Peak memory 248752 kb
Host smart-d27b029b-0403-4a71-b646-1300388959f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14823
56798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1482356798
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2630215671
Short name T357
Test name
Test status
Simulation time 5593180010 ps
CPU time 43.92 seconds
Started Jun 06 03:25:37 PM PDT 24
Finished Jun 06 03:26:22 PM PDT 24
Peak memory 248908 kb
Host smart-9d44dc32-35b2-4ec4-bf98-d0eae142b5df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26302
15671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2630215671
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.3254762749
Short name T79
Test name
Test status
Simulation time 95758068555 ps
CPU time 785.2 seconds
Started Jun 06 03:25:59 PM PDT 24
Finished Jun 06 03:39:07 PM PDT 24
Peak memory 273116 kb
Host smart-e96dca9d-7e3d-462e-8d77-941ef017088c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254762749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.3254762749
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3377488039
Short name T405
Test name
Test status
Simulation time 51391737772 ps
CPU time 2937.6 seconds
Started Jun 06 03:26:13 PM PDT 24
Finished Jun 06 04:15:12 PM PDT 24
Peak memory 288820 kb
Host smart-f312e4e7-5c21-4850-afa2-25b2b91b2d0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377488039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3377488039
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.92860159
Short name T586
Test name
Test status
Simulation time 8991435464 ps
CPU time 181.11 seconds
Started Jun 06 03:26:14 PM PDT 24
Finished Jun 06 03:29:16 PM PDT 24
Peak memory 257012 kb
Host smart-655218f2-bee4-4b4e-bfd2-8e584910d17c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92860
159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.92860159
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2187559017
Short name T80
Test name
Test status
Simulation time 537179473 ps
CPU time 9.68 seconds
Started Jun 06 03:26:13 PM PDT 24
Finished Jun 06 03:26:24 PM PDT 24
Peak memory 248728 kb
Host smart-9c38c3ae-1104-4072-bfb8-4f56e33bdd54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21875
59017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2187559017
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.1341345754
Short name T10
Test name
Test status
Simulation time 87713840454 ps
CPU time 1688.83 seconds
Started Jun 06 03:26:26 PM PDT 24
Finished Jun 06 03:54:37 PM PDT 24
Peak memory 272772 kb
Host smart-c64e560f-e7eb-43bb-945e-85104c052422
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341345754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.1341345754
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.73500407
Short name T652
Test name
Test status
Simulation time 153897766671 ps
CPU time 1791.85 seconds
Started Jun 06 03:26:26 PM PDT 24
Finished Jun 06 03:56:19 PM PDT 24
Peak memory 284228 kb
Host smart-f7ac7f3d-401f-4a4c-a694-70bd94144407
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73500407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.73500407
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2046163841
Short name T605
Test name
Test status
Simulation time 10254221605 ps
CPU time 409.77 seconds
Started Jun 06 03:26:14 PM PDT 24
Finished Jun 06 03:33:04 PM PDT 24
Peak memory 248252 kb
Host smart-37f6bc83-3469-43f4-9e56-eb8e25228712
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046163841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2046163841
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3492763620
Short name T20
Test name
Test status
Simulation time 1833529172 ps
CPU time 43.23 seconds
Started Jun 06 03:25:58 PM PDT 24
Finished Jun 06 03:26:44 PM PDT 24
Peak memory 255792 kb
Host smart-f35bde27-62ff-4e1f-bdc4-63df610ac1ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34927
63620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3492763620
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.4156074878
Short name T483
Test name
Test status
Simulation time 118711342 ps
CPU time 12.82 seconds
Started Jun 06 03:26:14 PM PDT 24
Finished Jun 06 03:26:28 PM PDT 24
Peak memory 247452 kb
Host smart-4c2a78cd-1b6a-440c-acaf-1b661a6019b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41560
74878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.4156074878
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3729876356
Short name T540
Test name
Test status
Simulation time 5330384006 ps
CPU time 24.93 seconds
Started Jun 06 03:25:58 PM PDT 24
Finished Jun 06 03:26:26 PM PDT 24
Peak memory 256376 kb
Host smart-68c16c2d-0d4b-4f1c-a071-4a6616d0b72d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37298
76356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3729876356
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.262870109
Short name T412
Test name
Test status
Simulation time 38971742709 ps
CPU time 2176.25 seconds
Started Jun 06 03:26:25 PM PDT 24
Finished Jun 06 04:02:42 PM PDT 24
Peak memory 289348 kb
Host smart-b8180ca7-2bb7-4cbe-81c6-f0596f9eeee4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262870109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_han
dler_stress_all.262870109
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.1505367929
Short name T566
Test name
Test status
Simulation time 45474685609 ps
CPU time 2937.17 seconds
Started Jun 06 03:26:26 PM PDT 24
Finished Jun 06 04:15:25 PM PDT 24
Peak memory 289788 kb
Host smart-e47093a1-6a53-4ed8-a05a-3dc51a900bd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505367929 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.1505367929
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.368310846
Short name T704
Test name
Test status
Simulation time 9251626129 ps
CPU time 666.77 seconds
Started Jun 06 03:26:36 PM PDT 24
Finished Jun 06 03:37:45 PM PDT 24
Peak memory 265168 kb
Host smart-6e688c21-7f66-4218-9f96-c5b452794f6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368310846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.368310846
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.582087122
Short name T45
Test name
Test status
Simulation time 332910239 ps
CPU time 32.79 seconds
Started Jun 06 03:26:26 PM PDT 24
Finished Jun 06 03:27:01 PM PDT 24
Peak memory 255200 kb
Host smart-e9262677-3826-4835-9192-cf3bf2e29c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58208
7122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.582087122
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2117938937
Short name T348
Test name
Test status
Simulation time 679088372 ps
CPU time 15.56 seconds
Started Jun 06 03:26:25 PM PDT 24
Finished Jun 06 03:26:42 PM PDT 24
Peak memory 248756 kb
Host smart-6174e91d-508c-49ab-a0ba-dcd60df63dbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21179
38937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2117938937
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.1522903191
Short name T314
Test name
Test status
Simulation time 38040666192 ps
CPU time 2772.92 seconds
Started Jun 06 03:26:35 PM PDT 24
Finished Jun 06 04:12:50 PM PDT 24
Peak memory 289340 kb
Host smart-a27ea165-ee2d-465f-a35a-11cbc147747c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522903191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1522903191
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.693788970
Short name T511
Test name
Test status
Simulation time 154033466316 ps
CPU time 1724.24 seconds
Started Jun 06 03:26:36 PM PDT 24
Finished Jun 06 03:55:22 PM PDT 24
Peak memory 273436 kb
Host smart-9712e83b-8218-442f-b0cd-d752d73a2100
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693788970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.693788970
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.697739163
Short name T303
Test name
Test status
Simulation time 62204257767 ps
CPU time 582.15 seconds
Started Jun 06 03:26:36 PM PDT 24
Finished Jun 06 03:36:20 PM PDT 24
Peak memory 248336 kb
Host smart-0a541f03-07de-4267-8708-2cac20529a4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697739163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.697739163
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3295383468
Short name T423
Test name
Test status
Simulation time 1634316753 ps
CPU time 36.61 seconds
Started Jun 06 03:26:26 PM PDT 24
Finished Jun 06 03:27:04 PM PDT 24
Peak memory 255928 kb
Host smart-f970ae92-a91f-48f8-a281-83bc8b4cf73c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32953
83468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3295383468
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3751084484
Short name T35
Test name
Test status
Simulation time 368880602 ps
CPU time 36.29 seconds
Started Jun 06 03:26:25 PM PDT 24
Finished Jun 06 03:27:02 PM PDT 24
Peak memory 256852 kb
Host smart-24cedd28-f916-4e38-b224-7533bc1af69f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37510
84484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3751084484
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3578416366
Short name T378
Test name
Test status
Simulation time 50981943 ps
CPU time 7.2 seconds
Started Jun 06 03:26:25 PM PDT 24
Finished Jun 06 03:26:34 PM PDT 24
Peak memory 253076 kb
Host smart-ccbc113c-a484-463c-94a6-e36c0a7aee94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35784
16366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3578416366
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.773141481
Short name T501
Test name
Test status
Simulation time 352568465 ps
CPU time 26.73 seconds
Started Jun 06 03:26:25 PM PDT 24
Finished Jun 06 03:26:53 PM PDT 24
Peak memory 248808 kb
Host smart-fccbfcf8-d2f3-4c5d-b4a4-d38e9cbb12ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77314
1481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.773141481
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.2105756440
Short name T597
Test name
Test status
Simulation time 463702624 ps
CPU time 28.67 seconds
Started Jun 06 03:26:35 PM PDT 24
Finished Jun 06 03:27:06 PM PDT 24
Peak memory 255968 kb
Host smart-a695ec0a-e9b4-4db6-8009-075b7144fb05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21057
56440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.2105756440
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.992426363
Short name T40
Test name
Test status
Simulation time 1504995261 ps
CPU time 29.92 seconds
Started Jun 06 03:26:39 PM PDT 24
Finished Jun 06 03:27:11 PM PDT 24
Peak memory 255348 kb
Host smart-67cd6d62-1548-43d2-aa64-e1b3b84b6911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99242
6363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.992426363
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.1430659524
Short name T225
Test name
Test status
Simulation time 14361285207 ps
CPU time 1264.09 seconds
Started Jun 06 03:26:46 PM PDT 24
Finished Jun 06 03:47:52 PM PDT 24
Peak memory 272780 kb
Host smart-ce965c03-d215-422c-ba13-3477aeee453d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430659524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.1430659524
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.2914490739
Short name T425
Test name
Test status
Simulation time 66503064364 ps
CPU time 1136.71 seconds
Started Jun 06 03:26:48 PM PDT 24
Finished Jun 06 03:45:47 PM PDT 24
Peak memory 282736 kb
Host smart-bead4e54-a200-47f9-83cc-2e8f809e9e73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914490739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2914490739
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2769433623
Short name T653
Test name
Test status
Simulation time 17883402602 ps
CPU time 488.36 seconds
Started Jun 06 03:26:49 PM PDT 24
Finished Jun 06 03:34:59 PM PDT 24
Peak memory 248140 kb
Host smart-9f44ad10-4058-4cab-9442-abd255e2107b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769433623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2769433623
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.17233620
Short name T393
Test name
Test status
Simulation time 156605657 ps
CPU time 12.27 seconds
Started Jun 06 03:26:37 PM PDT 24
Finished Jun 06 03:26:52 PM PDT 24
Peak memory 252780 kb
Host smart-2473658d-60b2-4236-b5c0-d9c272204324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17233
620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.17233620
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1609019175
Short name T14
Test name
Test status
Simulation time 922765451 ps
CPU time 29.07 seconds
Started Jun 06 03:26:37 PM PDT 24
Finished Jun 06 03:27:09 PM PDT 24
Peak memory 248884 kb
Host smart-94195a57-439f-4b88-9b79-53e750f1484c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16090
19175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1609019175
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.1885552923
Short name T350
Test name
Test status
Simulation time 36391847 ps
CPU time 3.35 seconds
Started Jun 06 03:26:35 PM PDT 24
Finished Jun 06 03:26:40 PM PDT 24
Peak memory 240736 kb
Host smart-80d5203a-1fc2-46de-997f-38bfa35623d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18855
52923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.1885552923
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.1726827918
Short name T523
Test name
Test status
Simulation time 116718207 ps
CPU time 17.23 seconds
Started Jun 06 03:26:37 PM PDT 24
Finished Jun 06 03:26:57 PM PDT 24
Peak memory 254928 kb
Host smart-c1c17e17-83b8-4e0d-b83a-340297fa1fca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17268
27918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1726827918
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2383436372
Short name T499
Test name
Test status
Simulation time 16668215098 ps
CPU time 408.46 seconds
Started Jun 06 03:26:56 PM PDT 24
Finished Jun 06 03:33:46 PM PDT 24
Peak memory 265184 kb
Host smart-854306c3-32ce-4b50-a2b0-92097b413575
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383436372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2383436372
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2277790307
Short name T36
Test name
Test status
Simulation time 9537531723 ps
CPU time 1633.2 seconds
Started Jun 06 03:27:07 PM PDT 24
Finished Jun 06 03:54:23 PM PDT 24
Peak memory 288548 kb
Host smart-dc47772d-3ee9-48d8-8c38-f326c4618a2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277790307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2277790307
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1081683736
Short name T498
Test name
Test status
Simulation time 1334660344 ps
CPU time 98.29 seconds
Started Jun 06 03:27:06 PM PDT 24
Finished Jun 06 03:28:45 PM PDT 24
Peak memory 256968 kb
Host smart-daf2de42-2dc1-41b5-99f9-c01e65f9ec24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10816
83736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1081683736
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2838373714
Short name T430
Test name
Test status
Simulation time 1125205695 ps
CPU time 67.09 seconds
Started Jun 06 03:27:13 PM PDT 24
Finished Jun 06 03:28:21 PM PDT 24
Peak memory 249112 kb
Host smart-bbe50060-1ee6-45b9-b1fe-6b28bd668c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28383
73714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2838373714
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.814496342
Short name T705
Test name
Test status
Simulation time 80756392926 ps
CPU time 1178.92 seconds
Started Jun 06 03:27:13 PM PDT 24
Finished Jun 06 03:46:53 PM PDT 24
Peak memory 265188 kb
Host smart-478cde3d-209f-442b-85f4-3ced47d0d373
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814496342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.814496342
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.4291919403
Short name T556
Test name
Test status
Simulation time 19634689359 ps
CPU time 1151.31 seconds
Started Jun 06 03:27:05 PM PDT 24
Finished Jun 06 03:46:18 PM PDT 24
Peak memory 272616 kb
Host smart-66ee64b1-1106-43e3-8518-280308c11426
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291919403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.4291919403
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2846727511
Short name T304
Test name
Test status
Simulation time 10080932615 ps
CPU time 87.58 seconds
Started Jun 06 03:27:06 PM PDT 24
Finished Jun 06 03:28:35 PM PDT 24
Peak memory 248204 kb
Host smart-ca623d5d-0009-4d41-b8c2-1b5327bf0579
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846727511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2846727511
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1074560637
Short name T600
Test name
Test status
Simulation time 313894084 ps
CPU time 26.57 seconds
Started Jun 06 03:27:07 PM PDT 24
Finished Jun 06 03:27:36 PM PDT 24
Peak memory 255996 kb
Host smart-b2027afe-497d-4d8b-a52e-214c46f34365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10745
60637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1074560637
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3821781013
Short name T679
Test name
Test status
Simulation time 703079791 ps
CPU time 19.5 seconds
Started Jun 06 03:27:07 PM PDT 24
Finished Jun 06 03:27:28 PM PDT 24
Peak memory 248968 kb
Host smart-4caa33c3-63b1-46b5-b082-dfc7f6c94bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38217
81013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3821781013
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.3713027246
Short name T695
Test name
Test status
Simulation time 172600829 ps
CPU time 29.71 seconds
Started Jun 06 03:27:07 PM PDT 24
Finished Jun 06 03:27:39 PM PDT 24
Peak memory 256972 kb
Host smart-8d76386f-c1f9-4c11-8fd1-531fa7b0e0d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37130
27246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3713027246
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.3899933120
Short name T668
Test name
Test status
Simulation time 3542571423 ps
CPU time 21.82 seconds
Started Jun 06 03:27:17 PM PDT 24
Finished Jun 06 03:27:39 PM PDT 24
Peak memory 248820 kb
Host smart-976df4e6-ea0f-4172-9b6e-d340fa5d3ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38999
33120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3899933120
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.1243977718
Short name T650
Test name
Test status
Simulation time 43334349893 ps
CPU time 2688.39 seconds
Started Jun 06 03:27:22 PM PDT 24
Finished Jun 06 04:12:12 PM PDT 24
Peak memory 289340 kb
Host smart-02162e0f-1996-4a93-a88c-c5d485c164b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243977718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1243977718
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1849437725
Short name T673
Test name
Test status
Simulation time 811144225 ps
CPU time 8.63 seconds
Started Jun 06 03:27:19 PM PDT 24
Finished Jun 06 03:27:29 PM PDT 24
Peak memory 254308 kb
Host smart-17f5912b-cabb-4a26-892e-ea065bc4d5a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18494
37725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1849437725
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3287514735
Short name T362
Test name
Test status
Simulation time 346113382 ps
CPU time 30.29 seconds
Started Jun 06 03:27:18 PM PDT 24
Finished Jun 06 03:27:50 PM PDT 24
Peak memory 248784 kb
Host smart-15a22a17-f833-4647-bdc3-6153fe806c93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32875
14735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3287514735
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2773553445
Short name T318
Test name
Test status
Simulation time 77088886420 ps
CPU time 1396.92 seconds
Started Jun 06 03:27:29 PM PDT 24
Finished Jun 06 03:50:48 PM PDT 24
Peak memory 280940 kb
Host smart-0f21bed1-ce0d-4943-aef5-f323470425cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773553445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2773553445
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2705375369
Short name T416
Test name
Test status
Simulation time 579364104506 ps
CPU time 2701.37 seconds
Started Jun 06 03:27:28 PM PDT 24
Finished Jun 06 04:12:31 PM PDT 24
Peak memory 281612 kb
Host smart-d9a819bd-8545-482a-b0f7-08fbac22e5c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705375369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2705375369
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.3098798476
Short name T306
Test name
Test status
Simulation time 165051903094 ps
CPU time 528.25 seconds
Started Jun 06 03:27:19 PM PDT 24
Finished Jun 06 03:36:09 PM PDT 24
Peak memory 248792 kb
Host smart-338ecbbc-b045-47fc-b144-034d759ec272
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098798476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3098798476
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.2873428140
Short name T608
Test name
Test status
Simulation time 60182615 ps
CPU time 6.01 seconds
Started Jun 06 03:27:18 PM PDT 24
Finished Jun 06 03:27:26 PM PDT 24
Peak memory 248772 kb
Host smart-c9e0b198-34bf-4db7-91a8-fc353e3df6b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28734
28140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2873428140
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1485171148
Short name T116
Test name
Test status
Simulation time 386056188 ps
CPU time 20.03 seconds
Started Jun 06 03:27:20 PM PDT 24
Finished Jun 06 03:27:42 PM PDT 24
Peak memory 255256 kb
Host smart-5b4f7753-71ab-4ddf-a0c6-5e4cf1f494d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14851
71148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1485171148
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3560685755
Short name T114
Test name
Test status
Simulation time 278693090 ps
CPU time 43.2 seconds
Started Jun 06 03:27:19 PM PDT 24
Finished Jun 06 03:28:04 PM PDT 24
Peak memory 247592 kb
Host smart-1fc451f8-3be8-41a4-b849-64122d515ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35606
85755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3560685755
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.536091093
Short name T583
Test name
Test status
Simulation time 1077081365 ps
CPU time 42.24 seconds
Started Jun 06 03:27:06 PM PDT 24
Finished Jun 06 03:27:49 PM PDT 24
Peak memory 248780 kb
Host smart-d4a595d5-3944-4368-b470-27290cdf43c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53609
1093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.536091093
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.4205719534
Short name T46
Test name
Test status
Simulation time 16891610427 ps
CPU time 1616.21 seconds
Started Jun 06 03:27:30 PM PDT 24
Finished Jun 06 03:54:28 PM PDT 24
Peak memory 289712 kb
Host smart-3dee71bd-7346-4c89-a1a7-50b2cdd0bd58
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205719534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.4205719534
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.2685124437
Short name T52
Test name
Test status
Simulation time 500193602055 ps
CPU time 4922.27 seconds
Started Jun 06 03:27:28 PM PDT 24
Finished Jun 06 04:49:33 PM PDT 24
Peak memory 318860 kb
Host smart-1fc92f6d-1e6c-4b03-a8cd-5a3d82719e7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685124437 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.2685124437
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1420931919
Short name T197
Test name
Test status
Simulation time 27461843 ps
CPU time 2.56 seconds
Started Jun 06 03:14:57 PM PDT 24
Finished Jun 06 03:15:02 PM PDT 24
Peak memory 248952 kb
Host smart-9c678e27-f4e7-4a98-8f83-26037e81b3d6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1420931919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1420931919
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1453604765
Short name T353
Test name
Test status
Simulation time 166210912266 ps
CPU time 2282.65 seconds
Started Jun 06 03:14:57 PM PDT 24
Finished Jun 06 03:53:01 PM PDT 24
Peak memory 281620 kb
Host smart-5ec47e38-8dad-4e57-a2f5-27d7e1fdf4be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453604765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1453604765
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1365280291
Short name T359
Test name
Test status
Simulation time 162576936 ps
CPU time 10.68 seconds
Started Jun 06 03:14:56 PM PDT 24
Finished Jun 06 03:15:08 PM PDT 24
Peak memory 240600 kb
Host smart-3e3aae2d-cedd-4b2d-92f5-d2d7e07924d5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1365280291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1365280291
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.860111367
Short name T508
Test name
Test status
Simulation time 4431198896 ps
CPU time 213.99 seconds
Started Jun 06 03:14:44 PM PDT 24
Finished Jun 06 03:18:19 PM PDT 24
Peak memory 257040 kb
Host smart-ee455c18-b844-41f7-ad41-00a376b540f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86011
1367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.860111367
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.1164856800
Short name T574
Test name
Test status
Simulation time 1408426113 ps
CPU time 55.78 seconds
Started Jun 06 03:14:44 PM PDT 24
Finished Jun 06 03:15:42 PM PDT 24
Peak memory 248908 kb
Host smart-a3f0e7cb-d354-4fb3-aa1e-b55fc4e9ee86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11648
56800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1164856800
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1954887209
Short name T322
Test name
Test status
Simulation time 146261782427 ps
CPU time 3513.4 seconds
Started Jun 06 03:14:56 PM PDT 24
Finished Jun 06 04:13:31 PM PDT 24
Peak memory 289268 kb
Host smart-c9dd98d6-bd91-4778-b77c-880b41219f0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954887209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1954887209
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.4093624195
Short name T648
Test name
Test status
Simulation time 30860762201 ps
CPU time 2284.53 seconds
Started Jun 06 03:14:58 PM PDT 24
Finished Jun 06 03:53:05 PM PDT 24
Peak memory 281572 kb
Host smart-8c7592f9-1903-4dad-ad27-9b5832470c81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093624195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.4093624195
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1114935461
Short name T622
Test name
Test status
Simulation time 3206008206 ps
CPU time 65.68 seconds
Started Jun 06 03:14:58 PM PDT 24
Finished Jun 06 03:16:06 PM PDT 24
Peak memory 248164 kb
Host smart-67e027a7-0d22-484b-a530-6d6e3ab26111
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114935461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1114935461
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.261595945
Short name T438
Test name
Test status
Simulation time 1257073209 ps
CPU time 17.96 seconds
Started Jun 06 03:14:42 PM PDT 24
Finished Jun 06 03:15:01 PM PDT 24
Peak memory 249064 kb
Host smart-ddd68318-90e4-42c7-aa8b-8de45d3b1f2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26159
5945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.261595945
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2701273365
Short name T370
Test name
Test status
Simulation time 605717107 ps
CPU time 33.32 seconds
Started Jun 06 03:14:43 PM PDT 24
Finished Jun 06 03:15:18 PM PDT 24
Peak memory 248772 kb
Host smart-cdc2109c-33dd-48ee-bb21-73581e569e59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27012
73365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2701273365
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.770836692
Short name T268
Test name
Test status
Simulation time 1633581055 ps
CPU time 26.92 seconds
Started Jun 06 03:15:00 PM PDT 24
Finished Jun 06 03:15:29 PM PDT 24
Peak memory 255580 kb
Host smart-06a3a314-48db-4c16-b29d-7f2376fc694d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77083
6692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.770836692
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.920459573
Short name T349
Test name
Test status
Simulation time 139088413 ps
CPU time 12.74 seconds
Started Jun 06 03:14:28 PM PDT 24
Finished Jun 06 03:14:42 PM PDT 24
Peak memory 248828 kb
Host smart-580d5a79-c148-4221-8e4e-aac4231ac0b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92045
9573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.920459573
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3419514312
Short name T38
Test name
Test status
Simulation time 274533115 ps
CPU time 9.83 seconds
Started Jun 06 03:14:56 PM PDT 24
Finished Jun 06 03:15:06 PM PDT 24
Peak memory 253448 kb
Host smart-22126454-f009-4fd7-bcca-bbd5357f9d15
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419514312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3419514312
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.3641704160
Short name T208
Test name
Test status
Simulation time 57837512 ps
CPU time 2.45 seconds
Started Jun 06 03:15:31 PM PDT 24
Finished Jun 06 03:15:35 PM PDT 24
Peak memory 248960 kb
Host smart-f20c8b6a-eaee-4db3-8903-87962671a939
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3641704160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3641704160
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.981043824
Short name T387
Test name
Test status
Simulation time 64149923382 ps
CPU time 2131.66 seconds
Started Jun 06 03:15:18 PM PDT 24
Finished Jun 06 03:50:52 PM PDT 24
Peak memory 268464 kb
Host smart-e791ed3f-df36-4c7c-999e-779bad5b1132
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981043824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.981043824
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2236970801
Short name T686
Test name
Test status
Simulation time 239329820 ps
CPU time 8.74 seconds
Started Jun 06 03:15:17 PM PDT 24
Finished Jun 06 03:15:28 PM PDT 24
Peak memory 248728 kb
Host smart-d6b6de43-d9ce-44c5-af50-411a6c5e4d50
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2236970801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2236970801
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.652388079
Short name T593
Test name
Test status
Simulation time 1289426145 ps
CPU time 129.31 seconds
Started Jun 06 03:15:17 PM PDT 24
Finished Jun 06 03:17:28 PM PDT 24
Peak memory 256948 kb
Host smart-506b66fa-4526-442d-96e7-0fbe4667c826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65238
8079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.652388079
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1435541421
Short name T689
Test name
Test status
Simulation time 178545859 ps
CPU time 3.85 seconds
Started Jun 06 03:15:07 PM PDT 24
Finished Jun 06 03:15:12 PM PDT 24
Peak memory 240596 kb
Host smart-6db6d610-be8a-4b37-8731-c34b09dba739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14355
41421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1435541421
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.1658632268
Short name T491
Test name
Test status
Simulation time 176882824154 ps
CPU time 1505.36 seconds
Started Jun 06 03:15:19 PM PDT 24
Finished Jun 06 03:40:26 PM PDT 24
Peak memory 286852 kb
Host smart-ac3178e9-e532-44a1-86f8-02b2fccbe940
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658632268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.1658632268
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3020064547
Short name T224
Test name
Test status
Simulation time 93976173634 ps
CPU time 1782.36 seconds
Started Jun 06 03:15:18 PM PDT 24
Finished Jun 06 03:45:03 PM PDT 24
Peak memory 273440 kb
Host smart-bbe5e084-00da-48a0-b174-e70bf5027f02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020064547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3020064547
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3107010849
Short name T299
Test name
Test status
Simulation time 14275774826 ps
CPU time 143.6 seconds
Started Jun 06 03:15:16 PM PDT 24
Finished Jun 06 03:17:41 PM PDT 24
Peak memory 247892 kb
Host smart-ea79785b-f2c7-405f-8fb9-411d886251d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107010849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3107010849
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2294972936
Short name T414
Test name
Test status
Simulation time 997271025 ps
CPU time 59.28 seconds
Started Jun 06 03:15:04 PM PDT 24
Finished Jun 06 03:16:05 PM PDT 24
Peak memory 256284 kb
Host smart-4a275886-a5f1-43dd-a7ae-88d4131b75ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22949
72936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2294972936
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.956677067
Short name T187
Test name
Test status
Simulation time 245263800 ps
CPU time 27.83 seconds
Started Jun 06 03:15:06 PM PDT 24
Finished Jun 06 03:15:35 PM PDT 24
Peak memory 256588 kb
Host smart-e78009f1-61be-420a-a168-bd7271647707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95667
7067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.956677067
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.967868529
Short name T260
Test name
Test status
Simulation time 505571149 ps
CPU time 13.05 seconds
Started Jun 06 03:15:16 PM PDT 24
Finished Jun 06 03:15:31 PM PDT 24
Peak memory 248796 kb
Host smart-cbcd0877-6013-4cb7-91ce-f5d56f8e9214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96786
8529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.967868529
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.3845579558
Short name T27
Test name
Test status
Simulation time 3562081121 ps
CPU time 46.73 seconds
Started Jun 06 03:15:08 PM PDT 24
Finished Jun 06 03:15:55 PM PDT 24
Peak memory 248844 kb
Host smart-7af5ca7a-be01-4bbb-be6b-a0f1c7ac3798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38455
79558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3845579558
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.3428524316
Short name T182
Test name
Test status
Simulation time 65065979555 ps
CPU time 5198.73 seconds
Started Jun 06 03:15:30 PM PDT 24
Finished Jun 06 04:42:11 PM PDT 24
Peak memory 315508 kb
Host smart-0b92b407-3dbb-4ba8-95a1-feb60ea0b1c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428524316 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.3428524316
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.2626927099
Short name T211
Test name
Test status
Simulation time 43334303 ps
CPU time 3.76 seconds
Started Jun 06 03:15:50 PM PDT 24
Finished Jun 06 03:15:56 PM PDT 24
Peak memory 248940 kb
Host smart-761e3e5a-e1ff-4411-bb1e-8ad419f531ad
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2626927099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2626927099
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.4096227968
Short name T554
Test name
Test status
Simulation time 38176013194 ps
CPU time 2280.74 seconds
Started Jun 06 03:15:40 PM PDT 24
Finished Jun 06 03:53:42 PM PDT 24
Peak memory 288160 kb
Host smart-32939348-3daa-46d4-bb87-b8bb21a0c0e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096227968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.4096227968
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.1700633286
Short name T363
Test name
Test status
Simulation time 681021344 ps
CPU time 11.56 seconds
Started Jun 06 03:15:51 PM PDT 24
Finished Jun 06 03:16:04 PM PDT 24
Peak memory 240576 kb
Host smart-ce17639e-5d4a-43f3-9632-3e7d324bd447
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1700633286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1700633286
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.1386483367
Short name T478
Test name
Test status
Simulation time 1457186152 ps
CPU time 50.27 seconds
Started Jun 06 03:15:43 PM PDT 24
Finished Jun 06 03:16:35 PM PDT 24
Peak memory 248736 kb
Host smart-3208543a-8972-4f61-a3f7-637984230703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13864
83367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1386483367
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.3650949853
Short name T696
Test name
Test status
Simulation time 1642953539 ps
CPU time 49.47 seconds
Started Jun 06 03:15:41 PM PDT 24
Finished Jun 06 03:16:32 PM PDT 24
Peak memory 256596 kb
Host smart-ffeeebbd-ec6d-439b-98b1-eb339e95329a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36509
49853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.3650949853
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1281201469
Short name T466
Test name
Test status
Simulation time 38382840545 ps
CPU time 761.04 seconds
Started Jun 06 03:15:51 PM PDT 24
Finished Jun 06 03:28:34 PM PDT 24
Peak memory 272644 kb
Host smart-5b3ad537-2f7f-4ab6-8c36-7248a2ffa089
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281201469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1281201469
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.423272160
Short name T71
Test name
Test status
Simulation time 27937749265 ps
CPU time 1342.85 seconds
Started Jun 06 03:15:52 PM PDT 24
Finished Jun 06 03:38:17 PM PDT 24
Peak memory 289212 kb
Host smart-ec7141f0-44a6-4a66-846d-761089db63ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423272160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.423272160
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2142937701
Short name T685
Test name
Test status
Simulation time 78666886667 ps
CPU time 503.61 seconds
Started Jun 06 03:15:43 PM PDT 24
Finished Jun 06 03:24:08 PM PDT 24
Peak memory 253788 kb
Host smart-6d5131d5-c4e9-44fd-b430-21940b4cb2a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142937701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2142937701
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.1799556634
Short name T494
Test name
Test status
Simulation time 190882218 ps
CPU time 14.79 seconds
Started Jun 06 03:15:30 PM PDT 24
Finished Jun 06 03:15:46 PM PDT 24
Peak memory 248768 kb
Host smart-1ff31c48-2db5-4644-a20f-d17c45c89c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17995
56634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.1799556634
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.2441950830
Short name T592
Test name
Test status
Simulation time 556640672 ps
CPU time 18.63 seconds
Started Jun 06 03:15:31 PM PDT 24
Finished Jun 06 03:15:51 PM PDT 24
Peak memory 253880 kb
Host smart-7c42376e-f8e9-4a6c-b3f9-bd88f96eb5c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24419
50830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2441950830
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1096597743
Short name T492
Test name
Test status
Simulation time 116699417 ps
CPU time 13.95 seconds
Started Jun 06 03:15:42 PM PDT 24
Finished Jun 06 03:15:57 PM PDT 24
Peak memory 248760 kb
Host smart-795aca37-54f8-4d97-8d5a-4bb764c6ff3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10965
97743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1096597743
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2054942980
Short name T651
Test name
Test status
Simulation time 488813966 ps
CPU time 34.85 seconds
Started Jun 06 03:15:30 PM PDT 24
Finished Jun 06 03:16:06 PM PDT 24
Peak memory 248724 kb
Host smart-de116835-5bdf-41bd-923d-76f350603e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20549
42980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2054942980
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2125219772
Short name T86
Test name
Test status
Simulation time 48129603167 ps
CPU time 3125.42 seconds
Started Jun 06 03:15:54 PM PDT 24
Finished Jun 06 04:08:01 PM PDT 24
Peak memory 305676 kb
Host smart-df80b9a1-211d-40c8-ab4b-ee62329938dc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125219772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2125219772
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.1152670452
Short name T188
Test name
Test status
Simulation time 106384221580 ps
CPU time 6072.51 seconds
Started Jun 06 03:15:52 PM PDT 24
Finished Jun 06 04:57:07 PM PDT 24
Peak memory 349584 kb
Host smart-a1d72ea8-8dc6-4fb2-89fe-0d4aa1c58ac2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152670452 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.1152670452
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.3317481079
Short name T203
Test name
Test status
Simulation time 17853743 ps
CPU time 2.41 seconds
Started Jun 06 03:16:31 PM PDT 24
Finished Jun 06 03:16:35 PM PDT 24
Peak memory 248952 kb
Host smart-38b3ffb9-0487-437f-bb8f-e40bce1e17be
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3317481079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3317481079
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2535337937
Short name T100
Test name
Test status
Simulation time 69892833870 ps
CPU time 832.23 seconds
Started Jun 06 03:16:14 PM PDT 24
Finished Jun 06 03:30:07 PM PDT 24
Peak memory 265160 kb
Host smart-d2bad276-c029-43b8-b328-c716a05f02bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535337937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2535337937
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.750948664
Short name T464
Test name
Test status
Simulation time 1104797772 ps
CPU time 27.68 seconds
Started Jun 06 03:16:13 PM PDT 24
Finished Jun 06 03:16:42 PM PDT 24
Peak memory 240544 kb
Host smart-57dd72b5-76e3-458f-a6fc-53d1174bba92
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=750948664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.750948664
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.3868815877
Short name T471
Test name
Test status
Simulation time 18845898522 ps
CPU time 277.37 seconds
Started Jun 06 03:16:12 PM PDT 24
Finished Jun 06 03:20:51 PM PDT 24
Peak memory 256328 kb
Host smart-34459008-915e-417c-ae80-c14d169b23ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38688
15877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3868815877
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.2625194415
Short name T615
Test name
Test status
Simulation time 486783787 ps
CPU time 38.22 seconds
Started Jun 06 03:16:02 PM PDT 24
Finished Jun 06 03:16:42 PM PDT 24
Peak memory 248768 kb
Host smart-337a75d9-9752-4826-bb10-e70badcbcdb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26251
94415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2625194415
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2912960137
Short name T327
Test name
Test status
Simulation time 675572715173 ps
CPU time 2746.25 seconds
Started Jun 06 03:16:11 PM PDT 24
Finished Jun 06 04:01:59 PM PDT 24
Peak memory 289184 kb
Host smart-7ba7165c-b354-4f81-b4f7-05121f622d63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912960137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2912960137
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.4044953426
Short name T572
Test name
Test status
Simulation time 9649278627 ps
CPU time 694.23 seconds
Started Jun 06 03:16:13 PM PDT 24
Finished Jun 06 03:27:49 PM PDT 24
Peak memory 265128 kb
Host smart-d91c087c-46b7-483f-a731-442f5874f35c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044953426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.4044953426
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.24518829
Short name T439
Test name
Test status
Simulation time 13888799375 ps
CPU time 284.04 seconds
Started Jun 06 03:16:10 PM PDT 24
Finished Jun 06 03:20:55 PM PDT 24
Peak memory 248264 kb
Host smart-88554a09-c6e1-4c0a-b8fe-9986e395039a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24518829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.24518829
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3427315395
Short name T17
Test name
Test status
Simulation time 909350441 ps
CPU time 50.68 seconds
Started Jun 06 03:16:03 PM PDT 24
Finished Jun 06 03:16:56 PM PDT 24
Peak memory 255964 kb
Host smart-87a4b526-2c03-4247-9c4d-c041d8a08091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34273
15395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3427315395
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2401407124
Short name T220
Test name
Test status
Simulation time 315360205 ps
CPU time 9.87 seconds
Started Jun 06 03:16:03 PM PDT 24
Finished Jun 06 03:16:15 PM PDT 24
Peak memory 255920 kb
Host smart-882b74c5-69cb-4663-99d8-fedf985b8051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24014
07124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2401407124
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.1530790012
Short name T628
Test name
Test status
Simulation time 791943374 ps
CPU time 46.01 seconds
Started Jun 06 03:16:12 PM PDT 24
Finished Jun 06 03:16:59 PM PDT 24
Peak memory 255252 kb
Host smart-351c017d-dd1d-40c9-8aa0-506b9c38bfa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15307
90012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1530790012
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2331859983
Short name T580
Test name
Test status
Simulation time 87852677 ps
CPU time 8.03 seconds
Started Jun 06 03:16:03 PM PDT 24
Finished Jun 06 03:16:13 PM PDT 24
Peak memory 240688 kb
Host smart-3c1d3d70-8eec-471c-8630-d2f6a80851b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23318
59983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2331859983
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3805027641
Short name T99
Test name
Test status
Simulation time 293379855198 ps
CPU time 2254.34 seconds
Started Jun 06 03:16:31 PM PDT 24
Finished Jun 06 03:54:07 PM PDT 24
Peak memory 289624 kb
Host smart-482a574c-07f0-4581-82ec-06fbe9832f7f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805027641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3805027641
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.2996261596
Short name T441
Test name
Test status
Simulation time 163961358246 ps
CPU time 4615.61 seconds
Started Jun 06 03:16:31 PM PDT 24
Finished Jun 06 04:33:28 PM PDT 24
Peak memory 346704 kb
Host smart-4d84aedf-83f3-4617-9d49-63c528ce0188
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996261596 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.2996261596
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.43797219
Short name T201
Test name
Test status
Simulation time 232247761 ps
CPU time 4.31 seconds
Started Jun 06 03:17:03 PM PDT 24
Finished Jun 06 03:17:08 PM PDT 24
Peak memory 248888 kb
Host smart-33f1c021-a953-4656-8f73-6aee56d2f55d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=43797219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.43797219
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3237265957
Short name T675
Test name
Test status
Simulation time 26601008552 ps
CPU time 1678.44 seconds
Started Jun 06 03:16:46 PM PDT 24
Finished Jun 06 03:44:46 PM PDT 24
Peak memory 273428 kb
Host smart-290623cd-bc4d-4f0d-bfa2-9397d40ddb18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237265957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3237265957
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1485930310
Short name T493
Test name
Test status
Simulation time 3489235255 ps
CPU time 72.65 seconds
Started Jun 06 03:16:58 PM PDT 24
Finished Jun 06 03:18:12 PM PDT 24
Peak memory 248816 kb
Host smart-d475fde2-1f77-4d1f-8b25-30ac7bcd8528
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1485930310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1485930310
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.4187480216
Short name T42
Test name
Test status
Simulation time 1286683541 ps
CPU time 113.03 seconds
Started Jun 06 03:16:48 PM PDT 24
Finished Jun 06 03:18:43 PM PDT 24
Peak memory 249868 kb
Host smart-009676f8-5614-4232-aa0e-dc742b82f60e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41874
80216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.4187480216
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.58853286
Short name T380
Test name
Test status
Simulation time 1009608861 ps
CPU time 24.78 seconds
Started Jun 06 03:16:48 PM PDT 24
Finished Jun 06 03:17:15 PM PDT 24
Peak memory 255772 kb
Host smart-f3b0716e-9367-4077-8717-90d7419d71d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58853
286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.58853286
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.3944752738
Short name T691
Test name
Test status
Simulation time 66416219001 ps
CPU time 1764.17 seconds
Started Jun 06 03:16:59 PM PDT 24
Finished Jun 06 03:46:25 PM PDT 24
Peak memory 273376 kb
Host smart-caa93a32-cb91-43d6-a989-55c16454d85e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944752738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3944752738
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2600353151
Short name T495
Test name
Test status
Simulation time 129264062269 ps
CPU time 2000.81 seconds
Started Jun 06 03:16:58 PM PDT 24
Finished Jun 06 03:50:20 PM PDT 24
Peak memory 286864 kb
Host smart-7440d7a7-eb50-4fc2-858c-34c20c4bc58c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600353151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2600353151
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1040317733
Short name T5
Test name
Test status
Simulation time 50863745975 ps
CPU time 535.32 seconds
Started Jun 06 03:16:59 PM PDT 24
Finished Jun 06 03:25:56 PM PDT 24
Peak memory 247968 kb
Host smart-0b0e258f-6bd3-4ea5-bc50-886add13bc4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040317733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1040317733
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2731317784
Short name T690
Test name
Test status
Simulation time 653114432 ps
CPU time 19.98 seconds
Started Jun 06 03:16:48 PM PDT 24
Finished Jun 06 03:17:10 PM PDT 24
Peak memory 248792 kb
Host smart-4198fc96-6e72-415c-acd8-3d8efde7643d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27313
17784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2731317784
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1142684071
Short name T451
Test name
Test status
Simulation time 4096150376 ps
CPU time 62.79 seconds
Started Jun 06 03:16:48 PM PDT 24
Finished Jun 06 03:17:52 PM PDT 24
Peak memory 256420 kb
Host smart-4fe2132e-3892-4d85-8d89-34f36713fd62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11426
84071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1142684071
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.637989461
Short name T369
Test name
Test status
Simulation time 24563273 ps
CPU time 3.03 seconds
Started Jun 06 03:16:32 PM PDT 24
Finished Jun 06 03:16:36 PM PDT 24
Peak memory 240536 kb
Host smart-5e705139-1fa6-4063-908b-b783bcb6b6c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63798
9461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.637989461
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.3237824224
Short name T664
Test name
Test status
Simulation time 258458871989 ps
CPU time 3663 seconds
Started Jun 06 03:17:00 PM PDT 24
Finished Jun 06 04:18:05 PM PDT 24
Peak memory 306056 kb
Host smart-952cc68c-97f3-4b12-bb2e-ac89aa07d9c6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237824224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.3237824224
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.1634101072
Short name T190
Test name
Test status
Simulation time 454540218174 ps
CPU time 6053.37 seconds
Started Jun 06 03:16:59 PM PDT 24
Finished Jun 06 04:57:55 PM PDT 24
Peak memory 355092 kb
Host smart-b0866628-ecab-4c7f-b381-1ae2b515b6f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634101072 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.1634101072
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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