Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	70861	1			T5	1		T10	4		T74	52
class_i[0x1]	93219	1			T1	501		T9	2859		T70	1
class_i[0x2]	76303	1			T1	6		T10	1		T11	7
class_i[0x3]	48820	1			T4	13		T46	17		T27	63

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	71877	1			T1	146		T4	9		T9	737
alert[0x1]	69792	1			T1	146		T4	3		T5	1
alert[0x2]	73393	1			T1	79		T4	1		T9	707
alert[0x3]	74141	1			T1	136		T9	623		T10	1

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

288934

1

T1

507

T4

13

T9

2859

esc_ping_fail

269

1

T5

1

T10

5

T11

7

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	71805	1			T1	146		T4	9		T9	737
esc_integrity_fail	alert[0x1]	69717	1			T1	146		T4	3		T9	792
esc_integrity_fail	alert[0x2]	73324	1			T1	79		T4	1		T9	707
esc_integrity_fail	alert[0x3]	74088	1			T1	136		T9	623		T46	1
esc_ping_fail	alert[0x0]	72	1			T10	1		T11	1		T99	1
esc_ping_fail	alert[0x1]	75	1			T5	1		T10	2		T99	1
esc_ping_fail	alert[0x2]	69	1			T10	1		T11	3		T103	3
esc_ping_fail	alert[0x3]	53	1			T10	1		T11	3		T103	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	70789	1			T74	52		T27	1270		T26	3482
esc_integrity_fail	class_i[0x1]	93168	1			T1	501		T9	2859		T70	1
esc_integrity_fail	class_i[0x2]	76231	1			T1	6		T46	15		T99	5
esc_integrity_fail	class_i[0x3]	48746	1			T4	13		T46	17		T27	63
esc_ping_fail	class_i[0x0]	72	1			T5	1		T10	4		T99	2
esc_ping_fail	class_i[0x1]	51	1			T34	6		T320	3		T266	6
esc_ping_fail	class_i[0x2]	72	1			T10	1		T11	7		T215	2
esc_ping_fail	class_i[0x3]	74	1			T300	3		T303	11		T325	7