Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	681991999	0	0	628
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	681991999	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	681991999	681833798	0	0
tb.dut.CheckAccuCntDw	0	0	628	628	0	0
tb.dut.CheckEscCntDw	0	0	628	628	0	0
tb.dut.CheckNAlerts	0	0	628	628	0	0
tb.dut.CheckNClasses	0	0	628	628	0	0
tb.dut.CheckNEscSev	0	0	628	628	0	0
tb.dut.CrashdumpKnownO_A	0	0	681991999	681833798	0	0
tb.dut.EdnKnownO_A	0	0	681991999	681833798	0	0
tb.dut.EscPKnownO_A	0	0	681991999	681833798	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	681991999	70	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	681991999	70	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	681991999	70	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	681991999	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	681991999	70	0	0
tb.dut.IrqAKnownO_A	0	0	681991999	681833798	0	0
tb.dut.IrqBKnownO_A	0	0	681991999	681833798	0	0
tb.dut.IrqCKnownO_A	0	0	681991999	681833798	0	0
tb.dut.IrqDKnownO_A	0	0	681991999	681833798	0	0
tb.dut.TlAReadyKnownO_A	0	0	681991999	681833798	0	0
tb.dut.TlDValidKnownO_A	0	0	681991999	681833798	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	705366761	4091577	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	705366761	14678	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	705366761	14250	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	705366761	14339	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	705366761	15014	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	705366761	15643	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	705366761	15047	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	705366761	15583	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	705366761	15974	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	705366761	14673	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	705366761	14131	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	705366761	14769	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	705366761	14679	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	705366761	14136	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	705366761	14912	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	705366761	14693	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	705366761	14568	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	705366761	15074	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	705366761	15554	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	705366761	15699	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	705366761	15439	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	705366761	14555	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	705366761	14247	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	705366761	14910	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	705366761	14807	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	705366761	14368	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	705366761	14339	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	705366761	14273	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	705366761	14007	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	705366761	15838	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	705366761	15010	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	705366761	14301	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	705366761	16124	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	705366761	14123	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	705366761	14268	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	705366761	15635	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	705366761	14645	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	705366761	14614	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	705366761	15219	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	705366761	14069	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	705366761	15021	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	705366761	14138	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	705366761	14541	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	705366761	15490	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	705366761	15128	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	705366761	14709	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	705366761	14064	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	705366761	14484	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	705366761	14622	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	705366761	14126	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	705366761	14834	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	705366761	14753	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	705366761	14114	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	705366761	14394	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	705366761	15052	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	705366761	15644	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	705366761	14467	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	705366761	14917	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	705366761	14985	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	705366761	15468	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	705366761	14298	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	705366761	14801	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	705366761	14267	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	705366761	15024	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	705366761	14860	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	705366761	14981	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	705366761	13933	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	705366761	13946	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	705366761	14690	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	705366761	15497	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	705366761	28728	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	705366761	15292	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	705366761	14923	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	705366761	14966	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	705366761	14700	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	705366761	14969	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	705366761	14489	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	705366761	14792	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	705366761	14366	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	681991999	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	681991999	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	681991999	70	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	681991999	6660	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	681991999	231955	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	681991999	373815120	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	681991999	225	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	681991999	869	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	681991999	53	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	681991999	439	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	681625816	279437149	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	681991999	973	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	681991999	956	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	681991999	937	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	681991999	917	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	681991999	3271	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	681991999	288108	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	681991999	3140	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	681991999	75	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	681991999	1223	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	681991999	1013	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	681624179	681555560	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	628	628	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	681991999	681833798	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	681991999	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	681991999	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	681991999	70	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	681991999	2169	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	681991999	233154	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	681991999	373075466	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	681991999	217	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	681991999	504	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	681991999	20	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	681991999	216	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	681625816	291334634	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	681991999	583	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	681991999	579	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	681991999	569	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	681991999	554	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	681991999	1577	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	681991999	181820	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	681991999	1484	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	681991999	69	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	681991999	1349	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	681991999	1139	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	681624179	681555560	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	628	628	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	681991999	681833798	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	681991999	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	681991999	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	681991999	70	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	681991999	3835	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	681991999	253052	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	681991999	343162511	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	681991999	272	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	681991999	494	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	681991999	24	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	681991999	236	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	681625816	276618677	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	681991999	577	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	681991999	561	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	681991999	554	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	681991999	538	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	681991999	2073	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	681991999	172444	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	681991999	1978	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	681991999	70	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	681991999	1326	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	681991999	1116	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	681624179	681555560	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	628	628	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	681991999	681833798	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	681991999	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	681991999	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	681991999	70	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	681991999	2900	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	681991999	187670	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	681991999	378214327	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	681991999	268	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	681991999	522	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	681991999	27	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	681991999	252	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	681625816	277416951	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	681991999	600	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	681991999	591	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	681991999	581	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	681991999	570	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	681991999	2024	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	681991999	162581	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	681991999	1939	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	681991999	55	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	681991999	1304	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	681991999	1094	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	681624179	681555560	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	628	628	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	681991999	681833798	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	705366761	152790059	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	705366761	704708760	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	705366761	704708760	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	705366761	184321285	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	705366761	704708760	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	705366761	704708760	0	0
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tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A	0	0	833	833	0	0
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tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	833	833	0	0
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	833	833	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	833	833	0	0

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