Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.15	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	1	39	97.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	1	39	97.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	75	1			T21	1		T23	1		T74	2
class_index[0x1]	69	1			T1	1		T20	2		T22	1
class_index[0x2]	70	1			T74	2		T27	2		T30	2
class_index[0x3]	55	1			T70	3		T74	1		T27	2

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	108	1			T1	1		T20	2		T21	1
intr_timeout_cnt[1]	56	1			T70	3		T74	2		T27	1
intr_timeout_cnt[2]	16	1			T27	1		T79	1		T97	1
intr_timeout_cnt[3]	22	1			T74	1		T27	1		T26	1
intr_timeout_cnt[4]	17	1			T74	1		T30	1		T31	4
intr_timeout_cnt[5]	11	1			T48	1		T55	1		T19	1
intr_timeout_cnt[6]	7	1			T55	1		T109	1		T87	1
intr_timeout_cnt[7]	13	1			T74	1		T27	1		T50	1
intr_timeout_cnt[8]	8	1			T74	1		T77	1		T279	1
intr_timeout_cnt[9]	11	1			T27	1		T26	1		T30	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	1	39	97.50	1

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x3]]	[intr_timeout_cnt[8]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	30	1			T21	1		T23	1		T64	1
class_index[0x0]	intr_timeout_cnt[1]	17	1			T41	1		T79	1		T280	1
class_index[0x0]	intr_timeout_cnt[2]	5	1			T87	1		T281	1		T282	1
class_index[0x0]	intr_timeout_cnt[3]	5	1			T74	1		T30	1		T283	2
class_index[0x0]	intr_timeout_cnt[4]	2	1			T74	1		T58	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	3	1			T109	1		T273	1		T284	1
class_index[0x0]	intr_timeout_cnt[6]	3	1			T109	1		T285	1		T252	1
class_index[0x0]	intr_timeout_cnt[7]	3	1			T239	1		T286	1		T287	1
class_index[0x0]	intr_timeout_cnt[8]	3	1			T77	1		T109	1		T239	1
class_index[0x0]	intr_timeout_cnt[9]	4	1			T26	1		T48	1		T25	1
class_index[0x1]	intr_timeout_cnt[0]	29	1			T1	1		T20	2		T22	1
class_index[0x1]	intr_timeout_cnt[1]	13	1			T30	3		T106	1		T288	1
class_index[0x1]	intr_timeout_cnt[2]	1	1			T61	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[3]	3	1			T279	1		T285	1		T289	1
class_index[0x1]	intr_timeout_cnt[4]	8	1			T76	1		T290	1		T267	1
class_index[0x1]	intr_timeout_cnt[5]	3	1			T55	1		T109	1		T291	1
class_index[0x1]	intr_timeout_cnt[6]	1	1			T87	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	6	1			T74	1		T27	1		T292	1
class_index[0x1]	intr_timeout_cnt[8]	3	1			T74	1		T253	1		T293	1
class_index[0x1]	intr_timeout_cnt[9]	2	1			T78	1		T273	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	27	1			T74	1		T30	1		T54	1
class_index[0x2]	intr_timeout_cnt[1]	17	1			T74	1		T27	1		T52	3
class_index[0x2]	intr_timeout_cnt[2]	4	1			T79	1		T294	1		T295	1
class_index[0x2]	intr_timeout_cnt[3]	8	1			T27	1		T24	1		T296	1
class_index[0x2]	intr_timeout_cnt[4]	5	1			T31	4		T239	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	1	1			T48	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	1	1			T272	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	2	1			T87	1		T289	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	2	1			T279	1		T270	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	3	1			T30	1		T87	1		T61	1
class_index[0x3]	intr_timeout_cnt[0]	22	1			T64	1		T51	1		T25	1
class_index[0x3]	intr_timeout_cnt[1]	9	1			T70	3		T74	1		T106	1
class_index[0x3]	intr_timeout_cnt[2]	6	1			T27	1		T97	1		T55	1
class_index[0x3]	intr_timeout_cnt[3]	6	1			T26	1		T109	1		T254	1
class_index[0x3]	intr_timeout_cnt[4]	2	1			T30	1		T239	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	4	1			T19	1		T87	1		T297	1
class_index[0x3]	intr_timeout_cnt[6]	2	1			T55	1		T298	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	2	1			T50	1		T115	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	2	1			T27	1		T24	1		-	-