Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	382996	1			T1	576		T2	167		T4	1167
all_values[1]	382996	1			T1	576		T2	167		T4	1167
all_values[2]	382996	1			T1	576		T2	167		T4	1167
all_values[3]	382996	1			T1	576		T2	167		T4	1167

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

760768

1

T1

1208

T2

362

T4

2359

auto[1]

771216

1

T1

1096

T2

306

T4

2309

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

911009

1

T1

1368

T2

341

T4

2355

auto[1]

620975

1

T1

936

T2

327

T4

2313

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	109086	1			T1	158		T2	45		T4	298
all_values[0]	auto[0]	auto[1]	81532	1			T1	158		T2	45		T4	294
all_values[0]	auto[1]	auto[0]	110330	1			T1	130		T2	40		T4	288
all_values[0]	auto[1]	auto[1]	82048	1			T1	130		T2	37		T4	287
all_values[1]	auto[0]	auto[0]	114464	1			T1	183		T2	37		T4	310
all_values[1]	auto[0]	auto[1]	75641	1			T1	111		T2	37		T4	298
all_values[1]	auto[1]	auto[0]	116802	1			T1	174		T2	48		T4	284
all_values[1]	auto[1]	auto[1]	76089	1			T1	108		T2	45		T4	275
all_values[2]	auto[0]	auto[0]	114436	1			T1	184		T2	54		T4	296
all_values[2]	auto[0]	auto[1]	75754	1			T1	103		T2	53		T4	295
all_values[2]	auto[1]	auto[0]	116371	1			T1	177		T2	30		T4	288
all_values[2]	auto[1]	auto[1]	76435	1			T1	112		T2	30		T4	288
all_values[3]	auto[0]	auto[0]	113548	1			T1	193		T2	48		T4	287
all_values[3]	auto[0]	auto[1]	76307	1			T1	118		T2	43		T4	281
all_values[3]	auto[1]	auto[0]	115972	1			T1	169		T2	39		T4	304
all_values[3]	auto[1]	auto[1]	77169	1			T1	96		T2	37		T4	295