Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	382996	1			T1	576		T2	167		T4	1167
all_pins[1]	382996	1			T1	576		T2	167		T4	1167
all_pins[2]	382996	1			T1	576		T2	167		T4	1167
all_pins[3]	382996	1			T1	576		T2	167		T4	1167

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1220243	1			T1	1858		T2	519		T4	3523
values[0x1]	311741	1			T1	446		T2	149		T4	1145
transitions[0x0=>0x1]	206956	1			T1	295		T2	106		T4	718
transitions[0x1=>0x0]	207206	1			T1	295		T2	106		T4	719

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	300948	1			T1	446		T2	130		T4	880
all_pins[0]	values[0x1]	82048	1			T1	130		T2	37		T4	287
all_pins[0]	transitions[0x0=>0x1]	81309	1			T1	127		T2	37		T4	286
all_pins[0]	transitions[0x1=>0x0]	76680	1			T1	93		T2	37		T4	295
all_pins[1]	values[0x0]	306907	1			T1	468		T2	122		T4	892
all_pins[1]	values[0x1]	76089	1			T1	108		T2	45		T4	275
all_pins[1]	transitions[0x0=>0x1]	41369	1			T1	62		T2	28		T4	136
all_pins[1]	transitions[0x1=>0x0]	47328	1			T1	84		T2	20		T4	148
all_pins[2]	values[0x0]	306561	1			T1	464		T2	137		T4	879
all_pins[2]	values[0x1]	76435	1			T1	112		T2	30		T4	288
all_pins[2]	transitions[0x0=>0x1]	41874	1			T1	58		T2	14		T4	149
all_pins[2]	transitions[0x1=>0x0]	41528	1			T1	54		T2	29		T4	136
all_pins[3]	values[0x0]	305827	1			T1	480		T2	130		T4	872
all_pins[3]	values[0x1]	77169	1			T1	96		T2	37		T4	295
all_pins[3]	transitions[0x0=>0x1]	42404	1			T1	48		T2	27		T4	147
all_pins[3]	transitions[0x1=>0x0]	41670	1			T1	64		T2	20		T4	140