Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	99354	1			T4	410		T9	412		T6	321
accum_cnt_1000	256566	1			T1	354		T2	46		T4	635
accum_cnt_100	26559	1			T1	107		T2	16		T4	37
accum_cnt_50	80959	1			T1	244		T2	165		T4	931
accum_cnt_10	204116	1			T1	444		T2	19		T4	14
accum_cnt_0	415944	1			T1	475		T2	86		T4	903

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	283530	1			T1	406		T2	83		T4	901
class_index[0x1]	283530	1			T1	406		T2	83		T4	901
class_index[0x2]	283530	1			T1	406		T2	83		T4	901
class_index[0x3]	283530	1			T1	406		T2	83		T4	901

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	23828	1			T4	322		T9	82		T15	668
class_index[0x0]	accum_cnt_1000	69761	1			T1	151		T4	524		T9	661
class_index[0x0]	accum_cnt_100	7994	1			T1	51		T4	30		T9	40
class_index[0x0]	accum_cnt_50	20968	1			T1	34		T2	77		T4	19
class_index[0x0]	accum_cnt_10	53955	1			T1	41		T2	4		T4	5
class_index[0x0]	accum_cnt_0	95114	1			T1	129		T2	2		T4	1
class_index[0x1]	accum_cnt_2000	25248	1			T9	71		T46	210		T74	444
class_index[0x1]	accum_cnt_1000	61455	1			T9	79		T6	673		T43	1
class_index[0x1]	accum_cnt_100	6118	1			T9	3		T6	38		T43	15
class_index[0x1]	accum_cnt_50	19325	1			T1	152		T2	74		T4	894
class_index[0x1]	accum_cnt_10	55181	1			T1	127		T2	9		T4	6
class_index[0x1]	accum_cnt_0	101834	1			T1	127		T4	1		T5	8
class_index[0x2]	accum_cnt_2000	25665	1			T4	88		T9	177		T15	557
class_index[0x2]	accum_cnt_1000	62346	1			T1	93		T2	46		T4	111
class_index[0x2]	accum_cnt_100	6512	1			T1	32		T2	16		T4	7
class_index[0x2]	accum_cnt_50	17067	1			T1	28		T2	14		T4	18
class_index[0x2]	accum_cnt_10	49851	1			T1	137		T2	3		T4	3
class_index[0x2]	accum_cnt_0	107891	1			T1	116		T2	4		T5	8
class_index[0x3]	accum_cnt_2000	24613	1			T9	82		T6	321		T8	682
class_index[0x3]	accum_cnt_1000	63004	1			T1	110		T9	665		T6	393
class_index[0x3]	accum_cnt_100	5935	1			T1	24		T9	39		T6	21
class_index[0x3]	accum_cnt_50	23599	1			T1	30		T9	28		T6	16
class_index[0x3]	accum_cnt_10	45129	1			T1	139		T2	3		T9	8
class_index[0x3]	accum_cnt_0	111105	1			T1	103		T2	80		T4	901