Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	1862	1			T1	5		T5	1		T215	1
alert[0x1]	3680	1			T1	26		T4	659		T9	112
alert[0x2]	4469	1			T46	520		T74	57		T26	3
alert[0x3]	3821	1			T1	3		T4	37		T9	243
alert[0x4]	6977	1			T9	1966		T11	2		T46	315
alert[0x5]	2744	1			T103	1		T215	1		T30	94
alert[0x6]	9530	1			T4	8		T11	1		T74	129
alert[0x7]	4741	1			T27	21		T30	431		T34	1
alert[0x8]	8522	1			T9	6		T27	44		T116	143
alert[0x9]	4324	1			T4	4		T9	42		T103	2
alert[0xa]	9604	1			T9	15		T46	205		T74	544
alert[0xb]	7837	1			T215	1		T300	1		T24	59
alert[0xc]	4234	1			T15	10		T46	258		T27	616
alert[0xd]	6906	1			T4	447		T74	128		T27	10
alert[0xe]	2680	1			T9	497		T103	1		T48	1
alert[0xf]	2294	1			T1	19		T4	18		T9	23
alert[0x10]	2782	1			T4	5		T9	17		T74	243
alert[0x11]	5455	1			T1	1		T4	29		T10	1
alert[0x12]	10134	1			T1	6		T10	1		T215	1
alert[0x13]	7022	1			T4	172		T74	99		T215	1
alert[0x14]	17481	1			T4	409		T74	1		T27	19
alert[0x15]	8549	1			T1	14		T4	21		T5	1
alert[0x16]	5042	1			T1	4		T5	1		T11	1
alert[0x17]	7411	1			T11	1		T46	32		T103	1
alert[0x18]	5784	1			T27	34		T103	1		T26	4
alert[0x19]	4078	1			T1	1		T4	13		T46	32
alert[0x1a]	4577	1			T27	6		T26	89		T215	1
alert[0x1b]	2530	1			T11	1		T74	42		T27	27
alert[0x1c]	13181	1			T4	24		T11	1		T74	29
alert[0x1d]	4687	1			T46	26		T74	1833		T27	51
alert[0x1e]	8430	1			T1	15		T4	128		T9	49
alert[0x1f]	6066	1			T4	13		T9	20		T10	1
alert[0x20]	14863	1			T10	1		T74	3		T103	1
alert[0x21]	8119	1			T4	7		T11	1		T27	75
alert[0x22]	5488	1			T4	332		T9	364		T27	347
alert[0x23]	2938	1			T4	725		T9	352		T11	1
alert[0x24]	3085	1			T74	85		T27	21		T103	1
alert[0x25]	3547	1			T4	27		T10	1		T215	1
alert[0x26]	6119	1			T4	276		T46	45		T30	29
alert[0x27]	6727	1			T4	1140		T70	33		T215	1
alert[0x28]	7754	1			T4	31		T5	1		T99	1
alert[0x29]	5875	1			T4	380		T46	832		T27	134
alert[0x2a]	3047	1			T4	11		T9	226		T27	4
alert[0x2b]	2171	1			T116	54		T42	184		T24	302
alert[0x2c]	22461	1			T11	1		T99	1		T103	1
alert[0x2d]	9602	1			T4	199		T74	37		T26	43
alert[0x2e]	5712	1			T9	29		T74	12		T99	1
alert[0x2f]	8165	1			T4	23		T74	57		T27	548
alert[0x30]	5019	1			T4	117		T9	1115		T70	15
alert[0x31]	2595	1			T4	199		T9	13		T30	105
alert[0x32]	1726	1			T15	2		T46	118		T74	20
alert[0x33]	6856	1			T4	7		T5	1		T10	1
alert[0x34]	8459	1			T4	26		T9	488		T215	1
alert[0x35]	2119	1			T1	2		T11	1		T46	18
alert[0x36]	7620	1			T4	3841		T74	3		T103	1
alert[0x37]	8319	1			T4	745		T10	1		T11	1
alert[0x38]	6970	1			T9	1427		T11	1		T26	115
alert[0x39]	3869	1			T9	12		T27	1462		T30	439
alert[0x3a]	5020	1			T72	15		T74	181		T99	1
alert[0x3b]	6472	1			T1	9		T9	2781		T10	1
alert[0x3c]	8185	1			T9	2		T46	31		T27	19
alert[0x3d]	6245	1			T9	28		T11	1		T46	2192
alert[0x3e]	7217	1			T26	11		T301	10		T84	223
alert[0x3f]	5321	1			T74	74		T26	31		T31	4
alert[0x40]	4755	1			T4	4		T44	3		T27	20

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	72358	1			T4	7		T5	5		T10	10
class_i[0x1]	80135	1			T4	1		T9	9827		T46	4797
class_i[0x2]	141627	1			T4	10005		T11	1		T46	13
class_i[0x3]	115754	1			T1	105		T4	64		T11	1

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

409276

1

T1

105

T4

10077

T9

9827

alert_ping_fail

598

1

T5

5

T10

10

T11

16

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	1856	1			T1	5		T31	3		T52	189
alert_integrity_fail	alert[0x1]	3674	1			T1	26		T4	659		T9	112
alert_integrity_fail	alert[0x2]	4464	1			T46	520		T74	57		T26	3
alert_integrity_fail	alert[0x3]	3814	1			T1	3		T4	37		T9	243
alert_integrity_fail	alert[0x4]	6961	1			T9	1966		T46	315		T74	12
alert_integrity_fail	alert[0x5]	2731	1			T30	94		T31	1		T116	21
alert_integrity_fail	alert[0x6]	9522	1			T4	8		T74	129		T26	1052
alert_integrity_fail	alert[0x7]	4729	1			T27	21		T30	431		T51	27
alert_integrity_fail	alert[0x8]	8512	1			T9	6		T27	44		T116	143
alert_integrity_fail	alert[0x9]	4316	1			T4	4		T9	42		T30	486
alert_integrity_fail	alert[0xa]	9597	1			T9	15		T46	205		T74	544
alert_integrity_fail	alert[0xb]	7822	1			T24	59		T274	30		T54	23
alert_integrity_fail	alert[0xc]	4224	1			T15	10		T46	258		T27	616
alert_integrity_fail	alert[0xd]	6900	1			T4	447		T74	128		T27	10
alert_integrity_fail	alert[0xe]	2671	1			T9	497		T48	1		T274	13
alert_integrity_fail	alert[0xf]	2288	1			T1	19		T4	18		T9	23
alert_integrity_fail	alert[0x10]	2776	1			T4	5		T9	17		T74	243
alert_integrity_fail	alert[0x11]	5448	1			T1	1		T4	29		T27	6
alert_integrity_fail	alert[0x12]	10125	1			T1	6		T30	116		T76	10
alert_integrity_fail	alert[0x13]	7002	1			T4	172		T74	99		T30	513
alert_integrity_fail	alert[0x14]	17476	1			T4	409		T74	1		T27	19
alert_integrity_fail	alert[0x15]	8537	1			T1	14		T4	21		T74	327
alert_integrity_fail	alert[0x16]	5027	1			T1	4		T27	76		T30	509
alert_integrity_fail	alert[0x17]	7405	1			T46	32		T26	50		T24	10
alert_integrity_fail	alert[0x18]	5772	1			T27	34		T26	4		T116	12
alert_integrity_fail	alert[0x19]	4070	1			T1	1		T4	13		T46	32
alert_integrity_fail	alert[0x1a]	4563	1			T27	6		T26	89		T116	612
alert_integrity_fail	alert[0x1b]	2515	1			T74	42		T27	27		T30	191
alert_integrity_fail	alert[0x1c]	13172	1			T4	24		T74	29		T26	87
alert_integrity_fail	alert[0x1d]	4675	1			T46	26		T74	1833		T27	51
alert_integrity_fail	alert[0x1e]	8426	1			T1	15		T4	128		T9	49
alert_integrity_fail	alert[0x1f]	6058	1			T4	13		T9	20		T15	2
alert_integrity_fail	alert[0x20]	14853	1			T74	3		T116	145		T42	572
alert_integrity_fail	alert[0x21]	8110	1			T4	7		T27	75		T26	216
alert_integrity_fail	alert[0x22]	5480	1			T4	332		T9	364		T27	347
alert_integrity_fail	alert[0x23]	2933	1			T4	725		T9	352		T30	8
alert_integrity_fail	alert[0x24]	3076	1			T74	85		T27	21		T26	13
alert_integrity_fail	alert[0x25]	3540	1			T4	27		T30	218		T116	120
alert_integrity_fail	alert[0x26]	6109	1			T4	276		T46	45		T30	29
alert_integrity_fail	alert[0x27]	6715	1			T4	1140		T70	33		T48	4
alert_integrity_fail	alert[0x28]	7743	1			T4	31		T116	60		T48	2
alert_integrity_fail	alert[0x29]	5863	1			T4	380		T46	832		T27	134
alert_integrity_fail	alert[0x2a]	3038	1			T4	11		T9	226		T27	4
alert_integrity_fail	alert[0x2b]	2162	1			T116	54		T42	184		T24	302
alert_integrity_fail	alert[0x2c]	22444	1			T48	1		T76	4		T42	75
alert_integrity_fail	alert[0x2d]	9591	1			T4	199		T74	37		T26	43
alert_integrity_fail	alert[0x2e]	5704	1			T9	29		T74	12		T30	54
alert_integrity_fail	alert[0x2f]	8148	1			T4	23		T74	57		T27	548
alert_integrity_fail	alert[0x30]	5008	1			T4	117		T9	1115		T70	15
alert_integrity_fail	alert[0x31]	2584	1			T4	199		T9	13		T30	105
alert_integrity_fail	alert[0x32]	1715	1			T15	2		T46	118		T74	20
alert_integrity_fail	alert[0x33]	6850	1			T4	7		T46	105		T27	61
alert_integrity_fail	alert[0x34]	8451	1			T4	26		T9	488		T30	270
alert_integrity_fail	alert[0x35]	2113	1			T1	2		T46	18		T30	94
alert_integrity_fail	alert[0x36]	7612	1			T4	3841		T74	3		T30	102
alert_integrity_fail	alert[0x37]	8310	1			T4	745		T46	127		T30	2334
alert_integrity_fail	alert[0x38]	6957	1			T9	1427		T26	115		T116	7
alert_integrity_fail	alert[0x39]	3863	1			T9	12		T27	1462		T30	439
alert_integrity_fail	alert[0x3a]	5013	1			T72	15		T74	181		T26	254
alert_integrity_fail	alert[0x3b]	6467	1			T1	9		T9	2781		T27	150
alert_integrity_fail	alert[0x3c]	8179	1			T9	2		T46	31		T27	19
alert_integrity_fail	alert[0x3d]	6237	1			T9	28		T46	2192		T27	155
alert_integrity_fail	alert[0x3e]	7210	1			T26	11		T301	10		T84	223
alert_integrity_fail	alert[0x3f]	5320	1			T74	74		T26	31		T31	4
alert_integrity_fail	alert[0x40]	4750	1			T4	4		T44	3		T27	20
alert_ping_fail	alert[0x0]	6	1			T5	1		T215	1		T302	1
alert_ping_fail	alert[0x1]	6	1			T10	1		T303	1		T266	2
alert_ping_fail	alert[0x2]	5	1			T303	1		T304	1		T305	1
alert_ping_fail	alert[0x3]	7	1			T306	1		T307	1		T308	1
alert_ping_fail	alert[0x4]	16	1			T11	2		T300	1		T303	1
alert_ping_fail	alert[0x5]	13	1			T103	1		T215	1		T299	1
alert_ping_fail	alert[0x6]	8	1			T11	1		T303	1		T309	1
alert_ping_fail	alert[0x7]	12	1			T34	1		T310	1		T311	1
alert_ping_fail	alert[0x8]	10	1			T36	2		T312	1		T313	1
alert_ping_fail	alert[0x9]	8	1			T103	2		T314	1		T34	1
alert_ping_fail	alert[0xa]	7	1			T306	1		T304	1		T302	1
alert_ping_fail	alert[0xb]	15	1			T215	1		T300	1		T190	1
alert_ping_fail	alert[0xc]	10	1			T215	1		T303	1		T190	1
alert_ping_fail	alert[0xd]	6	1			T303	1		T315	1		T316	1
alert_ping_fail	alert[0xe]	9	1			T103	1		T314	1		T317	1
alert_ping_fail	alert[0xf]	6	1			T308	1		T318	1		T319	1
alert_ping_fail	alert[0x10]	6	1			T300	1		T190	1		T312	1
alert_ping_fail	alert[0x11]	7	1			T10	1		T103	1		T320	1
alert_ping_fail	alert[0x12]	9	1			T10	1		T215	1		T303	1
alert_ping_fail	alert[0x13]	20	1			T215	1		T299	2		T317	1
alert_ping_fail	alert[0x14]	5	1			T103	1		T303	1		T321	1
alert_ping_fail	alert[0x15]	12	1			T5	1		T299	1		T36	1
alert_ping_fail	alert[0x16]	15	1			T5	1		T11	1		T40	1
alert_ping_fail	alert[0x17]	6	1			T11	1		T103	1		T266	1
alert_ping_fail	alert[0x18]	12	1			T103	1		T215	2		T314	1
alert_ping_fail	alert[0x19]	8	1			T306	1		T312	1		T322	1
alert_ping_fail	alert[0x1a]	14	1			T215	1		T312	1		T315	1
alert_ping_fail	alert[0x1b]	15	1			T11	1		T323	3		T317	1
alert_ping_fail	alert[0x1c]	9	1			T11	1		T99	1		T314	1
alert_ping_fail	alert[0x1d]	12	1			T34	1		T306	1		T313	1
alert_ping_fail	alert[0x1e]	4	1			T10	1		T103	1		T306	1
alert_ping_fail	alert[0x1f]	8	1			T10	1		T11	1		T62	1
alert_ping_fail	alert[0x20]	10	1			T10	1		T103	1		T34	1
alert_ping_fail	alert[0x21]	9	1			T11	1		T103	1		T34	1
alert_ping_fail	alert[0x22]	8	1			T103	1		T314	1		T324	1
alert_ping_fail	alert[0x23]	5	1			T11	1		T99	1		T307	1
alert_ping_fail	alert[0x24]	9	1			T103	1		T34	1		T306	1
alert_ping_fail	alert[0x25]	7	1			T10	1		T215	1		T325	1
alert_ping_fail	alert[0x26]	10	1			T300	1		T303	1		T306	1
alert_ping_fail	alert[0x27]	12	1			T215	1		T303	1		T312	1
alert_ping_fail	alert[0x28]	11	1			T5	1		T99	1		T215	1
alert_ping_fail	alert[0x29]	12	1			T215	1		T266	1		T313	1
alert_ping_fail	alert[0x2a]	9	1			T103	1		T266	2		T313	1
alert_ping_fail	alert[0x2b]	9	1			T266	3		T325	1		T326	1
alert_ping_fail	alert[0x2c]	17	1			T11	1		T99	1		T103	1
alert_ping_fail	alert[0x2d]	11	1			T314	2		T327	2		T328	1
alert_ping_fail	alert[0x2e]	8	1			T99	1		T215	1		T329	1
alert_ping_fail	alert[0x2f]	17	1			T215	1		T314	2		T312	1
alert_ping_fail	alert[0x30]	11	1			T99	1		T103	1		T215	1
alert_ping_fail	alert[0x31]	11	1			T300	1		T303	1		T320	1
alert_ping_fail	alert[0x32]	11	1			T215	1		T34	1		T190	1
alert_ping_fail	alert[0x33]	6	1			T5	1		T10	1		T324	1
alert_ping_fail	alert[0x34]	8	1			T215	1		T322	1		T309	1
alert_ping_fail	alert[0x35]	6	1			T11	1		T103	1		T306	1
alert_ping_fail	alert[0x36]	8	1			T103	1		T215	1		T313	1
alert_ping_fail	alert[0x37]	9	1			T10	1		T11	1		T34	1
alert_ping_fail	alert[0x38]	13	1			T11	1		T314	1		T317	1
alert_ping_fail	alert[0x39]	6	1			T324	1		T312	1		T313	1
alert_ping_fail	alert[0x3a]	7	1			T99	1		T306	1		T304	1
alert_ping_fail	alert[0x3b]	5	1			T10	1		T11	1		T306	1
alert_ping_fail	alert[0x3c]	6	1			T304	1		T326	1		T309	1
alert_ping_fail	alert[0x3d]	8	1			T11	1		T103	1		T317	1
alert_ping_fail	alert[0x3e]	7	1			T315	1		T322	1		T325	1
alert_ping_fail	alert[0x3f]	1	1			T305	1		-	-		-	-
alert_ping_fail	alert[0x40]	5	1			T215	1		T304	1		T316	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	72145	1			T4	7		T44	3		T70	48
alert_integrity_fail	class_i[0x1]	80055	1			T4	1		T9	9827		T46	4797
alert_integrity_fail	class_i[0x2]	141474	1			T4	10005		T46	13		T74	3
alert_integrity_fail	class_i[0x3]	115602	1			T1	105		T4	64		T15	14
alert_ping_fail	class_i[0x0]	213	1			T5	5		T10	10		T11	14
alert_ping_fail	class_i[0x1]	80	1			T99	3		T34	1		T300	1
alert_ping_fail	class_i[0x2]	153	1			T11	1		T99	2		T103	13
alert_ping_fail	class_i[0x3]	152	1			T11	1		T103	2		T62	1