Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.67 99.99 98.69 100.00 100.00 100.00 99.38 99.64


Total test records in report: 833
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T772 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3892677317 Jun 07 07:42:31 PM PDT 24 Jun 07 07:42:34 PM PDT 24 9919482 ps
T773 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3398776342 Jun 07 07:41:33 PM PDT 24 Jun 07 07:41:56 PM PDT 24 601121988 ps
T145 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1699762556 Jun 07 07:41:41 PM PDT 24 Jun 07 07:46:54 PM PDT 24 31199094476 ps
T774 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2927974716 Jun 07 07:41:16 PM PDT 24 Jun 07 07:41:33 PM PDT 24 490430435 ps
T775 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3356211811 Jun 07 07:41:34 PM PDT 24 Jun 07 07:42:14 PM PDT 24 1264006161 ps
T776 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1898676036 Jun 07 07:41:48 PM PDT 24 Jun 07 07:42:29 PM PDT 24 1884058085 ps
T169 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2936039314 Jun 07 07:41:38 PM PDT 24 Jun 07 07:42:01 PM PDT 24 162085945 ps
T777 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.336301480 Jun 07 07:41:34 PM PDT 24 Jun 07 07:41:36 PM PDT 24 14171519 ps
T778 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2078650963 Jun 07 07:41:42 PM PDT 24 Jun 07 07:41:49 PM PDT 24 78812357 ps
T151 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.798455209 Jun 07 07:42:08 PM PDT 24 Jun 07 08:01:14 PM PDT 24 16063447755 ps
T152 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3524767229 Jun 07 07:41:57 PM PDT 24 Jun 07 07:46:04 PM PDT 24 6275419938 ps
T779 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3444236406 Jun 07 07:41:42 PM PDT 24 Jun 07 07:41:44 PM PDT 24 11528632 ps
T780 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3822714521 Jun 07 07:42:22 PM PDT 24 Jun 07 07:42:26 PM PDT 24 15487998 ps
T147 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1232630014 Jun 07 07:41:41 PM PDT 24 Jun 07 07:44:17 PM PDT 24 23808028730 ps
T781 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1300204477 Jun 07 07:42:22 PM PDT 24 Jun 07 07:42:26 PM PDT 24 25343752 ps
T782 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3227992117 Jun 07 07:41:40 PM PDT 24 Jun 07 07:41:45 PM PDT 24 171477898 ps
T783 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1072646306 Jun 07 07:41:40 PM PDT 24 Jun 07 07:41:50 PM PDT 24 597188183 ps
T784 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.861914234 Jun 07 07:42:22 PM PDT 24 Jun 07 07:42:25 PM PDT 24 9835537 ps
T166 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.388537412 Jun 07 07:41:32 PM PDT 24 Jun 07 07:41:37 PM PDT 24 110963613 ps
T785 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.349957624 Jun 07 07:42:13 PM PDT 24 Jun 07 07:42:16 PM PDT 24 10701181 ps
T786 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2767126380 Jun 07 07:41:09 PM PDT 24 Jun 07 07:43:05 PM PDT 24 3553257258 ps
T787 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1892894510 Jun 07 07:42:22 PM PDT 24 Jun 07 07:42:25 PM PDT 24 15170062 ps
T788 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.628794129 Jun 07 07:42:13 PM PDT 24 Jun 07 07:42:16 PM PDT 24 13064001 ps
T789 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.800564615 Jun 07 07:42:13 PM PDT 24 Jun 07 07:42:36 PM PDT 24 612714705 ps
T790 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3562941075 Jun 07 07:41:07 PM PDT 24 Jun 07 07:41:14 PM PDT 24 358795270 ps
T172 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1662927248 Jun 07 07:41:20 PM PDT 24 Jun 07 07:41:23 PM PDT 24 23160151 ps
T791 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.914863253 Jun 07 07:42:06 PM PDT 24 Jun 07 07:42:08 PM PDT 24 6448528 ps
T792 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1308823331 Jun 07 07:41:09 PM PDT 24 Jun 07 07:41:20 PM PDT 24 298559421 ps
T793 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3162791155 Jun 07 07:42:22 PM PDT 24 Jun 07 07:42:25 PM PDT 24 7242818 ps
T167 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2336162061 Jun 07 07:41:17 PM PDT 24 Jun 07 07:41:23 PM PDT 24 108760154 ps
T794 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2336284910 Jun 07 07:41:51 PM PDT 24 Jun 07 07:42:04 PM PDT 24 1284770951 ps
T795 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3622788878 Jun 07 07:42:14 PM PDT 24 Jun 07 07:42:16 PM PDT 24 21781500 ps
T796 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1482961857 Jun 07 07:41:26 PM PDT 24 Jun 07 07:41:33 PM PDT 24 266245155 ps
T356 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2884353960 Jun 07 07:41:33 PM PDT 24 Jun 07 07:50:21 PM PDT 24 53796375105 ps
T797 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3046774066 Jun 07 07:41:38 PM PDT 24 Jun 07 07:41:45 PM PDT 24 118578462 ps
T798 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.4208535300 Jun 07 07:41:17 PM PDT 24 Jun 07 07:41:26 PM PDT 24 38963620 ps
T799 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1196974193 Jun 07 07:42:07 PM PDT 24 Jun 07 07:42:18 PM PDT 24 96283040 ps
T800 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3133729791 Jun 07 07:42:11 PM PDT 24 Jun 07 07:42:13 PM PDT 24 8937987 ps
T801 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2067209665 Jun 07 07:41:15 PM PDT 24 Jun 07 07:41:18 PM PDT 24 6714220 ps
T154 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.4182788970 Jun 07 07:41:12 PM PDT 24 Jun 07 07:42:46 PM PDT 24 1083531274 ps
T802 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1493029126 Jun 07 07:42:17 PM PDT 24 Jun 07 07:42:19 PM PDT 24 14116182 ps
T803 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.1830216733 Jun 07 07:42:05 PM PDT 24 Jun 07 07:42:20 PM PDT 24 4295203050 ps
T804 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.320617324 Jun 07 07:42:16 PM PDT 24 Jun 07 07:42:19 PM PDT 24 10297256 ps
T805 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1966309867 Jun 07 07:42:21 PM PDT 24 Jun 07 07:42:23 PM PDT 24 10139233 ps
T178 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3625955505 Jun 07 07:42:14 PM PDT 24 Jun 07 07:43:20 PM PDT 24 8848524083 ps
T806 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.4068271083 Jun 07 07:41:41 PM PDT 24 Jun 07 07:41:45 PM PDT 24 66316447 ps
T807 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3269453172 Jun 07 07:41:39 PM PDT 24 Jun 07 07:41:45 PM PDT 24 342574162 ps
T808 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2208835774 Jun 07 07:41:24 PM PDT 24 Jun 07 07:41:39 PM PDT 24 372525646 ps
T809 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3991311891 Jun 07 07:42:29 PM PDT 24 Jun 07 07:42:32 PM PDT 24 8803290 ps
T810 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3230382617 Jun 07 07:42:15 PM PDT 24 Jun 07 07:42:17 PM PDT 24 13387369 ps
T811 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1233847911 Jun 07 07:41:57 PM PDT 24 Jun 07 07:42:00 PM PDT 24 6476650 ps
T812 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2642223871 Jun 07 07:41:39 PM PDT 24 Jun 07 07:41:53 PM PDT 24 169656212 ps
T813 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1928198473 Jun 07 07:42:21 PM PDT 24 Jun 07 07:42:23 PM PDT 24 21651064 ps
T814 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.766118602 Jun 07 07:42:15 PM PDT 24 Jun 07 07:42:25 PM PDT 24 258318676 ps
T139 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.4004167226 Jun 07 07:41:37 PM PDT 24 Jun 07 07:44:57 PM PDT 24 1585747762 ps
T815 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3551196871 Jun 07 07:41:49 PM PDT 24 Jun 07 07:42:14 PM PDT 24 340597114 ps
T816 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.178825499 Jun 07 07:41:18 PM PDT 24 Jun 07 07:41:47 PM PDT 24 174377395 ps
T148 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3947226403 Jun 07 07:41:16 PM PDT 24 Jun 07 07:50:50 PM PDT 24 8557896985 ps
T153 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2032853547 Jun 07 07:41:49 PM PDT 24 Jun 07 07:51:25 PM PDT 24 22855929147 ps
T165 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2343468134 Jun 07 07:41:10 PM PDT 24 Jun 07 07:41:35 PM PDT 24 605488969 ps
T355 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1178163549 Jun 07 07:42:00 PM PDT 24 Jun 07 07:51:25 PM PDT 24 12516590706 ps
T817 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1706596849 Jun 07 07:41:16 PM PDT 24 Jun 07 07:41:24 PM PDT 24 152800404 ps
T157 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3948832611 Jun 07 07:41:28 PM PDT 24 Jun 07 07:46:57 PM PDT 24 9537263231 ps
T818 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.220522530 Jun 07 07:41:26 PM PDT 24 Jun 07 07:41:29 PM PDT 24 11082560 ps
T819 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2301727973 Jun 07 07:41:54 PM PDT 24 Jun 07 07:42:14 PM PDT 24 1003411959 ps
T156 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1645117797 Jun 07 07:41:17 PM PDT 24 Jun 07 07:43:58 PM PDT 24 4729570539 ps
T820 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.315277908 Jun 07 07:41:40 PM PDT 24 Jun 07 07:41:43 PM PDT 24 15472425 ps
T821 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2084201022 Jun 07 07:41:26 PM PDT 24 Jun 07 07:41:40 PM PDT 24 89536548 ps
T150 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2058445563 Jun 07 07:41:50 PM PDT 24 Jun 07 07:57:17 PM PDT 24 48829234489 ps
T822 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3775312857 Jun 07 07:41:10 PM PDT 24 Jun 07 07:41:13 PM PDT 24 9560262 ps
T823 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2792669807 Jun 07 07:42:09 PM PDT 24 Jun 07 07:42:29 PM PDT 24 709866415 ps
T824 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2786617892 Jun 07 07:41:38 PM PDT 24 Jun 07 07:41:47 PM PDT 24 160407934 ps
T825 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1072003351 Jun 07 07:41:23 PM PDT 24 Jun 07 07:43:39 PM PDT 24 2077431477 ps
T826 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.886315922 Jun 07 07:42:22 PM PDT 24 Jun 07 07:42:25 PM PDT 24 11733959 ps
T827 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.4121338384 Jun 07 07:41:33 PM PDT 24 Jun 07 07:46:12 PM PDT 24 8470137100 ps
T155 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2230452023 Jun 07 07:42:07 PM PDT 24 Jun 07 07:50:29 PM PDT 24 76069297532 ps
T828 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1694111720 Jun 07 07:41:17 PM PDT 24 Jun 07 07:44:15 PM PDT 24 3133280749 ps
T829 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3767620791 Jun 07 07:42:09 PM PDT 24 Jun 07 07:42:16 PM PDT 24 50195594 ps
T173 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.445294281 Jun 07 07:41:25 PM PDT 24 Jun 07 07:41:29 PM PDT 24 21864694 ps
T830 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4229931218 Jun 07 07:42:07 PM PDT 24 Jun 07 07:42:23 PM PDT 24 148850983 ps
T831 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1080563782 Jun 07 07:41:20 PM PDT 24 Jun 07 07:41:23 PM PDT 24 7767279 ps
T832 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1655956737 Jun 07 07:41:31 PM PDT 24 Jun 07 07:41:34 PM PDT 24 9813113 ps
T833 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1981104249 Jun 07 07:42:10 PM PDT 24 Jun 07 07:42:20 PM PDT 24 63627328 ps

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.3437323488
Short name T1
Test name
Test status
Simulation time 90054235265 ps
CPU time 1424.57 seconds
Started Jun 07 07:45:50 PM PDT 24
Finished Jun 07 08:09:36 PM PDT 24
Peak memory 288976 kb
Host smart-e417097a-dcc2-4d91-8ea0-6939ba536a8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437323488 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.3437323488
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.2265847206
Short name T13
Test name
Test status
Simulation time 1268307464 ps
CPU time 54.26 seconds
Started Jun 07 07:45:06 PM PDT 24
Finished Jun 07 07:46:03 PM PDT 24
Peak memory 275876 kb
Host smart-824334b6-585b-414a-9300-9d1b5b2d52e7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2265847206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2265847206
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.1430404637
Short name T30
Test name
Test status
Simulation time 258002517104 ps
CPU time 3014.38 seconds
Started Jun 07 07:45:55 PM PDT 24
Finished Jun 07 08:36:11 PM PDT 24
Peak memory 289112 kb
Host smart-67e3d082-ef45-414b-9b26-44df4059e9ed
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430404637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.1430404637
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1290443598
Short name T159
Test name
Test status
Simulation time 2464177575 ps
CPU time 47.74 seconds
Started Jun 07 07:41:58 PM PDT 24
Finished Jun 07 07:42:47 PM PDT 24
Peak memory 244960 kb
Host smart-26ee64c0-3243-41cb-9dcc-83e8d084ace8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1290443598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1290443598
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.2858315334
Short name T15
Test name
Test status
Simulation time 51119707391 ps
CPU time 3237.13 seconds
Started Jun 07 07:44:41 PM PDT 24
Finished Jun 07 08:38:40 PM PDT 24
Peak memory 289160 kb
Host smart-5335bac5-e9db-435d-8402-60a7158c0e50
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858315334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.2858315334
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.3409656981
Short name T110
Test name
Test status
Simulation time 84492859746 ps
CPU time 877.07 seconds
Started Jun 07 07:45:21 PM PDT 24
Finished Jun 07 08:00:01 PM PDT 24
Peak memory 289816 kb
Host smart-bbf33826-f630-4788-83c0-218afb4a0e0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409656981 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.3409656981
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3224796049
Short name T122
Test name
Test status
Simulation time 17863117804 ps
CPU time 580.44 seconds
Started Jun 07 07:41:49 PM PDT 24
Finished Jun 07 07:51:31 PM PDT 24
Peak memory 265112 kb
Host smart-ec5bb4bc-c8f4-4f01-be27-e6c06f99c53e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224796049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3224796049
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.3748129063
Short name T27
Test name
Test status
Simulation time 17375717998 ps
CPU time 1734.16 seconds
Started Jun 07 07:49:00 PM PDT 24
Finished Jun 07 08:17:56 PM PDT 24
Peak memory 289712 kb
Host smart-c1b3237c-7a7e-435a-b25c-8e817bde2dc6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748129063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.3748129063
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.714990189
Short name T299
Test name
Test status
Simulation time 41259764469 ps
CPU time 2196.55 seconds
Started Jun 07 07:45:28 PM PDT 24
Finished Jun 07 08:22:06 PM PDT 24
Peak memory 288648 kb
Host smart-50bdce90-b42e-4b0b-923d-e76e6fb66512
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714990189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.714990189
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.700026334
Short name T54
Test name
Test status
Simulation time 372982568425 ps
CPU time 2289.56 seconds
Started Jun 07 07:45:18 PM PDT 24
Finished Jun 07 08:23:29 PM PDT 24
Peak memory 289232 kb
Host smart-c4a5c0ce-240d-482f-a3fd-9576a907f3bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700026334 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.700026334
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1910825968
Short name T135
Test name
Test status
Simulation time 4149262924 ps
CPU time 320.32 seconds
Started Jun 07 07:41:48 PM PDT 24
Finished Jun 07 07:47:09 PM PDT 24
Peak memory 273272 kb
Host smart-3b0e1d63-ccd6-4d25-a866-7b16852595b6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1910825968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1910825968
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.2925675196
Short name T19
Test name
Test status
Simulation time 109285488650 ps
CPU time 7246.87 seconds
Started Jun 07 07:48:44 PM PDT 24
Finished Jun 07 09:49:34 PM PDT 24
Peak memory 335912 kb
Host smart-5ca7ef7d-bdbd-4ea4-9191-ed78c15b6af8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925675196 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.2925675196
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1000219024
Short name T138
Test name
Test status
Simulation time 16279973373 ps
CPU time 1213.68 seconds
Started Jun 07 07:41:56 PM PDT 24
Finished Jun 07 08:02:11 PM PDT 24
Peak memory 265088 kb
Host smart-924c6cd3-39ec-4b94-9878-8b248ede6110
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000219024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1000219024
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.1457957394
Short name T51
Test name
Test status
Simulation time 29071346362 ps
CPU time 730.24 seconds
Started Jun 07 07:46:51 PM PDT 24
Finished Jun 07 07:59:02 PM PDT 24
Peak memory 272792 kb
Host smart-2ce2843c-739c-4534-b502-3270825e839e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457957394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1457957394
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.1312591654
Short name T11
Test name
Test status
Simulation time 10922380620 ps
CPU time 445.29 seconds
Started Jun 07 07:48:00 PM PDT 24
Finished Jun 07 07:55:26 PM PDT 24
Peak memory 247168 kb
Host smart-2ca3c0f5-a38d-4805-9921-0a8c1d7cfbc1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312591654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1312591654
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.949937017
Short name T143
Test name
Test status
Simulation time 52916674114 ps
CPU time 706.08 seconds
Started Jun 07 07:41:42 PM PDT 24
Finished Jun 07 07:53:30 PM PDT 24
Peak memory 265072 kb
Host smart-aa5db956-d6c0-40d7-8aae-c73d85d1fa4b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949937017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.949937017
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2110455477
Short name T311
Test name
Test status
Simulation time 163856250071 ps
CPU time 2713.27 seconds
Started Jun 07 07:47:37 PM PDT 24
Finished Jun 07 08:32:53 PM PDT 24
Peak memory 289280 kb
Host smart-210387f4-d449-47ad-b983-73af52f74b85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110455477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2110455477
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2740982278
Short name T162
Test name
Test status
Simulation time 9892302 ps
CPU time 1.58 seconds
Started Jun 07 07:41:53 PM PDT 24
Finished Jun 07 07:41:55 PM PDT 24
Peak memory 236568 kb
Host smart-eb16c192-93ee-4928-88dd-720548fafc45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2740982278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2740982278
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.214721466
Short name T125
Test name
Test status
Simulation time 3128616326 ps
CPU time 211 seconds
Started Jun 07 07:41:49 PM PDT 24
Finished Jun 07 07:45:20 PM PDT 24
Peak memory 270204 kb
Host smart-07238227-df1e-4b43-a3c6-01389ddb85ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=214721466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.214721466
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3763809359
Short name T116
Test name
Test status
Simulation time 209901055979 ps
CPU time 2225.2 seconds
Started Jun 07 07:45:17 PM PDT 24
Finished Jun 07 08:22:24 PM PDT 24
Peak memory 286924 kb
Host smart-f3ff56c4-f529-45b0-bf64-a887cfb6ea46
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763809359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3763809359
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2742377739
Short name T40
Test name
Test status
Simulation time 100739075639 ps
CPU time 1487.91 seconds
Started Jun 07 07:48:35 PM PDT 24
Finished Jun 07 08:13:25 PM PDT 24
Peak memory 273432 kb
Host smart-e59b4e87-32a1-4a0b-8db5-75a24bf0b5c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742377739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2742377739
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2134724820
Short name T9
Test name
Test status
Simulation time 25117226329 ps
CPU time 1487.15 seconds
Started Jun 07 07:46:46 PM PDT 24
Finished Jun 07 08:11:35 PM PDT 24
Peak memory 273224 kb
Host smart-cc6ccd3f-f391-44f0-a84d-a178a3aea872
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134724820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2134724820
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.3231093305
Short name T215
Test name
Test status
Simulation time 134595777230 ps
CPU time 445.37 seconds
Started Jun 07 07:45:40 PM PDT 24
Finished Jun 07 07:53:07 PM PDT 24
Peak memory 248372 kb
Host smart-42fb247f-36c8-42e8-a62d-f156d9ac5ea6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231093305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.3231093305
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.4004167226
Short name T139
Test name
Test status
Simulation time 1585747762 ps
CPU time 198.88 seconds
Started Jun 07 07:41:37 PM PDT 24
Finished Jun 07 07:44:57 PM PDT 24
Peak memory 273208 kb
Host smart-3385da14-add4-41c6-97dc-42d6265e0f1d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4004167226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.4004167226
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3768854951
Short name T149
Test name
Test status
Simulation time 3441148645 ps
CPU time 196.02 seconds
Started Jun 07 07:42:07 PM PDT 24
Finished Jun 07 07:45:25 PM PDT 24
Peak memory 265104 kb
Host smart-84d48c97-cc9e-44bc-b978-c7ff67db4915
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3768854951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3768854951
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.1571171949
Short name T36
Test name
Test status
Simulation time 59219474675 ps
CPU time 1664.88 seconds
Started Jun 07 07:48:01 PM PDT 24
Finished Jun 07 08:15:47 PM PDT 24
Peak memory 273388 kb
Host smart-174a804b-d390-4832-bae3-2e5a9cc12239
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571171949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1571171949
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3157092359
Short name T74
Test name
Test status
Simulation time 260081903617 ps
CPU time 3672.1 seconds
Started Jun 07 07:48:28 PM PDT 24
Finished Jun 07 08:49:41 PM PDT 24
Peak memory 289588 kb
Host smart-05352bd6-8c3d-45fb-96b8-ba16386ed67a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157092359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3157092359
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.4229186994
Short name T127
Test name
Test status
Simulation time 340380295430 ps
CPU time 1201.99 seconds
Started Jun 07 07:41:25 PM PDT 24
Finished Jun 07 08:01:29 PM PDT 24
Peak memory 265336 kb
Host smart-7aafcfb1-b867-4cf9-8a79-abf39c625e25
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229186994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.4229186994
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.605957996
Short name T318
Test name
Test status
Simulation time 12015249123 ps
CPU time 482.46 seconds
Started Jun 07 07:47:14 PM PDT 24
Finished Jun 07 07:55:18 PM PDT 24
Peak memory 247236 kb
Host smart-d6a31845-a8c5-402d-855e-12e0f113f221
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605957996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.605957996
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.2944358002
Short name T87
Test name
Test status
Simulation time 1505998526067 ps
CPU time 4909.96 seconds
Started Jun 07 07:46:46 PM PDT 24
Finished Jun 07 09:08:38 PM PDT 24
Peak memory 305772 kb
Host smart-8a42f463-43c1-422e-ba00-6eeca6f8e39e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944358002 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.2944358002
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.798455209
Short name T151
Test name
Test status
Simulation time 16063447755 ps
CPU time 1144.41 seconds
Started Jun 07 07:42:08 PM PDT 24
Finished Jun 07 08:01:14 PM PDT 24
Peak memory 265080 kb
Host smart-40cf3ca7-e4c1-4c45-8229-f38151480831
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798455209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.798455209
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.586662241
Short name T103
Test name
Test status
Simulation time 51135087053 ps
CPU time 510.93 seconds
Started Jun 07 07:45:19 PM PDT 24
Finished Jun 07 07:53:52 PM PDT 24
Peak memory 248272 kb
Host smart-05a39168-8740-4977-b28a-ac02ea6b14df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586662241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.586662241
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1856371580
Short name T336
Test name
Test status
Simulation time 45408956284 ps
CPU time 2823.56 seconds
Started Jun 07 07:45:17 PM PDT 24
Finished Jun 07 08:32:23 PM PDT 24
Peak memory 289176 kb
Host smart-c937908e-17c1-42ba-a3b4-b0ad4c6cbf0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856371580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1856371580
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1008596564
Short name T133
Test name
Test status
Simulation time 6642782461 ps
CPU time 719.9 seconds
Started Jun 07 07:42:08 PM PDT 24
Finished Jun 07 07:54:09 PM PDT 24
Peak memory 265096 kb
Host smart-f65b6b99-0889-4ab0-93e3-43e7fe1ebf91
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008596564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1008596564
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2993183490
Short name T109
Test name
Test status
Simulation time 152459187117 ps
CPU time 2543 seconds
Started Jun 07 07:44:50 PM PDT 24
Finished Jun 07 08:27:15 PM PDT 24
Peak memory 289024 kb
Host smart-1614de5b-c776-46f5-a918-bc76ccb82d4e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993183490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2993183490
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.2994657968
Short name T334
Test name
Test status
Simulation time 51425889094 ps
CPU time 1404.41 seconds
Started Jun 07 07:47:15 PM PDT 24
Finished Jun 07 08:10:41 PM PDT 24
Peak memory 273384 kb
Host smart-044c01be-fcf1-4fbf-9e6f-f44d52bae321
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994657968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2994657968
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.3280175013
Short name T25
Test name
Test status
Simulation time 316326031186 ps
CPU time 6540.6 seconds
Started Jun 07 07:45:10 PM PDT 24
Finished Jun 07 09:34:14 PM PDT 24
Peak memory 371776 kb
Host smart-e59ab50a-6759-4f7d-a6dc-a4f412ad92c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280175013 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.3280175013
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.4154076563
Short name T170
Test name
Test status
Simulation time 145329160 ps
CPU time 3.9 seconds
Started Jun 07 07:41:58 PM PDT 24
Finished Jun 07 07:42:03 PM PDT 24
Peak memory 235748 kb
Host smart-53d5d47d-f64d-4ac5-a665-d6d4a592769d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4154076563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.4154076563
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3791260056
Short name T123
Test name
Test status
Simulation time 4330697068 ps
CPU time 95.4 seconds
Started Jun 07 07:41:26 PM PDT 24
Finished Jun 07 07:43:02 PM PDT 24
Peak memory 256912 kb
Host smart-89df17eb-bf60-4c94-a443-1763cf780a64
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3791260056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3791260056
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.1331631495
Short name T743
Test name
Test status
Simulation time 10034139 ps
CPU time 1.55 seconds
Started Jun 07 07:41:57 PM PDT 24
Finished Jun 07 07:42:00 PM PDT 24
Peak memory 236652 kb
Host smart-92e53026-676f-4e8d-9a19-00391ceb6b39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1331631495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.1331631495
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.1976392725
Short name T610
Test name
Test status
Simulation time 9792126182 ps
CPU time 413.22 seconds
Started Jun 07 07:45:20 PM PDT 24
Finished Jun 07 07:52:16 PM PDT 24
Peak memory 254916 kb
Host smart-35d07b2b-666a-4226-816f-51fb493cefc5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976392725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1976392725
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3819626111
Short name T303
Test name
Test status
Simulation time 22690981751 ps
CPU time 451.76 seconds
Started Jun 07 07:47:05 PM PDT 24
Finished Jun 07 07:54:38 PM PDT 24
Peak memory 248244 kb
Host smart-1de60467-a173-4b58-b73a-7329d48b5422
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819626111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3819626111
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.2801174269
Short name T337
Test name
Test status
Simulation time 17610291425 ps
CPU time 1602.25 seconds
Started Jun 07 07:48:45 PM PDT 24
Finished Jun 07 08:15:29 PM PDT 24
Peak memory 288400 kb
Host smart-b3d5027f-f6b8-404f-8e95-4407a09ca2a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801174269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.2801174269
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.4106202224
Short name T24
Test name
Test status
Simulation time 136512713690 ps
CPU time 1840.58 seconds
Started Jun 07 07:45:08 PM PDT 24
Finished Jun 07 08:15:51 PM PDT 24
Peak memory 273324 kb
Host smart-6fed0ac2-3480-40d8-98d6-d6a7f3b59212
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106202224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.4106202224
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.332489884
Short name T312
Test name
Test status
Simulation time 12680331424 ps
CPU time 265.13 seconds
Started Jun 07 07:44:45 PM PDT 24
Finished Jun 07 07:49:12 PM PDT 24
Peak memory 248352 kb
Host smart-1bf6fcc2-fa35-4cdb-8141-66c91d6d59ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332489884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.332489884
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.514412769
Short name T247
Test name
Test status
Simulation time 20677736966 ps
CPU time 1856.46 seconds
Started Jun 07 07:46:23 PM PDT 24
Finished Jun 07 08:17:21 PM PDT 24
Peak memory 289356 kb
Host smart-74e8a01f-bcee-462d-adbf-f18e73b77fc5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514412769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.514412769
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.2414229652
Short name T273
Test name
Test status
Simulation time 356993380146 ps
CPU time 9620.52 seconds
Started Jun 07 07:47:17 PM PDT 24
Finished Jun 07 10:27:40 PM PDT 24
Peak memory 394920 kb
Host smart-c9150cb7-6ddb-41a5-a9d5-16f0412355da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414229652 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.2414229652
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.3250813273
Short name T239
Test name
Test status
Simulation time 130332524776 ps
CPU time 9039.57 seconds
Started Jun 07 07:47:39 PM PDT 24
Finished Jun 07 10:18:22 PM PDT 24
Peak memory 365652 kb
Host smart-4b771ab1-cb42-423d-a453-eed2899180be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250813273 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.3250813273
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.347065162
Short name T132
Test name
Test status
Simulation time 6472303820 ps
CPU time 370.82 seconds
Started Jun 07 07:41:54 PM PDT 24
Finished Jun 07 07:48:06 PM PDT 24
Peak memory 272700 kb
Host smart-bbdc12af-0477-407e-b4e2-945f0633bb77
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=347065162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro
rs.347065162
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.4226730677
Short name T22
Test name
Test status
Simulation time 737362159 ps
CPU time 52.05 seconds
Started Jun 07 07:47:23 PM PDT 24
Finished Jun 07 07:48:17 PM PDT 24
Peak memory 249016 kb
Host smart-383c6b7d-49cd-432d-810c-315201f43cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42267
30677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.4226730677
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2111505214
Short name T209
Test name
Test status
Simulation time 71248875 ps
CPU time 3.14 seconds
Started Jun 07 07:44:39 PM PDT 24
Finished Jun 07 07:44:44 PM PDT 24
Peak memory 248876 kb
Host smart-eea579b6-bbfd-4895-ad58-86f9cbfbaac1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2111505214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2111505214
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.2662282697
Short name T203
Test name
Test status
Simulation time 332385632 ps
CPU time 3.02 seconds
Started Jun 07 07:44:42 PM PDT 24
Finished Jun 07 07:44:47 PM PDT 24
Peak memory 248896 kb
Host smart-168e7427-9a11-4381-8919-c391318919a6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2662282697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2662282697
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.1683982192
Short name T83
Test name
Test status
Simulation time 46741829 ps
CPU time 3.61 seconds
Started Jun 07 07:45:19 PM PDT 24
Finished Jun 07 07:45:26 PM PDT 24
Peak memory 248908 kb
Host smart-dc96b9c9-1cb2-4762-ac83-cf3d3c3abc2c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1683982192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.1683982192
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.630615084
Short name T211
Test name
Test status
Simulation time 16075612 ps
CPU time 2.64 seconds
Started Jun 07 07:45:35 PM PDT 24
Finished Jun 07 07:45:39 PM PDT 24
Peak memory 248804 kb
Host smart-bd0e3844-369e-4411-8b92-a98f8c31951f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=630615084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.630615084
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1338298168
Short name T126
Test name
Test status
Simulation time 4642172917 ps
CPU time 178.28 seconds
Started Jun 07 07:42:06 PM PDT 24
Finished Jun 07 07:45:05 PM PDT 24
Peak memory 273228 kb
Host smart-9bffc337-be0a-4644-a56b-41adceaf66df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1338298168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1338298168
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.200380685
Short name T350
Test name
Test status
Simulation time 17724746 ps
CPU time 1.39 seconds
Started Jun 07 07:42:13 PM PDT 24
Finished Jun 07 07:42:15 PM PDT 24
Peak memory 236692 kb
Host smart-af22e181-d3ca-4e4b-a80c-90d0a06a059a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=200380685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.200380685
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.1387310468
Short name T252
Test name
Test status
Simulation time 267850945389 ps
CPU time 6752.71 seconds
Started Jun 07 07:45:26 PM PDT 24
Finished Jun 07 09:38:02 PM PDT 24
Peak memory 403384 kb
Host smart-5cc2d364-fc0c-4d70-a353-0a4cfb1809ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387310468 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.1387310468
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.3392118219
Short name T617
Test name
Test status
Simulation time 157221118152 ps
CPU time 2449.16 seconds
Started Jun 07 07:45:40 PM PDT 24
Finished Jun 07 08:26:32 PM PDT 24
Peak memory 288564 kb
Host smart-3a4318e2-6d2f-4fff-a753-8c4493bfd647
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392118219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3392118219
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.874268818
Short name T279
Test name
Test status
Simulation time 3568256569 ps
CPU time 54.86 seconds
Started Jun 07 07:45:47 PM PDT 24
Finished Jun 07 07:46:43 PM PDT 24
Peak memory 249020 kb
Host smart-dd529f07-a492-4fa3-bee0-db00e14764e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87426
8818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.874268818
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.2579344070
Short name T272
Test name
Test status
Simulation time 62206081201 ps
CPU time 908.7 seconds
Started Jun 07 07:47:16 PM PDT 24
Finished Jun 07 08:02:26 PM PDT 24
Peak memory 265116 kb
Host smart-7bf08741-3821-4c22-8551-f626a91dc58f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579344070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.2579344070
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1283225042
Short name T115
Test name
Test status
Simulation time 344430660816 ps
CPU time 8132.99 seconds
Started Jun 07 07:47:49 PM PDT 24
Finished Jun 07 10:03:25 PM PDT 24
Peak memory 394792 kb
Host smart-a5699502-a49b-40dc-a161-8a022b00902b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283225042 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1283225042
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.3679197738
Short name T112
Test name
Test status
Simulation time 25793512433 ps
CPU time 1332.73 seconds
Started Jun 07 07:45:08 PM PDT 24
Finished Jun 07 08:07:23 PM PDT 24
Peak memory 289024 kb
Host smart-e1382987-12ef-4d65-9b88-1adc7e1e6ebe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679197738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3679197738
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3269808129
Short name T130
Test name
Test status
Simulation time 6066113612 ps
CPU time 355.71 seconds
Started Jun 07 07:41:31 PM PDT 24
Finished Jun 07 07:47:28 PM PDT 24
Peak memory 273232 kb
Host smart-f6f66069-8e39-4607-bd39-1f9b8328fb0e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3269808129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3269808129
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.2922909427
Short name T23
Test name
Test status
Simulation time 1663649577 ps
CPU time 30.74 seconds
Started Jun 07 07:46:53 PM PDT 24
Finished Jun 07 07:47:25 PM PDT 24
Peak memory 256740 kb
Host smart-61c4cc45-3066-4165-948a-0c96001205eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29229
09427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2922909427
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1232630014
Short name T147
Test name
Test status
Simulation time 23808028730 ps
CPU time 154.46 seconds
Started Jun 07 07:41:41 PM PDT 24
Finished Jun 07 07:44:17 PM PDT 24
Peak memory 265124 kb
Host smart-dff43eca-901b-4c2e-96ff-52e5a51f6ce0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1232630014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1232630014
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3327128079
Short name T241
Test name
Test status
Simulation time 81632528 ps
CPU time 3.17 seconds
Started Jun 07 07:41:10 PM PDT 24
Finished Jun 07 07:41:14 PM PDT 24
Peak memory 236656 kb
Host smart-4330f041-6b63-4ce8-8109-67b291ebf0f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3327128079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.3327128079
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.613774300
Short name T255
Test name
Test status
Simulation time 1879634834 ps
CPU time 123.08 seconds
Started Jun 07 07:44:40 PM PDT 24
Finished Jun 07 07:46:45 PM PDT 24
Peak memory 256488 kb
Host smart-9f73e6f3-4e08-4f02-b164-726cd1bfd20c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61377
4300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.613774300
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.742853153
Short name T259
Test name
Test status
Simulation time 38346946671 ps
CPU time 1077.94 seconds
Started Jun 07 07:44:40 PM PDT 24
Finished Jun 07 08:02:40 PM PDT 24
Peak memory 282636 kb
Host smart-dca78704-b95b-409f-9f22-af951e66d25a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742853153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.742853153
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.2181052976
Short name T276
Test name
Test status
Simulation time 269729011860 ps
CPU time 7760.25 seconds
Started Jun 07 07:44:40 PM PDT 24
Finished Jun 07 09:54:03 PM PDT 24
Peak memory 387236 kb
Host smart-9a205e58-06e1-435f-ac23-8fb568b071a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181052976 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.2181052976
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.138200396
Short name T263
Test name
Test status
Simulation time 22393010439 ps
CPU time 1529.67 seconds
Started Jun 07 07:45:09 PM PDT 24
Finished Jun 07 08:10:41 PM PDT 24
Peak memory 288908 kb
Host smart-f69cbadc-98f6-4b04-a36f-b91fa762a8af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138200396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.138200396
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3912396675
Short name T320
Test name
Test status
Simulation time 2900325181 ps
CPU time 124.83 seconds
Started Jun 07 07:45:09 PM PDT 24
Finished Jun 07 07:47:17 PM PDT 24
Peak memory 247192 kb
Host smart-8bed4f9f-32c8-40f5-af76-00c29bd24217
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912396675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3912396675
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1165041400
Short name T298
Test name
Test status
Simulation time 1263239218 ps
CPU time 31.53 seconds
Started Jun 07 07:45:18 PM PDT 24
Finished Jun 07 07:45:51 PM PDT 24
Peak memory 248664 kb
Host smart-77ab7e42-71e9-4ddd-8e4d-0443833f154f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11650
41400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1165041400
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.562265801
Short name T256
Test name
Test status
Simulation time 87695047210 ps
CPU time 2515.57 seconds
Started Jun 07 07:45:26 PM PDT 24
Finished Jun 07 08:27:24 PM PDT 24
Peak memory 284936 kb
Host smart-aba70b40-f1e9-46ed-8e4c-032f76e8ae22
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562265801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.562265801
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.603070643
Short name T294
Test name
Test status
Simulation time 223131411214 ps
CPU time 4124.49 seconds
Started Jun 07 07:45:46 PM PDT 24
Finished Jun 07 08:54:32 PM PDT 24
Peak memory 305944 kb
Host smart-5f99f88f-2f12-4acd-9a03-67ad2e8f27cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603070643 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.603070643
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3809544671
Short name T265
Test name
Test status
Simulation time 237577195479 ps
CPU time 2466.03 seconds
Started Jun 07 07:45:49 PM PDT 24
Finished Jun 07 08:26:56 PM PDT 24
Peak memory 273672 kb
Host smart-13ac0cde-56b2-43df-8680-460f4ba9c580
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809544671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3809544671
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.3003989913
Short name T48
Test name
Test status
Simulation time 2193240628 ps
CPU time 38.14 seconds
Started Jun 07 07:44:48 PM PDT 24
Finished Jun 07 07:45:28 PM PDT 24
Peak memory 256776 kb
Host smart-98d3e09a-bdea-4f0d-87ad-8d346cdf362f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30039
89913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3003989913
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.2581350434
Short name T330
Test name
Test status
Simulation time 101248653296 ps
CPU time 1627.3 seconds
Started Jun 07 07:46:22 PM PDT 24
Finished Jun 07 08:13:31 PM PDT 24
Peak memory 273384 kb
Host smart-6d41546b-b35a-4a71-89b4-0fb16a9abadc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581350434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.2581350434
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.1305533757
Short name T61
Test name
Test status
Simulation time 48274358297 ps
CPU time 1119.25 seconds
Started Jun 07 07:47:37 PM PDT 24
Finished Jun 07 08:06:18 PM PDT 24
Peak memory 281492 kb
Host smart-f15db1bf-bbeb-4993-894a-d12feea2ab81
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305533757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.1305533757
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1438695555
Short name T305
Test name
Test status
Simulation time 45559833086 ps
CPU time 463.8 seconds
Started Jun 07 07:48:20 PM PDT 24
Finished Jun 07 07:56:05 PM PDT 24
Peak memory 247216 kb
Host smart-c001b241-49a5-4da3-ad48-28312a0bbb61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438695555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1438695555
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3163780389
Short name T246
Test name
Test status
Simulation time 21666730932 ps
CPU time 1256.32 seconds
Started Jun 07 07:48:38 PM PDT 24
Finished Jun 07 08:09:36 PM PDT 24
Peak memory 272936 kb
Host smart-39b7fdb5-cbd0-4f4b-aacc-cc13ab7b4cb1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163780389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3163780389
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2336162061
Short name T167
Test name
Test status
Simulation time 108760154 ps
CPU time 4.29 seconds
Started Jun 07 07:41:17 PM PDT 24
Finished Jun 07 07:41:23 PM PDT 24
Peak memory 235732 kb
Host smart-0f828e4e-4e6c-4cb4-aa93-9d857a060ab7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2336162061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2336162061
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2343468134
Short name T165
Test name
Test status
Simulation time 605488969 ps
CPU time 22.94 seconds
Started Jun 07 07:41:10 PM PDT 24
Finished Jun 07 07:41:35 PM PDT 24
Peak memory 240108 kb
Host smart-8349db92-ea0e-4dee-a53c-dad20991dd20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2343468134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.2343468134
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2936039314
Short name T169
Test name
Test status
Simulation time 162085945 ps
CPU time 21.52 seconds
Started Jun 07 07:41:38 PM PDT 24
Finished Jun 07 07:42:01 PM PDT 24
Peak memory 240064 kb
Host smart-7fb74aaf-579d-4277-9309-511889e6a7a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2936039314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2936039314
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1806853126
Short name T168
Test name
Test status
Simulation time 53938794 ps
CPU time 2.12 seconds
Started Jun 07 07:42:07 PM PDT 24
Finished Jun 07 07:42:10 PM PDT 24
Peak memory 236844 kb
Host smart-234351a8-8f6a-4dee-beee-5b78607e240d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1806853126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.1806853126
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1662927248
Short name T172
Test name
Test status
Simulation time 23160151 ps
CPU time 2.43 seconds
Started Jun 07 07:41:20 PM PDT 24
Finished Jun 07 07:41:23 PM PDT 24
Peak memory 236544 kb
Host smart-396f0f1d-d7d8-4685-b391-eda9152cd3fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1662927248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1662927248
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.388537412
Short name T166
Test name
Test status
Simulation time 110963613 ps
CPU time 3.17 seconds
Started Jun 07 07:41:32 PM PDT 24
Finished Jun 07 07:41:37 PM PDT 24
Peak memory 236692 kb
Host smart-88735bcb-3e5e-476b-a409-2be111f16c2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=388537412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.388537412
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1732708280
Short name T174
Test name
Test status
Simulation time 97624839 ps
CPU time 2.44 seconds
Started Jun 07 07:41:50 PM PDT 24
Finished Jun 07 07:41:53 PM PDT 24
Peak memory 236680 kb
Host smart-03b86012-af53-443c-8c48-f7482b886d2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1732708280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1732708280
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2322579776
Short name T179
Test name
Test status
Simulation time 634628879 ps
CPU time 23.66 seconds
Started Jun 07 07:41:58 PM PDT 24
Finished Jun 07 07:42:23 PM PDT 24
Peak memory 248276 kb
Host smart-894788fe-1c95-40f5-8da8-7b34f80026b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2322579776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2322579776
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1032860040
Short name T164
Test name
Test status
Simulation time 156212217 ps
CPU time 21.13 seconds
Started Jun 07 07:42:06 PM PDT 24
Finished Jun 07 07:42:28 PM PDT 24
Peak memory 245132 kb
Host smart-80855df1-d2d4-4d51-aa75-682ea4fa9bc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1032860040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1032860040
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3625955505
Short name T178
Test name
Test status
Simulation time 8848524083 ps
CPU time 65.17 seconds
Started Jun 07 07:42:14 PM PDT 24
Finished Jun 07 07:43:20 PM PDT 24
Peak memory 237820 kb
Host smart-d91e9e3a-4f94-4bf2-95de-4445563cdf55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3625955505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3625955505
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.445294281
Short name T173
Test name
Test status
Simulation time 21864694 ps
CPU time 2.65 seconds
Started Jun 07 07:41:25 PM PDT 24
Finished Jun 07 07:41:29 PM PDT 24
Peak memory 236692 kb
Host smart-19952d54-0227-4114-afd9-bdcc54e0b434
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=445294281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.445294281
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1082295771
Short name T158
Test name
Test status
Simulation time 93508136 ps
CPU time 4.07 seconds
Started Jun 07 07:41:24 PM PDT 24
Finished Jun 07 07:41:29 PM PDT 24
Peak memory 237052 kb
Host smart-60f32f8a-4fb3-47d2-8fff-4d2be802acb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1082295771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1082295771
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3865586363
Short name T171
Test name
Test status
Simulation time 40252266 ps
CPU time 3.17 seconds
Started Jun 07 07:41:33 PM PDT 24
Finished Jun 07 07:41:38 PM PDT 24
Peak memory 236692 kb
Host smart-bf8ddd72-7706-40c6-abd9-6fff01079cbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3865586363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3865586363
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3079043373
Short name T720
Test name
Test status
Simulation time 4306694379 ps
CPU time 157.53 seconds
Started Jun 07 07:41:12 PM PDT 24
Finished Jun 07 07:43:50 PM PDT 24
Peak memory 240188 kb
Host smart-9a262f3f-0455-419f-99f5-524d07c523c8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3079043373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3079043373
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2767126380
Short name T786
Test name
Test status
Simulation time 3553257258 ps
CPU time 115.32 seconds
Started Jun 07 07:41:09 PM PDT 24
Finished Jun 07 07:43:05 PM PDT 24
Peak memory 236768 kb
Host smart-a98403dc-dd8a-4dea-9359-e70859e5b901
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2767126380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2767126380
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3562941075
Short name T790
Test name
Test status
Simulation time 358795270 ps
CPU time 5.99 seconds
Started Jun 07 07:41:07 PM PDT 24
Finished Jun 07 07:41:14 PM PDT 24
Peak memory 240096 kb
Host smart-901dd806-66a9-4222-a500-38ec4da2e02e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3562941075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3562941075
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.390861648
Short name T763
Test name
Test status
Simulation time 84673056 ps
CPU time 5.42 seconds
Started Jun 07 07:41:11 PM PDT 24
Finished Jun 07 07:41:18 PM PDT 24
Peak memory 236972 kb
Host smart-4318cddb-da3b-4303-b077-bb643c4b5896
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390861648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.390861648
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.553568635
Short name T736
Test name
Test status
Simulation time 50902034 ps
CPU time 5.04 seconds
Started Jun 07 07:41:14 PM PDT 24
Finished Jun 07 07:41:20 PM PDT 24
Peak memory 236648 kb
Host smart-b2aa5be3-2588-46a9-a0a7-00f5ff032f82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=553568635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.553568635
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3775312857
Short name T822
Test name
Test status
Simulation time 9560262 ps
CPU time 1.41 seconds
Started Jun 07 07:41:10 PM PDT 24
Finished Jun 07 07:41:13 PM PDT 24
Peak memory 234756 kb
Host smart-58f93e18-2a31-42f4-afb3-6f1502f76d6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3775312857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3775312857
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.785398042
Short name T185
Test name
Test status
Simulation time 451485779 ps
CPU time 26.64 seconds
Started Jun 07 07:41:09 PM PDT 24
Finished Jun 07 07:41:36 PM PDT 24
Peak memory 244884 kb
Host smart-a01c2cf1-4419-4136-9079-a9ba1a047e54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=785398042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.785398042
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1130087007
Short name T144
Test name
Test status
Simulation time 1859164970 ps
CPU time 159.93 seconds
Started Jun 07 07:41:11 PM PDT 24
Finished Jun 07 07:43:52 PM PDT 24
Peak memory 256908 kb
Host smart-038878bb-1cf1-4ef1-a3a5-f06edf31b52e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1130087007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1130087007
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2408113763
Short name T142
Test name
Test status
Simulation time 17292892708 ps
CPU time 1355.51 seconds
Started Jun 07 07:41:07 PM PDT 24
Finished Jun 07 08:03:44 PM PDT 24
Peak memory 265208 kb
Host smart-aea1d0be-c6f8-414a-bcc1-8b76b5979f09
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408113763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.2408113763
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1308823331
Short name T792
Test name
Test status
Simulation time 298559421 ps
CPU time 10.07 seconds
Started Jun 07 07:41:09 PM PDT 24
Finished Jun 07 07:41:20 PM PDT 24
Peak memory 254508 kb
Host smart-d33706aa-931f-4009-a505-2d16dc086ab2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1308823331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1308823331
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.649911181
Short name T183
Test name
Test status
Simulation time 8291417843 ps
CPU time 271.36 seconds
Started Jun 07 07:41:16 PM PDT 24
Finished Jun 07 07:45:49 PM PDT 24
Peak memory 240148 kb
Host smart-b5c7b3ed-929b-4846-a14e-e77f088bb451
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=649911181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.649911181
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2345175278
Short name T753
Test name
Test status
Simulation time 11382917927 ps
CPU time 200.63 seconds
Started Jun 07 07:41:16 PM PDT 24
Finished Jun 07 07:44:39 PM PDT 24
Peak memory 235836 kb
Host smart-0be0be87-bd6f-4888-a188-568bc7f3695e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2345175278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2345175278
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.883161891
Short name T727
Test name
Test status
Simulation time 316858876 ps
CPU time 4.96 seconds
Started Jun 07 07:41:17 PM PDT 24
Finished Jun 07 07:41:24 PM PDT 24
Peak memory 240072 kb
Host smart-abaeb6bf-0902-4c65-9769-bd075d57743e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=883161891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.883161891
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.4208535300
Short name T798
Test name
Test status
Simulation time 38963620 ps
CPU time 6.8 seconds
Started Jun 07 07:41:17 PM PDT 24
Finished Jun 07 07:41:26 PM PDT 24
Peak memory 256568 kb
Host smart-deb8e5f7-caae-4b9b-affa-0c15d7ab1a9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208535300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.4208535300
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1960096239
Short name T180
Test name
Test status
Simulation time 168586992 ps
CPU time 4.84 seconds
Started Jun 07 07:41:16 PM PDT 24
Finished Jun 07 07:41:23 PM PDT 24
Peak memory 239360 kb
Host smart-3c02d829-94a2-480d-be4c-3c4cf1514c20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1960096239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1960096239
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2067209665
Short name T801
Test name
Test status
Simulation time 6714220 ps
CPU time 1.52 seconds
Started Jun 07 07:41:15 PM PDT 24
Finished Jun 07 07:41:18 PM PDT 24
Peak memory 236668 kb
Host smart-4a54c085-632a-4ec9-a699-8afb92bbe040
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2067209665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2067209665
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.178825499
Short name T816
Test name
Test status
Simulation time 174377395 ps
CPU time 27.02 seconds
Started Jun 07 07:41:18 PM PDT 24
Finished Jun 07 07:41:47 PM PDT 24
Peak memory 244860 kb
Host smart-281a3e8e-6954-41c2-92b9-097abb4dd998
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=178825499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outs
tanding.178825499
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.4182788970
Short name T154
Test name
Test status
Simulation time 1083531274 ps
CPU time 91.87 seconds
Started Jun 07 07:41:12 PM PDT 24
Finished Jun 07 07:42:46 PM PDT 24
Peak memory 266224 kb
Host smart-f6c2cbc8-ef37-4b25-aa01-7da1d4d3b82c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4182788970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.4182788970
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.4096170840
Short name T128
Test name
Test status
Simulation time 2095424564 ps
CPU time 333.5 seconds
Started Jun 07 07:41:10 PM PDT 24
Finished Jun 07 07:46:44 PM PDT 24
Peak memory 265288 kb
Host smart-622d7815-9724-4193-bd6e-8d50d741f7b1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096170840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.4096170840
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.890869438
Short name T751
Test name
Test status
Simulation time 133536040 ps
CPU time 3.85 seconds
Started Jun 07 07:41:09 PM PDT 24
Finished Jun 07 07:41:13 PM PDT 24
Peak memory 240172 kb
Host smart-ed841142-88a0-4cb6-bb1d-5ff3972f0fb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=890869438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.890869438
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.93900919
Short name T176
Test name
Test status
Simulation time 394429070 ps
CPU time 7.82 seconds
Started Jun 07 07:41:49 PM PDT 24
Finished Jun 07 07:41:58 PM PDT 24
Peak memory 240140 kb
Host smart-2a3b5725-a002-4769-b357-0293bfc3bc1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93900919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.alert_handler_csr_mem_rw_with_rand_reset.93900919
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3017714763
Short name T230
Test name
Test status
Simulation time 451568150 ps
CPU time 9.68 seconds
Started Jun 07 07:41:39 PM PDT 24
Finished Jun 07 07:41:50 PM PDT 24
Peak memory 236508 kb
Host smart-4e32a9dd-8d88-4d0d-bf82-2a5a01c77261
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3017714763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3017714763
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1301034063
Short name T742
Test name
Test status
Simulation time 32307321 ps
CPU time 1.26 seconds
Started Jun 07 07:41:39 PM PDT 24
Finished Jun 07 07:41:41 PM PDT 24
Peak memory 236716 kb
Host smart-c6aeb3c8-d85a-461e-b3ad-c873aad9d3f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1301034063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1301034063
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3551196871
Short name T815
Test name
Test status
Simulation time 340597114 ps
CPU time 24 seconds
Started Jun 07 07:41:49 PM PDT 24
Finished Jun 07 07:42:14 PM PDT 24
Peak memory 244876 kb
Host smart-9c8ed824-df9a-419e-b6cb-9911a2b7986b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3551196871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3551196871
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2642032644
Short name T131
Test name
Test status
Simulation time 13516416195 ps
CPU time 178.29 seconds
Started Jun 07 07:41:40 PM PDT 24
Finished Jun 07 07:44:39 PM PDT 24
Peak memory 263976 kb
Host smart-18200dcd-1431-4ac5-8f32-82206575d6fa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2642032644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.2642032644
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1699762556
Short name T145
Test name
Test status
Simulation time 31199094476 ps
CPU time 311.84 seconds
Started Jun 07 07:41:41 PM PDT 24
Finished Jun 07 07:46:54 PM PDT 24
Peak memory 265184 kb
Host smart-a16f1aaf-08ce-4465-96a9-d5ef8619ef01
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699762556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.1699762556
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3968112967
Short name T714
Test name
Test status
Simulation time 72189513 ps
CPU time 5.61 seconds
Started Jun 07 07:41:38 PM PDT 24
Finished Jun 07 07:41:45 PM PDT 24
Peak memory 251580 kb
Host smart-599c00ad-0f24-40dd-aeff-ef4a54a3d32b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3968112967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3968112967
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2336284910
Short name T794
Test name
Test status
Simulation time 1284770951 ps
CPU time 12.83 seconds
Started Jun 07 07:41:51 PM PDT 24
Finished Jun 07 07:42:04 PM PDT 24
Peak memory 251368 kb
Host smart-059d46e9-bb0a-4000-ba3d-9cbc434f505f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336284910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2336284910
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3629028118
Short name T182
Test name
Test status
Simulation time 269402932 ps
CPU time 4.95 seconds
Started Jun 07 07:41:51 PM PDT 24
Finished Jun 07 07:41:57 PM PDT 24
Peak memory 240036 kb
Host smart-c84886f0-3c42-4395-96b0-b07b1254d4c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3629028118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.3629028118
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1898676036
Short name T776
Test name
Test status
Simulation time 1884058085 ps
CPU time 40.06 seconds
Started Jun 07 07:41:48 PM PDT 24
Finished Jun 07 07:42:29 PM PDT 24
Peak memory 243940 kb
Host smart-ab1a0689-49bb-4d4b-9298-fc2d40bf78b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1898676036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1898676036
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2032853547
Short name T153
Test name
Test status
Simulation time 22855929147 ps
CPU time 576.02 seconds
Started Jun 07 07:41:49 PM PDT 24
Finished Jun 07 07:51:25 PM PDT 24
Peak memory 269672 kb
Host smart-99a9019a-de7a-40da-a9f3-6172d43f2525
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032853547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2032853547
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.983416972
Short name T739
Test name
Test status
Simulation time 166891299 ps
CPU time 6.11 seconds
Started Jun 07 07:41:47 PM PDT 24
Finished Jun 07 07:41:54 PM PDT 24
Peak memory 247428 kb
Host smart-0beaac57-7992-482c-9a7b-3fc0d36fc780
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=983416972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.983416972
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3668928905
Short name T240
Test name
Test status
Simulation time 91328635 ps
CPU time 3.93 seconds
Started Jun 07 07:41:53 PM PDT 24
Finished Jun 07 07:41:58 PM PDT 24
Peak memory 236404 kb
Host smart-831150c0-2348-420e-8147-ba088bdabc35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3668928905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3668928905
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1513595802
Short name T177
Test name
Test status
Simulation time 316768087 ps
CPU time 7.77 seconds
Started Jun 07 07:41:49 PM PDT 24
Finished Jun 07 07:41:57 PM PDT 24
Peak memory 240104 kb
Host smart-9b387f66-4e6d-4898-aaa7-288eb7c94ff4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513595802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1513595802
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1962202460
Short name T764
Test name
Test status
Simulation time 61222198 ps
CPU time 5.76 seconds
Started Jun 07 07:41:50 PM PDT 24
Finished Jun 07 07:41:56 PM PDT 24
Peak memory 236656 kb
Host smart-5d3c0130-6349-4fb7-9459-1a7d01ad2c1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1962202460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1962202460
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.797033384
Short name T740
Test name
Test status
Simulation time 18315554 ps
CPU time 1.37 seconds
Started Jun 07 07:41:48 PM PDT 24
Finished Jun 07 07:41:50 PM PDT 24
Peak memory 235748 kb
Host smart-e6bef538-11d4-4281-876a-b7b7af0717b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=797033384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.797033384
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2301727973
Short name T819
Test name
Test status
Simulation time 1003411959 ps
CPU time 19.67 seconds
Started Jun 07 07:41:54 PM PDT 24
Finished Jun 07 07:42:14 PM PDT 24
Peak memory 248160 kb
Host smart-b3de1da2-4df6-46ac-b0a6-863124d7039a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2301727973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.2301727973
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2058445563
Short name T150
Test name
Test status
Simulation time 48829234489 ps
CPU time 926.29 seconds
Started Jun 07 07:41:50 PM PDT 24
Finished Jun 07 07:57:17 PM PDT 24
Peak memory 265060 kb
Host smart-86286803-e1ec-4043-985e-85cd987dd9fd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058445563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2058445563
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3648184280
Short name T721
Test name
Test status
Simulation time 613134056 ps
CPU time 12.49 seconds
Started Jun 07 07:41:54 PM PDT 24
Finished Jun 07 07:42:08 PM PDT 24
Peak memory 251556 kb
Host smart-9831205d-90eb-4c18-9c31-48f4d5929a46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3648184280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3648184280
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2891482178
Short name T232
Test name
Test status
Simulation time 201226874 ps
CPU time 15.24 seconds
Started Jun 07 07:41:58 PM PDT 24
Finished Jun 07 07:42:14 PM PDT 24
Peak memory 250524 kb
Host smart-27058236-2a37-4e55-874f-f764dfc1c30d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891482178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2891482178
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.255129523
Short name T175
Test name
Test status
Simulation time 257597834 ps
CPU time 5.85 seconds
Started Jun 07 07:41:58 PM PDT 24
Finished Jun 07 07:42:05 PM PDT 24
Peak memory 236688 kb
Host smart-c005f5ea-bda7-462d-b26b-f3aee78049d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=255129523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.255129523
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2893628873
Short name T754
Test name
Test status
Simulation time 8569753 ps
CPU time 1.51 seconds
Started Jun 07 07:41:58 PM PDT 24
Finished Jun 07 07:42:01 PM PDT 24
Peak memory 235752 kb
Host smart-c31bde1f-d493-43a7-b6d4-5cb48abb8286
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2893628873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.2893628873
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2327999242
Short name T757
Test name
Test status
Simulation time 391638964 ps
CPU time 19.62 seconds
Started Jun 07 07:41:57 PM PDT 24
Finished Jun 07 07:42:18 PM PDT 24
Peak memory 243940 kb
Host smart-65f1ec90-a602-45e1-8550-569cbe1b712e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2327999242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2327999242
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3605840298
Short name T760
Test name
Test status
Simulation time 537248915 ps
CPU time 16.78 seconds
Started Jun 07 07:41:49 PM PDT 24
Finished Jun 07 07:42:07 PM PDT 24
Peak memory 248292 kb
Host smart-e2e0a8b8-8ad7-4c40-873d-1a24ad30a346
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3605840298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3605840298
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3870156785
Short name T354
Test name
Test status
Simulation time 38167395 ps
CPU time 6.49 seconds
Started Jun 07 07:41:58 PM PDT 24
Finished Jun 07 07:42:06 PM PDT 24
Peak memory 248360 kb
Host smart-bd01c776-9655-4d41-b97d-5dd735763640
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870156785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3870156785
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2277591226
Short name T732
Test name
Test status
Simulation time 34145273 ps
CPU time 3.75 seconds
Started Jun 07 07:41:57 PM PDT 24
Finished Jun 07 07:42:02 PM PDT 24
Peak memory 236676 kb
Host smart-5cb562d3-b563-4871-9c10-bf48d4c8f4c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2277591226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2277591226
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2131913064
Short name T220
Test name
Test status
Simulation time 1772261924 ps
CPU time 20.62 seconds
Started Jun 07 07:41:55 PM PDT 24
Finished Jun 07 07:42:17 PM PDT 24
Peak memory 248312 kb
Host smart-eaaf120c-a1e9-4206-ab68-9ce27353c91b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2131913064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.2131913064
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3524767229
Short name T152
Test name
Test status
Simulation time 6275419938 ps
CPU time 244.79 seconds
Started Jun 07 07:41:57 PM PDT 24
Finished Jun 07 07:46:04 PM PDT 24
Peak memory 265148 kb
Host smart-1bd410a5-1051-4b3d-85f9-8764ff1f7d45
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3524767229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3524767229
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3877713853
Short name T766
Test name
Test status
Simulation time 770020017 ps
CPU time 14.72 seconds
Started Jun 07 07:41:55 PM PDT 24
Finished Jun 07 07:42:11 PM PDT 24
Peak memory 253944 kb
Host smart-b49b7b18-a28f-44d9-8f43-a4b79876fda4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3877713853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3877713853
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1783228259
Short name T718
Test name
Test status
Simulation time 95542410 ps
CPU time 4.74 seconds
Started Jun 07 07:42:08 PM PDT 24
Finished Jun 07 07:42:14 PM PDT 24
Peak memory 238588 kb
Host smart-10111173-c619-482d-b2c2-9ff961fc3db6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783228259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1783228259
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3767620791
Short name T829
Test name
Test status
Simulation time 50195594 ps
CPU time 5.26 seconds
Started Jun 07 07:42:09 PM PDT 24
Finished Jun 07 07:42:16 PM PDT 24
Peak memory 235708 kb
Host smart-04d3ff11-fe32-4ad6-a4e2-387024dc2655
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3767620791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3767620791
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1233847911
Short name T811
Test name
Test status
Simulation time 6476650 ps
CPU time 1.46 seconds
Started Jun 07 07:41:57 PM PDT 24
Finished Jun 07 07:42:00 PM PDT 24
Peak memory 235796 kb
Host smart-a8aea49f-1f86-46f2-8d8c-7e9394ea16d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1233847911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1233847911
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2792669807
Short name T823
Test name
Test status
Simulation time 709866415 ps
CPU time 18.41 seconds
Started Jun 07 07:42:09 PM PDT 24
Finished Jun 07 07:42:29 PM PDT 24
Peak memory 243944 kb
Host smart-42730fe9-b6d0-4504-8229-43bd97bfe90b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2792669807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2792669807
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1491094929
Short name T140
Test name
Test status
Simulation time 2029149932 ps
CPU time 137.4 seconds
Started Jun 07 07:41:58 PM PDT 24
Finished Jun 07 07:44:17 PM PDT 24
Peak memory 265064 kb
Host smart-928a5616-2487-4f47-b30f-ecfad6bbf59f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1491094929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1491094929
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1178163549
Short name T355
Test name
Test status
Simulation time 12516590706 ps
CPU time 564.18 seconds
Started Jun 07 07:42:00 PM PDT 24
Finished Jun 07 07:51:25 PM PDT 24
Peak memory 265100 kb
Host smart-15b357d0-06c1-4766-b2e9-a143d5e8e46a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178163549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1178163549
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3881944078
Short name T722
Test name
Test status
Simulation time 1044689901 ps
CPU time 29.3 seconds
Started Jun 07 07:41:57 PM PDT 24
Finished Jun 07 07:42:28 PM PDT 24
Peak memory 248360 kb
Host smart-e067c04f-a644-450c-ba1f-ea7ef5368702
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3881944078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3881944078
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1981104249
Short name T833
Test name
Test status
Simulation time 63627328 ps
CPU time 8.88 seconds
Started Jun 07 07:42:10 PM PDT 24
Finished Jun 07 07:42:20 PM PDT 24
Peak memory 252128 kb
Host smart-b81820ab-0068-43c0-b9ff-561153134540
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981104249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.1981104249
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2296802375
Short name T770
Test name
Test status
Simulation time 35882838 ps
CPU time 5.74 seconds
Started Jun 07 07:42:09 PM PDT 24
Finished Jun 07 07:42:17 PM PDT 24
Peak memory 236656 kb
Host smart-efa4248e-6432-44d9-b1be-1ac0bb6e82a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2296802375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2296802375
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3133729791
Short name T800
Test name
Test status
Simulation time 8937987 ps
CPU time 1.39 seconds
Started Jun 07 07:42:11 PM PDT 24
Finished Jun 07 07:42:13 PM PDT 24
Peak memory 236716 kb
Host smart-94c7d31a-d5c7-48f3-b59f-86d152d0fac6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3133729791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.3133729791
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3183919088
Short name T755
Test name
Test status
Simulation time 648165847 ps
CPU time 43.16 seconds
Started Jun 07 07:42:12 PM PDT 24
Finished Jun 07 07:42:56 PM PDT 24
Peak memory 248304 kb
Host smart-6e84bbe8-370c-4e96-914c-d10a8ed43dcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3183919088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3183919088
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.953101805
Short name T136
Test name
Test status
Simulation time 795064948 ps
CPU time 94.72 seconds
Started Jun 07 07:42:06 PM PDT 24
Finished Jun 07 07:43:42 PM PDT 24
Peak memory 265088 kb
Host smart-d791078b-e621-4033-abf4-6ced96ec15cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=953101805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_erro
rs.953101805
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2230452023
Short name T155
Test name
Test status
Simulation time 76069297532 ps
CPU time 500.78 seconds
Started Jun 07 07:42:07 PM PDT 24
Finished Jun 07 07:50:29 PM PDT 24
Peak memory 269272 kb
Host smart-8b87aee2-91bd-4a7d-b0cf-fd1a4a64a1e0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230452023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2230452023
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3091354159
Short name T759
Test name
Test status
Simulation time 275828745 ps
CPU time 6.86 seconds
Started Jun 07 07:42:07 PM PDT 24
Finished Jun 07 07:42:16 PM PDT 24
Peak memory 247788 kb
Host smart-0c71f775-6f49-4927-a0d4-05b553aafd2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3091354159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3091354159
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3516284696
Short name T731
Test name
Test status
Simulation time 70791866 ps
CPU time 6.25 seconds
Started Jun 07 07:42:07 PM PDT 24
Finished Jun 07 07:42:15 PM PDT 24
Peak memory 240144 kb
Host smart-156123ec-b98f-428b-8e65-d925d63ab5c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516284696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.3516284696
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1196974193
Short name T799
Test name
Test status
Simulation time 96283040 ps
CPU time 8.6 seconds
Started Jun 07 07:42:07 PM PDT 24
Finished Jun 07 07:42:18 PM PDT 24
Peak memory 236608 kb
Host smart-6d70a59d-c9ff-4f17-a4b1-4c0844000a48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1196974193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1196974193
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3119790035
Short name T747
Test name
Test status
Simulation time 23508505 ps
CPU time 1.52 seconds
Started Jun 07 07:42:06 PM PDT 24
Finished Jun 07 07:42:08 PM PDT 24
Peak memory 235712 kb
Host smart-f5d7c57c-f113-4679-a36a-f14ff05f50e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3119790035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3119790035
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2774080993
Short name T737
Test name
Test status
Simulation time 497846124 ps
CPU time 34.58 seconds
Started Jun 07 07:42:05 PM PDT 24
Finished Jun 07 07:42:41 PM PDT 24
Peak memory 248300 kb
Host smart-cdc91e83-b94a-421f-93da-c9e1379d46d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2774080993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2774080993
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1784077919
Short name T137
Test name
Test status
Simulation time 10204643700 ps
CPU time 156.19 seconds
Started Jun 07 07:42:07 PM PDT 24
Finished Jun 07 07:44:45 PM PDT 24
Peak memory 265104 kb
Host smart-64184352-ff75-4828-917d-fa3ed78e1b16
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1784077919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.1784077919
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.1830216733
Short name T803
Test name
Test status
Simulation time 4295203050 ps
CPU time 14.06 seconds
Started Jun 07 07:42:05 PM PDT 24
Finished Jun 07 07:42:20 PM PDT 24
Peak memory 248072 kb
Host smart-e7b9b599-a7a3-4271-8a08-ae5153894573
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1830216733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.1830216733
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4229931218
Short name T830
Test name
Test status
Simulation time 148850983 ps
CPU time 14.23 seconds
Started Jun 07 07:42:07 PM PDT 24
Finished Jun 07 07:42:23 PM PDT 24
Peak memory 250760 kb
Host smart-43bd622e-446c-4735-9dc7-d4137479a81a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229931218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.4229931218
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.974216169
Short name T734
Test name
Test status
Simulation time 429116284 ps
CPU time 8.72 seconds
Started Jun 07 07:42:06 PM PDT 24
Finished Jun 07 07:42:16 PM PDT 24
Peak memory 240048 kb
Host smart-8059f9ae-33fe-4dd5-8c6a-fdf23c946e66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=974216169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.974216169
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.914863253
Short name T791
Test name
Test status
Simulation time 6448528 ps
CPU time 1.39 seconds
Started Jun 07 07:42:06 PM PDT 24
Finished Jun 07 07:42:08 PM PDT 24
Peak memory 235764 kb
Host smart-b72766b3-642b-421b-8e9c-e0b58888a386
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=914863253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.914863253
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.159763986
Short name T758
Test name
Test status
Simulation time 1373384091 ps
CPU time 21.12 seconds
Started Jun 07 07:42:09 PM PDT 24
Finished Jun 07 07:42:31 PM PDT 24
Peak memory 244892 kb
Host smart-ceb99488-3d6e-498e-8412-2c4e92c9fdc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=159763986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_out
standing.159763986
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2057405777
Short name T719
Test name
Test status
Simulation time 35893148 ps
CPU time 5.67 seconds
Started Jun 07 07:42:05 PM PDT 24
Finished Jun 07 07:42:11 PM PDT 24
Peak memory 249416 kb
Host smart-263f06fe-07cf-4f9d-b8be-64db8f506aa6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2057405777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.2057405777
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2901995960
Short name T242
Test name
Test status
Simulation time 362167437 ps
CPU time 44.5 seconds
Started Jun 07 07:42:07 PM PDT 24
Finished Jun 07 07:42:54 PM PDT 24
Peak memory 239548 kb
Host smart-082209d0-f0fb-4680-af67-6e2635f880e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2901995960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2901995960
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.766118602
Short name T814
Test name
Test status
Simulation time 258318676 ps
CPU time 9.26 seconds
Started Jun 07 07:42:15 PM PDT 24
Finished Jun 07 07:42:25 PM PDT 24
Peak memory 251616 kb
Host smart-c31e8d0a-3a01-42c4-8419-a6a86d3f21b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766118602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.766118602
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1261226307
Short name T197
Test name
Test status
Simulation time 109940110 ps
CPU time 8.49 seconds
Started Jun 07 07:42:15 PM PDT 24
Finished Jun 07 07:42:24 PM PDT 24
Peak memory 240024 kb
Host smart-e379fb36-b255-454e-bf33-b71c4bf7f20c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1261226307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1261226307
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3712981762
Short name T730
Test name
Test status
Simulation time 10366829 ps
CPU time 1.59 seconds
Started Jun 07 07:42:12 PM PDT 24
Finished Jun 07 07:42:15 PM PDT 24
Peak memory 236720 kb
Host smart-e4a3417f-1033-4ce0-af98-b82757b7ab9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3712981762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3712981762
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.800564615
Short name T789
Test name
Test status
Simulation time 612714705 ps
CPU time 21.77 seconds
Started Jun 07 07:42:13 PM PDT 24
Finished Jun 07 07:42:36 PM PDT 24
Peak memory 244892 kb
Host smart-bb75bd12-675a-4dd8-82bc-7722e6909a3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=800564615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_out
standing.800564615
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1733437446
Short name T129
Test name
Test status
Simulation time 60013995713 ps
CPU time 474.45 seconds
Started Jun 07 07:42:08 PM PDT 24
Finished Jun 07 07:50:04 PM PDT 24
Peak memory 265100 kb
Host smart-4d44a025-98c1-43f4-b471-3f1d52544d52
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733437446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.1733437446
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3846206502
Short name T717
Test name
Test status
Simulation time 71245503 ps
CPU time 10.86 seconds
Started Jun 07 07:42:17 PM PDT 24
Finished Jun 07 07:42:29 PM PDT 24
Peak memory 248312 kb
Host smart-71ac2f9c-e6d9-457d-98f3-7528dc19f69d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3846206502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3846206502
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.4003820399
Short name T771
Test name
Test status
Simulation time 1208897438 ps
CPU time 170.3 seconds
Started Jun 07 07:41:18 PM PDT 24
Finished Jun 07 07:44:10 PM PDT 24
Peak memory 240088 kb
Host smart-2e5a26d9-0e2d-4f19-ad3f-82b9abb96e14
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4003820399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.4003820399
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3944005154
Short name T724
Test name
Test status
Simulation time 10584827214 ps
CPU time 216.57 seconds
Started Jun 07 07:41:15 PM PDT 24
Finished Jun 07 07:44:53 PM PDT 24
Peak memory 236724 kb
Host smart-ddd49bff-4d9b-4177-ac7f-05c229888944
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3944005154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3944005154
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1807513931
Short name T738
Test name
Test status
Simulation time 200785350 ps
CPU time 5.14 seconds
Started Jun 07 07:41:14 PM PDT 24
Finished Jun 07 07:41:21 PM PDT 24
Peak memory 240088 kb
Host smart-0b8c42ad-5562-42f6-ace9-3ebae3313398
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1807513931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1807513931
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1706596849
Short name T817
Test name
Test status
Simulation time 152800404 ps
CPU time 5.7 seconds
Started Jun 07 07:41:16 PM PDT 24
Finished Jun 07 07:41:24 PM PDT 24
Peak memory 248372 kb
Host smart-2e087860-cde4-46b9-aebf-86227a337611
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706596849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1706596849
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2634000353
Short name T762
Test name
Test status
Simulation time 539737861 ps
CPU time 9.27 seconds
Started Jun 07 07:41:16 PM PDT 24
Finished Jun 07 07:41:26 PM PDT 24
Peak memory 236644 kb
Host smart-b79ad6c4-84bb-4e7e-b2da-deaf2aa890e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2634000353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2634000353
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2440011424
Short name T733
Test name
Test status
Simulation time 13959797 ps
CPU time 1.72 seconds
Started Jun 07 07:41:15 PM PDT 24
Finished Jun 07 07:41:18 PM PDT 24
Peak memory 234720 kb
Host smart-b361ea35-e9d9-4d0e-af57-0f9f16a633df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2440011424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2440011424
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3942332940
Short name T744
Test name
Test status
Simulation time 1315953760 ps
CPU time 39.72 seconds
Started Jun 07 07:41:18 PM PDT 24
Finished Jun 07 07:41:59 PM PDT 24
Peak memory 244868 kb
Host smart-1610d95b-4201-4cfe-814f-88af7905e97a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3942332940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3942332940
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1645117797
Short name T156
Test name
Test status
Simulation time 4729570539 ps
CPU time 159.14 seconds
Started Jun 07 07:41:17 PM PDT 24
Finished Jun 07 07:43:58 PM PDT 24
Peak memory 265140 kb
Host smart-9667f19f-02f2-4f0c-a748-ef77474d891d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1645117797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1645117797
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3947226403
Short name T148
Test name
Test status
Simulation time 8557896985 ps
CPU time 571.25 seconds
Started Jun 07 07:41:16 PM PDT 24
Finished Jun 07 07:50:50 PM PDT 24
Peak memory 265072 kb
Host smart-6a1f88b5-61ed-4ed8-964e-390a0c206c2a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947226403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.3947226403
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3984286227
Short name T715
Test name
Test status
Simulation time 108446833 ps
CPU time 5.08 seconds
Started Jun 07 07:41:16 PM PDT 24
Finished Jun 07 07:41:23 PM PDT 24
Peak memory 250584 kb
Host smart-66b02d68-e59d-49d5-bee3-518733599b17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3984286227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.3984286227
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1629388542
Short name T351
Test name
Test status
Simulation time 16349864 ps
CPU time 1.35 seconds
Started Jun 07 07:42:14 PM PDT 24
Finished Jun 07 07:42:16 PM PDT 24
Peak memory 236672 kb
Host smart-285a6ac8-5d00-47f3-9c71-4362dbc2e005
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1629388542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1629388542
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1493029126
Short name T802
Test name
Test status
Simulation time 14116182 ps
CPU time 1.41 seconds
Started Jun 07 07:42:17 PM PDT 24
Finished Jun 07 07:42:19 PM PDT 24
Peak memory 235752 kb
Host smart-afa1abfb-3389-4b71-992a-c3117a4020c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1493029126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1493029126
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1378862745
Short name T767
Test name
Test status
Simulation time 8665130 ps
CPU time 1.38 seconds
Started Jun 07 07:42:14 PM PDT 24
Finished Jun 07 07:42:16 PM PDT 24
Peak memory 235780 kb
Host smart-a5937a68-21e3-4e0e-a396-325503928556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1378862745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1378862745
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.596593980
Short name T161
Test name
Test status
Simulation time 8362063 ps
CPU time 1.52 seconds
Started Jun 07 07:42:14 PM PDT 24
Finished Jun 07 07:42:17 PM PDT 24
Peak memory 236700 kb
Host smart-a505e9f7-7135-44f2-b09c-78cd57e31939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=596593980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.596593980
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.913691600
Short name T349
Test name
Test status
Simulation time 8747473 ps
CPU time 1.43 seconds
Started Jun 07 07:42:17 PM PDT 24
Finished Jun 07 07:42:19 PM PDT 24
Peak memory 235684 kb
Host smart-f5033351-3e6a-455a-8ade-0df2f0aa547f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=913691600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.913691600
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3622788878
Short name T795
Test name
Test status
Simulation time 21781500 ps
CPU time 1.36 seconds
Started Jun 07 07:42:14 PM PDT 24
Finished Jun 07 07:42:16 PM PDT 24
Peak memory 234736 kb
Host smart-03b08fbb-3021-4b9d-b4cb-9e0e30f353e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3622788878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3622788878
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.349957624
Short name T785
Test name
Test status
Simulation time 10701181 ps
CPU time 1.44 seconds
Started Jun 07 07:42:13 PM PDT 24
Finished Jun 07 07:42:16 PM PDT 24
Peak memory 235732 kb
Host smart-33defde1-c15e-4832-b96a-90ba210aab97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=349957624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.349957624
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.320617324
Short name T804
Test name
Test status
Simulation time 10297256 ps
CPU time 1.33 seconds
Started Jun 07 07:42:16 PM PDT 24
Finished Jun 07 07:42:19 PM PDT 24
Peak memory 236680 kb
Host smart-c67db1bb-f8f5-4cde-a3a5-8ba4ef13ce8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=320617324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.320617324
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.628794129
Short name T788
Test name
Test status
Simulation time 13064001 ps
CPU time 1.66 seconds
Started Jun 07 07:42:13 PM PDT 24
Finished Jun 07 07:42:16 PM PDT 24
Peak memory 235764 kb
Host smart-14e5c2ad-82e0-47c4-ae68-c04263cbb679
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=628794129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.628794129
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1072003351
Short name T825
Test name
Test status
Simulation time 2077431477 ps
CPU time 133.92 seconds
Started Jun 07 07:41:23 PM PDT 24
Finished Jun 07 07:43:39 PM PDT 24
Peak memory 240092 kb
Host smart-ea1cdd81-5177-4aa6-8f3f-6fa4981c9904
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1072003351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1072003351
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3369093372
Short name T728
Test name
Test status
Simulation time 3405747752 ps
CPU time 117.22 seconds
Started Jun 07 07:41:25 PM PDT 24
Finished Jun 07 07:43:24 PM PDT 24
Peak memory 240168 kb
Host smart-33d5cbb2-db2c-48d3-acf7-84fc55c6c537
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3369093372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3369093372
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2631071473
Short name T756
Test name
Test status
Simulation time 53999894 ps
CPU time 5.22 seconds
Started Jun 07 07:41:15 PM PDT 24
Finished Jun 07 07:41:22 PM PDT 24
Peak memory 240112 kb
Host smart-4025156c-7f25-477b-a8f5-e28175f7fe84
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2631071473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2631071473
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1482961857
Short name T796
Test name
Test status
Simulation time 266245155 ps
CPU time 5.7 seconds
Started Jun 07 07:41:26 PM PDT 24
Finished Jun 07 07:41:33 PM PDT 24
Peak memory 238680 kb
Host smart-da7a5dab-84dc-40ff-88aa-612f81608e65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482961857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1482961857
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2738340765
Short name T181
Test name
Test status
Simulation time 151295365 ps
CPU time 3.46 seconds
Started Jun 07 07:41:16 PM PDT 24
Finished Jun 07 07:41:21 PM PDT 24
Peak memory 235720 kb
Host smart-6c65d330-11d5-42f3-b36e-f80e80bd38d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2738340765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2738340765
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1080563782
Short name T831
Test name
Test status
Simulation time 7767279 ps
CPU time 1.34 seconds
Started Jun 07 07:41:20 PM PDT 24
Finished Jun 07 07:41:23 PM PDT 24
Peak memory 236664 kb
Host smart-58438a87-257f-49af-bf01-5d3173377f7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1080563782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1080563782
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2259681032
Short name T752
Test name
Test status
Simulation time 485058055 ps
CPU time 22.71 seconds
Started Jun 07 07:41:31 PM PDT 24
Finished Jun 07 07:41:55 PM PDT 24
Peak memory 244896 kb
Host smart-4ae489da-30df-4079-b54f-22d34f78d9d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2259681032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2259681032
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1694111720
Short name T828
Test name
Test status
Simulation time 3133280749 ps
CPU time 176.5 seconds
Started Jun 07 07:41:17 PM PDT 24
Finished Jun 07 07:44:15 PM PDT 24
Peak memory 265140 kb
Host smart-db6ca7f1-9fce-41b7-8f39-d9d79f1b899a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1694111720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1694111720
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3775652553
Short name T146
Test name
Test status
Simulation time 30490592996 ps
CPU time 548.37 seconds
Started Jun 07 07:41:23 PM PDT 24
Finished Jun 07 07:50:33 PM PDT 24
Peak memory 265144 kb
Host smart-a3c70abc-efe6-4811-8b8a-71ff117cb9b8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775652553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.3775652553
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2927974716
Short name T774
Test name
Test status
Simulation time 490430435 ps
CPU time 15.38 seconds
Started Jun 07 07:41:16 PM PDT 24
Finished Jun 07 07:41:33 PM PDT 24
Peak memory 247728 kb
Host smart-cbc70c74-692c-453b-9d28-5c40bff2a3b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2927974716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2927974716
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3230382617
Short name T810
Test name
Test status
Simulation time 13387369 ps
CPU time 1.34 seconds
Started Jun 07 07:42:15 PM PDT 24
Finished Jun 07 07:42:17 PM PDT 24
Peak memory 234748 kb
Host smart-d99208a5-4219-4a91-aa9c-2e437e457f79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3230382617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3230382617
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3286841597
Short name T235
Test name
Test status
Simulation time 11224328 ps
CPU time 1.6 seconds
Started Jun 07 07:42:31 PM PDT 24
Finished Jun 07 07:42:34 PM PDT 24
Peak memory 236716 kb
Host smart-6760dc74-8460-4608-8ff2-aca622d7a112
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3286841597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3286841597
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3162791155
Short name T793
Test name
Test status
Simulation time 7242818 ps
CPU time 1.44 seconds
Started Jun 07 07:42:22 PM PDT 24
Finished Jun 07 07:42:25 PM PDT 24
Peak memory 236708 kb
Host smart-e07d41ec-2c5e-4150-a418-417dacf59b7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3162791155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3162791155
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3991311891
Short name T809
Test name
Test status
Simulation time 8803290 ps
CPU time 1.62 seconds
Started Jun 07 07:42:29 PM PDT 24
Finished Jun 07 07:42:32 PM PDT 24
Peak memory 235792 kb
Host smart-ef0bac9e-8529-46c5-82ab-5dfe91aa719a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3991311891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3991311891
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1300204477
Short name T781
Test name
Test status
Simulation time 25343752 ps
CPU time 1.94 seconds
Started Jun 07 07:42:22 PM PDT 24
Finished Jun 07 07:42:26 PM PDT 24
Peak memory 235748 kb
Host smart-fd7c7a82-c233-47a4-92fc-e0e8f6e6a7da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1300204477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1300204477
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3822714521
Short name T780
Test name
Test status
Simulation time 15487998 ps
CPU time 1.44 seconds
Started Jun 07 07:42:22 PM PDT 24
Finished Jun 07 07:42:26 PM PDT 24
Peak memory 234712 kb
Host smart-5b8acee9-a45d-472a-8b90-429849fbf84b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3822714521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3822714521
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1928198473
Short name T813
Test name
Test status
Simulation time 21651064 ps
CPU time 1.4 seconds
Started Jun 07 07:42:21 PM PDT 24
Finished Jun 07 07:42:23 PM PDT 24
Peak memory 236716 kb
Host smart-ea922eb8-7b53-40a4-9611-72d0bce9eb63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1928198473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1928198473
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1888778613
Short name T352
Test name
Test status
Simulation time 11449345 ps
CPU time 1.35 seconds
Started Jun 07 07:42:21 PM PDT 24
Finished Jun 07 07:42:23 PM PDT 24
Peak memory 236716 kb
Host smart-918e2668-d141-4aee-83bd-6c70053f0184
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1888778613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1888778613
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.861914234
Short name T784
Test name
Test status
Simulation time 9835537 ps
CPU time 1.68 seconds
Started Jun 07 07:42:22 PM PDT 24
Finished Jun 07 07:42:25 PM PDT 24
Peak memory 235776 kb
Host smart-b4570eda-6d3b-4d4c-89a4-ca7a3277ab7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=861914234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.861914234
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.4233574313
Short name T761
Test name
Test status
Simulation time 11835268 ps
CPU time 1.66 seconds
Started Jun 07 07:42:21 PM PDT 24
Finished Jun 07 07:42:23 PM PDT 24
Peak memory 236696 kb
Host smart-300a26c6-8666-47f5-a5ff-8232e75afb2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4233574313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.4233574313
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3337035840
Short name T769
Test name
Test status
Simulation time 6411168800 ps
CPU time 247.89 seconds
Started Jun 07 07:41:25 PM PDT 24
Finished Jun 07 07:45:34 PM PDT 24
Peak memory 240180 kb
Host smart-1c58ca1c-0ba2-440f-bb43-c2e4879506ff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3337035840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3337035840
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.530636926
Short name T750
Test name
Test status
Simulation time 14814509241 ps
CPU time 219.14 seconds
Started Jun 07 07:41:26 PM PDT 24
Finished Jun 07 07:45:06 PM PDT 24
Peak memory 240100 kb
Host smart-f9f937d7-aecd-4eff-8842-aa5d42c02775
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=530636926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.530636926
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.4039897641
Short name T716
Test name
Test status
Simulation time 39538881 ps
CPU time 4.01 seconds
Started Jun 07 07:41:26 PM PDT 24
Finished Jun 07 07:41:31 PM PDT 24
Peak memory 240080 kb
Host smart-f2072458-11b7-485b-85b0-eb1e7ca235f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4039897641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.4039897641
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2726172071
Short name T196
Test name
Test status
Simulation time 1035607693 ps
CPU time 10.82 seconds
Started Jun 07 07:41:25 PM PDT 24
Finished Jun 07 07:41:37 PM PDT 24
Peak memory 250864 kb
Host smart-82757276-7c66-4a8c-b77f-9f9aa900a496
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726172071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2726172071
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1336214467
Short name T233
Test name
Test status
Simulation time 204649449 ps
CPU time 8.73 seconds
Started Jun 07 07:41:26 PM PDT 24
Finished Jun 07 07:41:36 PM PDT 24
Peak memory 235684 kb
Host smart-32a2460c-d2ab-46b1-87a9-ac4696571d5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1336214467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1336214467
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.220522530
Short name T818
Test name
Test status
Simulation time 11082560 ps
CPU time 1.6 seconds
Started Jun 07 07:41:26 PM PDT 24
Finished Jun 07 07:41:29 PM PDT 24
Peak memory 234684 kb
Host smart-700ac544-84ec-483d-9664-8ff7c5994a0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=220522530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.220522530
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2084201022
Short name T821
Test name
Test status
Simulation time 89536548 ps
CPU time 12.33 seconds
Started Jun 07 07:41:26 PM PDT 24
Finished Jun 07 07:41:40 PM PDT 24
Peak memory 248308 kb
Host smart-d47ffe73-841c-437e-85d2-b604ff1ed656
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2084201022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.2084201022
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3948832611
Short name T157
Test name
Test status
Simulation time 9537263231 ps
CPU time 328.29 seconds
Started Jun 07 07:41:28 PM PDT 24
Finished Jun 07 07:46:57 PM PDT 24
Peak memory 265240 kb
Host smart-c8e68fec-3072-47e8-8d09-8064b290111b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3948832611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3948832611
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1244434913
Short name T124
Test name
Test status
Simulation time 4719713091 ps
CPU time 383.37 seconds
Started Jun 07 07:41:25 PM PDT 24
Finished Jun 07 07:47:50 PM PDT 24
Peak memory 265128 kb
Host smart-5f7fb2a0-6cc9-437b-b7ea-0dc7164c7039
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244434913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1244434913
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2208835774
Short name T808
Test name
Test status
Simulation time 372525646 ps
CPU time 13.24 seconds
Started Jun 07 07:41:24 PM PDT 24
Finished Jun 07 07:41:39 PM PDT 24
Peak memory 252264 kb
Host smart-8ea653fa-7298-426b-b3ec-0fe0ddb13417
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2208835774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2208835774
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3116516878
Short name T353
Test name
Test status
Simulation time 6152684 ps
CPU time 1.35 seconds
Started Jun 07 07:42:20 PM PDT 24
Finished Jun 07 07:42:22 PM PDT 24
Peak memory 236696 kb
Host smart-06966e80-2d1e-4483-8668-8afbba8cd514
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3116516878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3116516878
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.222014132
Short name T765
Test name
Test status
Simulation time 14187174 ps
CPU time 1.58 seconds
Started Jun 07 07:42:20 PM PDT 24
Finished Jun 07 07:42:22 PM PDT 24
Peak memory 236700 kb
Host smart-1306e3bf-272e-4c93-8104-454b2f8caff3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=222014132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.222014132
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.4196150442
Short name T749
Test name
Test status
Simulation time 9008614 ps
CPU time 1.53 seconds
Started Jun 07 07:42:20 PM PDT 24
Finished Jun 07 07:42:22 PM PDT 24
Peak memory 235704 kb
Host smart-a7dc8c05-2e47-43bb-8b2a-9d22baaebc86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4196150442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.4196150442
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1892894510
Short name T787
Test name
Test status
Simulation time 15170062 ps
CPU time 1.32 seconds
Started Jun 07 07:42:22 PM PDT 24
Finished Jun 07 07:42:25 PM PDT 24
Peak memory 235780 kb
Host smart-883713ea-d60e-4282-9d9c-99fa699ee574
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1892894510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1892894510
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3848151143
Short name T746
Test name
Test status
Simulation time 14345677 ps
CPU time 1.75 seconds
Started Jun 07 07:42:21 PM PDT 24
Finished Jun 07 07:42:24 PM PDT 24
Peak memory 236692 kb
Host smart-dd3e391a-58fd-45a5-b7a4-43fbc0643399
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3848151143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3848151143
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.321703509
Short name T163
Test name
Test status
Simulation time 9733517 ps
CPU time 1.58 seconds
Started Jun 07 07:42:22 PM PDT 24
Finished Jun 07 07:42:26 PM PDT 24
Peak memory 235716 kb
Host smart-49486a1b-1c25-47ff-8c95-beb4cffd8c22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=321703509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.321703509
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1966309867
Short name T805
Test name
Test status
Simulation time 10139233 ps
CPU time 1.65 seconds
Started Jun 07 07:42:21 PM PDT 24
Finished Jun 07 07:42:23 PM PDT 24
Peak memory 235808 kb
Host smart-dc4684b8-87ff-4323-9f61-0ea677f889f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1966309867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.1966309867
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3892677317
Short name T772
Test name
Test status
Simulation time 9919482 ps
CPU time 1.64 seconds
Started Jun 07 07:42:31 PM PDT 24
Finished Jun 07 07:42:34 PM PDT 24
Peak memory 236720 kb
Host smart-23898f32-fc4a-47ce-875e-6650c2bf7962
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3892677317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3892677317
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2610877375
Short name T725
Test name
Test status
Simulation time 12355761 ps
CPU time 1.5 seconds
Started Jun 07 07:42:23 PM PDT 24
Finished Jun 07 07:42:26 PM PDT 24
Peak memory 236720 kb
Host smart-552d5fa2-bf0e-4ca7-9914-9b75dae2a4f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2610877375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2610877375
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.886315922
Short name T826
Test name
Test status
Simulation time 11733959 ps
CPU time 1.55 seconds
Started Jun 07 07:42:22 PM PDT 24
Finished Jun 07 07:42:25 PM PDT 24
Peak memory 235732 kb
Host smart-1b2cb429-c0bc-487d-bc5b-f7c8a0519a5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=886315922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.886315922
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3091839211
Short name T748
Test name
Test status
Simulation time 311756553 ps
CPU time 14.22 seconds
Started Jun 07 07:41:27 PM PDT 24
Finished Jun 07 07:41:43 PM PDT 24
Peak memory 243784 kb
Host smart-c7119c2e-69dd-47c9-ae3e-d6108fa16b97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091839211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3091839211
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.324013901
Short name T723
Test name
Test status
Simulation time 62052158 ps
CPU time 6.32 seconds
Started Jun 07 07:41:25 PM PDT 24
Finished Jun 07 07:41:33 PM PDT 24
Peak memory 236680 kb
Host smart-bf6fec89-0294-4529-9710-bcae48280332
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=324013901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.324013901
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1491767470
Short name T768
Test name
Test status
Simulation time 9546926 ps
CPU time 1.54 seconds
Started Jun 07 07:41:23 PM PDT 24
Finished Jun 07 07:41:26 PM PDT 24
Peak memory 234732 kb
Host smart-133cc5f5-a107-4c28-b712-e38d9e0db758
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1491767470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1491767470
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1651048260
Short name T184
Test name
Test status
Simulation time 171698387 ps
CPU time 24.04 seconds
Started Jun 07 07:41:28 PM PDT 24
Finished Jun 07 07:41:53 PM PDT 24
Peak memory 244856 kb
Host smart-116372da-11f7-4410-b7d4-6dae91520711
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1651048260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.1651048260
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2470980689
Short name T141
Test name
Test status
Simulation time 10218384056 ps
CPU time 334.52 seconds
Started Jun 07 07:41:26 PM PDT 24
Finished Jun 07 07:47:02 PM PDT 24
Peak memory 265104 kb
Host smart-203f18ef-9794-4a61-89e4-f3611f935b65
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470980689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.2470980689
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.657041896
Short name T234
Test name
Test status
Simulation time 305942343 ps
CPU time 23.12 seconds
Started Jun 07 07:41:25 PM PDT 24
Finished Jun 07 07:41:50 PM PDT 24
Peak memory 248348 kb
Host smart-481332dd-cd03-48e0-96bf-3e071c8e290e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=657041896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.657041896
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2786617892
Short name T824
Test name
Test status
Simulation time 160407934 ps
CPU time 7.59 seconds
Started Jun 07 07:41:38 PM PDT 24
Finished Jun 07 07:41:47 PM PDT 24
Peak memory 239732 kb
Host smart-39fd90b8-8ada-42af-a82c-2020a0c9680d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786617892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2786617892
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.4068271083
Short name T806
Test name
Test status
Simulation time 66316447 ps
CPU time 3.43 seconds
Started Jun 07 07:41:41 PM PDT 24
Finished Jun 07 07:41:45 PM PDT 24
Peak memory 236660 kb
Host smart-ba64123c-76c9-49d4-b0ed-4c9920ce6239
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4068271083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.4068271083
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.336301480
Short name T777
Test name
Test status
Simulation time 14171519 ps
CPU time 1.41 seconds
Started Jun 07 07:41:34 PM PDT 24
Finished Jun 07 07:41:36 PM PDT 24
Peak memory 235756 kb
Host smart-6970d720-ac09-4b18-838f-36f74fa52e37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=336301480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.336301480
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3356211811
Short name T775
Test name
Test status
Simulation time 1264006161 ps
CPU time 38.62 seconds
Started Jun 07 07:41:34 PM PDT 24
Finished Jun 07 07:42:14 PM PDT 24
Peak memory 243908 kb
Host smart-efe284a4-1644-469e-b510-ff102bd2bd0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3356211811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.3356211811
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3081130193
Short name T745
Test name
Test status
Simulation time 546065261 ps
CPU time 18.49 seconds
Started Jun 07 07:41:37 PM PDT 24
Finished Jun 07 07:41:57 PM PDT 24
Peak memory 248316 kb
Host smart-4b8b88fb-55cf-4544-9cb8-5752a312b5a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3081130193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3081130193
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.489374534
Short name T160
Test name
Test status
Simulation time 29901109 ps
CPU time 2.76 seconds
Started Jun 07 07:41:39 PM PDT 24
Finished Jun 07 07:41:43 PM PDT 24
Peak memory 236668 kb
Host smart-8bd70d8a-ff76-4418-a507-be8c20e043d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=489374534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.489374534
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.235010022
Short name T219
Test name
Test status
Simulation time 80953369 ps
CPU time 5.81 seconds
Started Jun 07 07:41:33 PM PDT 24
Finished Jun 07 07:41:40 PM PDT 24
Peak memory 237776 kb
Host smart-b11c8508-4a58-4a15-8724-754cc736fabd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235010022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.235010022
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1531631685
Short name T726
Test name
Test status
Simulation time 34368071 ps
CPU time 3.31 seconds
Started Jun 07 07:41:32 PM PDT 24
Finished Jun 07 07:41:37 PM PDT 24
Peak memory 236688 kb
Host smart-24edc209-89c0-44ed-b307-f5c0865dbe4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1531631685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1531631685
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1655956737
Short name T832
Test name
Test status
Simulation time 9813113 ps
CPU time 1.48 seconds
Started Jun 07 07:41:31 PM PDT 24
Finished Jun 07 07:41:34 PM PDT 24
Peak memory 234700 kb
Host smart-f98282f7-f333-4fdf-905b-f8e14400018f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1655956737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1655956737
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2642223871
Short name T812
Test name
Test status
Simulation time 169656212 ps
CPU time 12.85 seconds
Started Jun 07 07:41:39 PM PDT 24
Finished Jun 07 07:41:53 PM PDT 24
Peak memory 244868 kb
Host smart-c8ac1841-9e86-42cd-ae1f-d37106b13c01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2642223871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.2642223871
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.4121338384
Short name T827
Test name
Test status
Simulation time 8470137100 ps
CPU time 277.18 seconds
Started Jun 07 07:41:33 PM PDT 24
Finished Jun 07 07:46:12 PM PDT 24
Peak memory 269512 kb
Host smart-6db9bb8d-4839-4744-8e6a-f0bfed2a6190
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121338384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.4121338384
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3398776342
Short name T773
Test name
Test status
Simulation time 601121988 ps
CPU time 21.02 seconds
Started Jun 07 07:41:33 PM PDT 24
Finished Jun 07 07:41:56 PM PDT 24
Peak memory 255428 kb
Host smart-561ffccf-5a40-4ba3-bd3f-efbdf162920d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3398776342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3398776342
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3269453172
Short name T807
Test name
Test status
Simulation time 342574162 ps
CPU time 5.39 seconds
Started Jun 07 07:41:39 PM PDT 24
Finished Jun 07 07:41:45 PM PDT 24
Peak memory 237752 kb
Host smart-131b32cb-b4b6-4c88-95c4-c3a68d2a861f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269453172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3269453172
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1474543553
Short name T735
Test name
Test status
Simulation time 98431427 ps
CPU time 4.64 seconds
Started Jun 07 07:41:39 PM PDT 24
Finished Jun 07 07:41:45 PM PDT 24
Peak memory 235752 kb
Host smart-aa85f032-44b1-4a0e-a43d-bc849cad0cdf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1474543553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1474543553
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.315277908
Short name T820
Test name
Test status
Simulation time 15472425 ps
CPU time 1.81 seconds
Started Jun 07 07:41:40 PM PDT 24
Finished Jun 07 07:41:43 PM PDT 24
Peak memory 235776 kb
Host smart-b0d37858-bd94-41db-9770-397b94f3288f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=315277908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.315277908
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2400558401
Short name T741
Test name
Test status
Simulation time 478992390 ps
CPU time 12.61 seconds
Started Jun 07 07:41:41 PM PDT 24
Finished Jun 07 07:41:55 PM PDT 24
Peak memory 244864 kb
Host smart-a3528ada-d502-4f76-852b-0f2949909b28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2400558401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2400558401
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.4177305895
Short name T134
Test name
Test status
Simulation time 6313702677 ps
CPU time 308.36 seconds
Started Jun 07 07:41:32 PM PDT 24
Finished Jun 07 07:46:42 PM PDT 24
Peak memory 265176 kb
Host smart-59907465-05ca-4eec-a2ff-9c1039326121
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4177305895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.4177305895
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2884353960
Short name T356
Test name
Test status
Simulation time 53796375105 ps
CPU time 526.84 seconds
Started Jun 07 07:41:33 PM PDT 24
Finished Jun 07 07:50:21 PM PDT 24
Peak memory 265064 kb
Host smart-8d2ebfce-0d6b-4dd1-954e-1daf53a3f1ed
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884353960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2884353960
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.567770051
Short name T231
Test name
Test status
Simulation time 352520400 ps
CPU time 13.38 seconds
Started Jun 07 07:41:35 PM PDT 24
Finished Jun 07 07:41:49 PM PDT 24
Peak memory 248312 kb
Host smart-e0b405e2-2c79-4eb4-aa27-e8c52459c50d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=567770051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.567770051
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2078650963
Short name T778
Test name
Test status
Simulation time 78812357 ps
CPU time 5.84 seconds
Started Jun 07 07:41:42 PM PDT 24
Finished Jun 07 07:41:49 PM PDT 24
Peak memory 239984 kb
Host smart-9af7006f-901d-4032-adda-aa17a59e14c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078650963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2078650963
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3046774066
Short name T797
Test name
Test status
Simulation time 118578462 ps
CPU time 5.32 seconds
Started Jun 07 07:41:38 PM PDT 24
Finished Jun 07 07:41:45 PM PDT 24
Peak memory 236684 kb
Host smart-9be7ec9a-d707-408b-82bf-c5da3b6b613e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3046774066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3046774066
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3444236406
Short name T779
Test name
Test status
Simulation time 11528632 ps
CPU time 1.59 seconds
Started Jun 07 07:41:42 PM PDT 24
Finished Jun 07 07:41:44 PM PDT 24
Peak memory 236636 kb
Host smart-7ed75613-549b-4a06-a474-e0a24a3e5718
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3444236406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3444236406
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.458844089
Short name T729
Test name
Test status
Simulation time 734208877 ps
CPU time 27.12 seconds
Started Jun 07 07:41:39 PM PDT 24
Finished Jun 07 07:42:08 PM PDT 24
Peak memory 244820 kb
Host smart-5070a431-a1cb-48ee-a484-accd49c2d253
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=458844089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outs
tanding.458844089
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1072646306
Short name T783
Test name
Test status
Simulation time 597188183 ps
CPU time 9.14 seconds
Started Jun 07 07:41:40 PM PDT 24
Finished Jun 07 07:41:50 PM PDT 24
Peak memory 252432 kb
Host smart-15e856fb-32b7-489b-84fa-b122eeb6bb73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1072646306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1072646306
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3227992117
Short name T782
Test name
Test status
Simulation time 171477898 ps
CPU time 3.98 seconds
Started Jun 07 07:41:40 PM PDT 24
Finished Jun 07 07:41:45 PM PDT 24
Peak memory 236688 kb
Host smart-1b3cf562-5192-4549-8e8f-7061e5a6248c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3227992117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3227992117
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.2551922517
Short name T401
Test name
Test status
Simulation time 244369842982 ps
CPU time 2168.29 seconds
Started Jun 07 07:44:39 PM PDT 24
Finished Jun 07 08:20:49 PM PDT 24
Peak memory 288952 kb
Host smart-420ed108-a2b4-4715-8c12-412263e271c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551922517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2551922517
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.3781219372
Short name T556
Test name
Test status
Simulation time 184843074 ps
CPU time 11.45 seconds
Started Jun 07 07:44:40 PM PDT 24
Finished Jun 07 07:44:52 PM PDT 24
Peak memory 248712 kb
Host smart-e3be680f-002c-45ad-9614-4ae1b934139c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3781219372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3781219372
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.4292109240
Short name T472
Test name
Test status
Simulation time 44246441 ps
CPU time 4.01 seconds
Started Jun 07 07:44:42 PM PDT 24
Finished Jun 07 07:44:49 PM PDT 24
Peak memory 240476 kb
Host smart-eb18d42f-1288-4bb3-991b-b4a62025ba25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42921
09240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.4292109240
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2872089511
Short name T321
Test name
Test status
Simulation time 41914687767 ps
CPU time 2481.25 seconds
Started Jun 07 07:44:42 PM PDT 24
Finished Jun 07 08:26:05 PM PDT 24
Peak memory 281628 kb
Host smart-91a41795-12e0-42ad-8d2e-b59e3411b510
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872089511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2872089511
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.959567889
Short name T681
Test name
Test status
Simulation time 17063949548 ps
CPU time 1560.15 seconds
Started Jun 07 07:44:40 PM PDT 24
Finished Jun 07 08:10:42 PM PDT 24
Peak memory 289096 kb
Host smart-1888344c-ff8d-406c-b8b1-f464ef59118f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959567889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.959567889
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1113700442
Short name T685
Test name
Test status
Simulation time 134703902298 ps
CPU time 461.14 seconds
Started Jun 07 07:44:39 PM PDT 24
Finished Jun 07 07:52:21 PM PDT 24
Peak memory 248020 kb
Host smart-fd1c1cd8-ad83-46ae-b10c-8000c10546c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113700442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1113700442
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.306630803
Short name T66
Test name
Test status
Simulation time 258027207 ps
CPU time 14.54 seconds
Started Jun 07 07:44:41 PM PDT 24
Finished Jun 07 07:44:57 PM PDT 24
Peak memory 254400 kb
Host smart-1f1ca81b-d4ca-47f1-96b2-7d82383495c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30663
0803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.306630803
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.2261220477
Short name T500
Test name
Test status
Simulation time 1396198954 ps
CPU time 23.45 seconds
Started Jun 07 07:44:45 PM PDT 24
Finished Jun 07 07:45:10 PM PDT 24
Peak memory 255976 kb
Host smart-ddc70b17-7322-475a-af28-23de8153d240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22612
20477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2261220477
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3612546807
Short name T33
Test name
Test status
Simulation time 577447990 ps
CPU time 23.98 seconds
Started Jun 07 07:44:42 PM PDT 24
Finished Jun 07 07:45:08 PM PDT 24
Peak memory 270648 kb
Host smart-d5993ab5-7642-41c6-b397-51bde7b92312
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3612546807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3612546807
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.2773922704
Short name T50
Test name
Test status
Simulation time 1714808075 ps
CPU time 32.21 seconds
Started Jun 07 07:44:42 PM PDT 24
Finished Jun 07 07:45:16 PM PDT 24
Peak memory 248396 kb
Host smart-20623282-2542-4c0f-8ac0-ca24c34c8285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27739
22704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2773922704
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.4075378490
Short name T229
Test name
Test status
Simulation time 909081713 ps
CPU time 64.19 seconds
Started Jun 07 07:44:42 PM PDT 24
Finished Jun 07 07:45:48 PM PDT 24
Peak memory 248768 kb
Host smart-5320d9c4-440b-4c99-a8b9-3340594f613f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40753
78490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.4075378490
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.3894549137
Short name T78
Test name
Test status
Simulation time 153578939230 ps
CPU time 2073.83 seconds
Started Jun 07 07:44:40 PM PDT 24
Finished Jun 07 08:19:15 PM PDT 24
Peak memory 283716 kb
Host smart-62df690e-1ebf-4580-bdae-e063782f621e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894549137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.3894549137
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3867223007
Short name T655
Test name
Test status
Simulation time 41710809257 ps
CPU time 862.34 seconds
Started Jun 07 07:44:39 PM PDT 24
Finished Jun 07 07:59:03 PM PDT 24
Peak memory 269008 kb
Host smart-ed24a610-9ccf-4d74-85bf-2291435c8f0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867223007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3867223007
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.929643890
Short name T216
Test name
Test status
Simulation time 5542328476 ps
CPU time 18.52 seconds
Started Jun 07 07:44:41 PM PDT 24
Finished Jun 07 07:45:01 PM PDT 24
Peak memory 248780 kb
Host smart-b6dd65ce-2db3-49b3-9080-b6c28f4fab91
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=929643890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.929643890
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.3414600035
Short name T95
Test name
Test status
Simulation time 1226763035 ps
CPU time 119.95 seconds
Started Jun 07 07:44:41 PM PDT 24
Finished Jun 07 07:46:43 PM PDT 24
Peak memory 256700 kb
Host smart-0758317e-a0d3-4a88-bcdb-7cb123b31236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34146
00035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3414600035
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.219842658
Short name T572
Test name
Test status
Simulation time 691284929 ps
CPU time 30.21 seconds
Started Jun 07 07:44:42 PM PDT 24
Finished Jun 07 07:45:14 PM PDT 24
Peak memory 255080 kb
Host smart-c79a15c7-f2c5-49f4-bbb7-941f51c44030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21984
2658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.219842658
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3034765219
Short name T666
Test name
Test status
Simulation time 17239581516 ps
CPU time 1548.25 seconds
Started Jun 07 07:44:38 PM PDT 24
Finished Jun 07 08:10:28 PM PDT 24
Peak memory 286988 kb
Host smart-6849842f-908c-446b-9c81-603e811c0644
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034765219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3034765219
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.112297550
Short name T187
Test name
Test status
Simulation time 3126899155 ps
CPU time 124.99 seconds
Started Jun 07 07:44:40 PM PDT 24
Finished Jun 07 07:46:46 PM PDT 24
Peak memory 247208 kb
Host smart-08a5523d-e215-46ef-b729-39b62106b114
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112297550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.112297550
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.497442254
Short name T487
Test name
Test status
Simulation time 27588455 ps
CPU time 2.81 seconds
Started Jun 07 07:44:43 PM PDT 24
Finished Jun 07 07:44:48 PM PDT 24
Peak memory 240568 kb
Host smart-b2eea7a2-7e84-4779-964d-adb8d9430acc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49744
2254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.497442254
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.4037828212
Short name T28
Test name
Test status
Simulation time 263727988 ps
CPU time 14.25 seconds
Started Jun 07 07:44:42 PM PDT 24
Finished Jun 07 07:44:58 PM PDT 24
Peak memory 255348 kb
Host smart-f61d92e4-7020-477d-b89a-6ffaebf44071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40378
28212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.4037828212
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.2214316574
Short name T32
Test name
Test status
Simulation time 435072279 ps
CPU time 12.69 seconds
Started Jun 07 07:44:39 PM PDT 24
Finished Jun 07 07:44:53 PM PDT 24
Peak memory 270980 kb
Host smart-0af55410-4538-4b26-a008-45bbcb0670dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2214316574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.2214316574
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.529242028
Short name T442
Test name
Test status
Simulation time 5264673270 ps
CPU time 60.47 seconds
Started Jun 07 07:44:42 PM PDT 24
Finished Jun 07 07:45:45 PM PDT 24
Peak memory 256896 kb
Host smart-b3da1d83-2f5d-41a1-acab-f37411c68023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52924
2028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.529242028
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.97697822
Short name T614
Test name
Test status
Simulation time 796613644 ps
CPU time 57.71 seconds
Started Jun 07 07:44:41 PM PDT 24
Finished Jun 07 07:45:40 PM PDT 24
Peak memory 256912 kb
Host smart-a4647e20-10d6-4907-9a95-0e42d668a8b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97697
822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.97697822
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3287506
Short name T210
Test name
Test status
Simulation time 174218409 ps
CPU time 3.91 seconds
Started Jun 07 07:45:08 PM PDT 24
Finished Jun 07 07:45:14 PM PDT 24
Peak memory 248904 kb
Host smart-89ba35b2-d8f2-4751-bea7-f9ef27cd69e5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3287506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3287506
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2059399578
Short name T189
Test name
Test status
Simulation time 352833941 ps
CPU time 11.21 seconds
Started Jun 07 07:45:10 PM PDT 24
Finished Jun 07 07:45:23 PM PDT 24
Peak memory 248640 kb
Host smart-874d150e-1e5b-488e-a823-0857583f0dc5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2059399578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2059399578
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.1391638874
Short name T702
Test name
Test status
Simulation time 6255261347 ps
CPU time 140 seconds
Started Jun 07 07:45:13 PM PDT 24
Finished Jun 07 07:47:36 PM PDT 24
Peak memory 256884 kb
Host smart-4cd7a2ef-5aa8-4aab-ae15-156275e09b5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13916
38874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1391638874
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2474499979
Short name T454
Test name
Test status
Simulation time 1073985367 ps
CPU time 16.4 seconds
Started Jun 07 07:45:10 PM PDT 24
Finished Jun 07 07:45:29 PM PDT 24
Peak memory 252284 kb
Host smart-5878489d-dc14-4059-bc6a-01ddfb0c51e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24744
99979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2474499979
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2507420494
Short name T658
Test name
Test status
Simulation time 147953515322 ps
CPU time 2343.3 seconds
Started Jun 07 07:45:11 PM PDT 24
Finished Jun 07 08:24:18 PM PDT 24
Peak memory 287056 kb
Host smart-d965b2d4-d775-4210-8003-7f78aa6a4f8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507420494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2507420494
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3581695946
Short name T676
Test name
Test status
Simulation time 1234772354 ps
CPU time 34.72 seconds
Started Jun 07 07:45:10 PM PDT 24
Finished Jun 07 07:45:48 PM PDT 24
Peak memory 256712 kb
Host smart-a42054e4-3ab1-400b-8078-a79fd7656555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35816
95946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3581695946
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.1392139466
Short name T410
Test name
Test status
Simulation time 147407424 ps
CPU time 13.08 seconds
Started Jun 07 07:45:11 PM PDT 24
Finished Jun 07 07:45:28 PM PDT 24
Peak memory 255964 kb
Host smart-6310b696-2745-473e-9965-78f00d452ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13921
39466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1392139466
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.3342594487
Short name T357
Test name
Test status
Simulation time 1211844611 ps
CPU time 42.82 seconds
Started Jun 07 07:45:09 PM PDT 24
Finished Jun 07 07:45:55 PM PDT 24
Peak memory 248020 kb
Host smart-b2b492cf-1e35-4fd2-969d-038f17519306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33425
94487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3342594487
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.456194194
Short name T508
Test name
Test status
Simulation time 1992999653 ps
CPU time 33.87 seconds
Started Jun 07 07:45:09 PM PDT 24
Finished Jun 07 07:45:45 PM PDT 24
Peak memory 256956 kb
Host smart-68b7e3dc-8436-453e-b79e-963def2ef3b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45619
4194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.456194194
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.2831125418
Short name T677
Test name
Test status
Simulation time 12963875772 ps
CPU time 1274.59 seconds
Started Jun 07 07:45:12 PM PDT 24
Finished Jun 07 08:06:30 PM PDT 24
Peak memory 289720 kb
Host smart-147064cd-90b5-46bf-9e17-c9d420e114d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831125418 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.2831125418
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2404429130
Short name T202
Test name
Test status
Simulation time 130099828 ps
CPU time 4.1 seconds
Started Jun 07 07:45:17 PM PDT 24
Finished Jun 07 07:45:23 PM PDT 24
Peak memory 248812 kb
Host smart-11553606-af7f-439d-bbef-df3b016407f8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2404429130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2404429130
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.2920361819
Short name T47
Test name
Test status
Simulation time 151616451657 ps
CPU time 1452.84 seconds
Started Jun 07 07:45:11 PM PDT 24
Finished Jun 07 08:09:27 PM PDT 24
Peak memory 288840 kb
Host smart-bc7fa02a-42cb-4847-af13-e74c89b54cac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920361819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2920361819
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2307696598
Short name T592
Test name
Test status
Simulation time 1363252400 ps
CPU time 13.49 seconds
Started Jun 07 07:45:17 PM PDT 24
Finished Jun 07 07:45:33 PM PDT 24
Peak memory 240444 kb
Host smart-f0891772-7cac-4505-9d53-e2dc3e8cc69f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2307696598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2307696598
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1438911513
Short name T424
Test name
Test status
Simulation time 788050892 ps
CPU time 29.74 seconds
Started Jun 07 07:45:11 PM PDT 24
Finished Jun 07 07:45:44 PM PDT 24
Peak memory 256140 kb
Host smart-87a23d46-f167-47c1-b740-632c95d69583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14389
11513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1438911513
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.3395651607
Short name T661
Test name
Test status
Simulation time 1945239822 ps
CPU time 30.84 seconds
Started Jun 07 07:45:10 PM PDT 24
Finished Jun 07 07:45:44 PM PDT 24
Peak memory 248888 kb
Host smart-298fa765-354f-4c1d-9a3f-844b261b9bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33956
51607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3395651607
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.2497926569
Short name T323
Test name
Test status
Simulation time 45392638371 ps
CPU time 2458.56 seconds
Started Jun 07 07:45:20 PM PDT 24
Finished Jun 07 08:26:22 PM PDT 24
Peak memory 281084 kb
Host smart-a22d2563-687a-4ff2-b402-771cd4b66538
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497926569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2497926569
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2704873000
Short name T8
Test name
Test status
Simulation time 24517955582 ps
CPU time 1687.01 seconds
Started Jun 07 07:45:17 PM PDT 24
Finished Jun 07 08:13:25 PM PDT 24
Peak memory 288856 kb
Host smart-a094fe78-4f64-479a-8023-0a4bea8fd69c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704873000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2704873000
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.3425013729
Short name T565
Test name
Test status
Simulation time 2847218568 ps
CPU time 118.77 seconds
Started Jun 07 07:45:13 PM PDT 24
Finished Jun 07 07:47:15 PM PDT 24
Peak memory 248748 kb
Host smart-bdc6ce48-afab-4dbf-ac98-7efe43404f23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425013729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.3425013729
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.73723752
Short name T562
Test name
Test status
Simulation time 1601177773 ps
CPU time 23.9 seconds
Started Jun 07 07:45:11 PM PDT 24
Finished Jun 07 07:45:39 PM PDT 24
Peak memory 248680 kb
Host smart-d4f7bb01-ca9b-4f8e-9e8b-db43d1e7669f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73723
752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.73723752
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.94692064
Short name T485
Test name
Test status
Simulation time 746343681 ps
CPU time 53.11 seconds
Started Jun 07 07:45:09 PM PDT 24
Finished Jun 07 07:46:05 PM PDT 24
Peak memory 255672 kb
Host smart-62e9048b-3ff9-48f0-b864-58c6025f4809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94692
064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.94692064
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.2191632892
Short name T292
Test name
Test status
Simulation time 203307103 ps
CPU time 14.89 seconds
Started Jun 07 07:45:10 PM PDT 24
Finished Jun 07 07:45:27 PM PDT 24
Peak memory 255156 kb
Host smart-d72824e5-01e5-4af6-aa21-95861f568001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21916
32892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2191632892
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.2084695162
Short name T480
Test name
Test status
Simulation time 1176425921 ps
CPU time 38.12 seconds
Started Jun 07 07:45:12 PM PDT 24
Finished Jun 07 07:45:53 PM PDT 24
Peak memory 248724 kb
Host smart-e9f22caf-0774-4687-876c-6c7d5f584fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20846
95162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2084695162
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3752132520
Short name T237
Test name
Test status
Simulation time 17332474316 ps
CPU time 1581.92 seconds
Started Jun 07 07:45:18 PM PDT 24
Finished Jun 07 08:11:42 PM PDT 24
Peak memory 289100 kb
Host smart-cbf1130e-11d5-400c-ba13-f04fef04d50e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752132520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3752132520
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.985341862
Short name T207
Test name
Test status
Simulation time 17107884 ps
CPU time 2.61 seconds
Started Jun 07 07:45:20 PM PDT 24
Finished Jun 07 07:45:25 PM PDT 24
Peak memory 248924 kb
Host smart-f4520e57-22e4-4d02-9eb6-6fca31aa1c07
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=985341862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.985341862
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2784628595
Short name T534
Test name
Test status
Simulation time 89848541071 ps
CPU time 1404.56 seconds
Started Jun 07 07:45:18 PM PDT 24
Finished Jun 07 08:08:46 PM PDT 24
Peak memory 272632 kb
Host smart-6a7f6aa9-57fb-47c3-b32a-9d4cc1343fde
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784628595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2784628595
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.4096666211
Short name T632
Test name
Test status
Simulation time 2781888130 ps
CPU time 28.97 seconds
Started Jun 07 07:45:18 PM PDT 24
Finished Jun 07 07:45:49 PM PDT 24
Peak memory 248728 kb
Host smart-3d79db71-51ed-4eec-87ad-d4b0e0c8b4e2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4096666211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.4096666211
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3495756179
Short name T2
Test name
Test status
Simulation time 3737185885 ps
CPU time 211.98 seconds
Started Jun 07 07:45:19 PM PDT 24
Finished Jun 07 07:48:54 PM PDT 24
Peak memory 251692 kb
Host smart-67f86350-d79e-4b0f-9ac2-48b0fc66aed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34957
56179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3495756179
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2756873356
Short name T662
Test name
Test status
Simulation time 593659793 ps
CPU time 12.08 seconds
Started Jun 07 07:45:18 PM PDT 24
Finished Jun 07 07:45:32 PM PDT 24
Peak memory 254324 kb
Host smart-b42370ea-907d-442f-9314-5bd2f1067b53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27568
73356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2756873356
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.234487910
Short name T629
Test name
Test status
Simulation time 44114249901 ps
CPU time 1113.6 seconds
Started Jun 07 07:45:21 PM PDT 24
Finished Jun 07 08:03:57 PM PDT 24
Peak memory 273372 kb
Host smart-8e52ecc0-322e-4f8e-ac6e-5a6aaa5c6fbb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234487910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.234487910
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.629976789
Short name T434
Test name
Test status
Simulation time 193981855109 ps
CPU time 2444.25 seconds
Started Jun 07 07:45:19 PM PDT 24
Finished Jun 07 08:26:06 PM PDT 24
Peak memory 289308 kb
Host smart-f2a4d0a0-dabc-4540-9670-f3104407e0cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629976789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.629976789
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.4048483453
Short name T53
Test name
Test status
Simulation time 538858279 ps
CPU time 20.57 seconds
Started Jun 07 07:45:18 PM PDT 24
Finished Jun 07 07:45:40 PM PDT 24
Peak memory 256200 kb
Host smart-133c3fc4-1fa5-4a5a-953b-c685391b41d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40484
83453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.4048483453
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.836961210
Short name T674
Test name
Test status
Simulation time 14657248572 ps
CPU time 41.28 seconds
Started Jun 07 07:45:18 PM PDT 24
Finished Jun 07 07:46:03 PM PDT 24
Peak memory 256276 kb
Host smart-1b16b5eb-c99e-4e80-86c2-4cb7fab59125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83696
1210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.836961210
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3577027958
Short name T224
Test name
Test status
Simulation time 2182963549 ps
CPU time 28.71 seconds
Started Jun 07 07:45:18 PM PDT 24
Finished Jun 07 07:45:50 PM PDT 24
Peak memory 247476 kb
Host smart-b7994548-220b-46ea-9bae-f461f3f03156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35770
27958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3577027958
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.4255966233
Short name T435
Test name
Test status
Simulation time 559230898 ps
CPU time 30.38 seconds
Started Jun 07 07:45:18 PM PDT 24
Finished Jun 07 07:45:52 PM PDT 24
Peak memory 248748 kb
Host smart-0ba220d0-afcf-4d07-94fc-8c0996c7c73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42559
66233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.4255966233
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.1141024984
Short name T635
Test name
Test status
Simulation time 729651939 ps
CPU time 40.11 seconds
Started Jun 07 07:45:19 PM PDT 24
Finished Jun 07 07:46:02 PM PDT 24
Peak memory 255956 kb
Host smart-fd631495-a367-4323-bb9f-af90219c6364
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141024984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.1141024984
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.3650768033
Short name T458
Test name
Test status
Simulation time 12981951769 ps
CPU time 1152.63 seconds
Started Jun 07 07:45:19 PM PDT 24
Finished Jun 07 08:04:35 PM PDT 24
Peak memory 281940 kb
Host smart-ad51a3a2-67fe-44b9-8cb5-b2cd6ff08c16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650768033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3650768033
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3662890603
Short name T600
Test name
Test status
Simulation time 2885450567 ps
CPU time 10.69 seconds
Started Jun 07 07:45:21 PM PDT 24
Finished Jun 07 07:45:34 PM PDT 24
Peak memory 248804 kb
Host smart-a7741069-30e5-4e84-bfbd-251615db2c89
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3662890603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3662890603
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3605128634
Short name T432
Test name
Test status
Simulation time 4873412877 ps
CPU time 253.21 seconds
Started Jun 07 07:45:19 PM PDT 24
Finished Jun 07 07:49:35 PM PDT 24
Peak memory 256952 kb
Host smart-e24a517c-cbb8-4718-86f5-2ef4553a4c85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36051
28634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3605128634
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.3289579719
Short name T20
Test name
Test status
Simulation time 529696131 ps
CPU time 33.17 seconds
Started Jun 07 07:45:16 PM PDT 24
Finished Jun 07 07:45:51 PM PDT 24
Peak memory 255068 kb
Host smart-b9c333c3-fbc4-4aae-9e67-7e8ada9c5540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32895
79719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3289579719
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3761294073
Short name T444
Test name
Test status
Simulation time 16655176405 ps
CPU time 919.15 seconds
Started Jun 07 07:45:18 PM PDT 24
Finished Jun 07 08:00:40 PM PDT 24
Peak memory 267232 kb
Host smart-817e4688-e52b-49dd-98a4-8d90c193ab5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761294073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3761294073
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2761851278
Short name T482
Test name
Test status
Simulation time 13164870368 ps
CPU time 1495.92 seconds
Started Jun 07 07:45:18 PM PDT 24
Finished Jun 07 08:10:15 PM PDT 24
Peak memory 288696 kb
Host smart-fcfce4d6-405c-4eb8-a4f9-0b5756cb729a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761851278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2761851278
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2421321952
Short name T668
Test name
Test status
Simulation time 942525535 ps
CPU time 19.87 seconds
Started Jun 07 07:45:20 PM PDT 24
Finished Jun 07 07:45:43 PM PDT 24
Peak memory 248764 kb
Host smart-700768d3-7f52-4fb6-aae0-1f481fa96785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24213
21952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2421321952
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.653460880
Short name T486
Test name
Test status
Simulation time 514772775 ps
CPU time 13.23 seconds
Started Jun 07 07:45:18 PM PDT 24
Finished Jun 07 07:45:33 PM PDT 24
Peak memory 256068 kb
Host smart-b80ef94c-4bd8-4f5a-9890-8fb312c48039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65346
0880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.653460880
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2495723717
Short name T297
Test name
Test status
Simulation time 6130841138 ps
CPU time 57.9 seconds
Started Jun 07 07:45:19 PM PDT 24
Finished Jun 07 07:46:20 PM PDT 24
Peak memory 247984 kb
Host smart-4354c107-139a-450b-859c-39182078ecaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24957
23717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2495723717
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.2292230046
Short name T499
Test name
Test status
Simulation time 352442579 ps
CPU time 15.99 seconds
Started Jun 07 07:45:20 PM PDT 24
Finished Jun 07 07:45:39 PM PDT 24
Peak memory 248740 kb
Host smart-444c4648-d453-4bac-a088-725b8bc926c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22922
30046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.2292230046
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3899379449
Short name T206
Test name
Test status
Simulation time 155138260 ps
CPU time 3.86 seconds
Started Jun 07 07:45:29 PM PDT 24
Finished Jun 07 07:45:34 PM PDT 24
Peak memory 248896 kb
Host smart-ce4976e1-cddf-4d55-94db-f6163f5af60d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3899379449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3899379449
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.266927514
Short name T648
Test name
Test status
Simulation time 31806112989 ps
CPU time 2088.06 seconds
Started Jun 07 07:45:19 PM PDT 24
Finished Jun 07 08:20:10 PM PDT 24
Peak memory 287220 kb
Host smart-bd556a48-17c8-48fd-b7d4-a1b903a72b1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266927514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.266927514
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.3966421174
Short name T361
Test name
Test status
Simulation time 659462487 ps
CPU time 30.19 seconds
Started Jun 07 07:45:18 PM PDT 24
Finished Jun 07 07:45:51 PM PDT 24
Peak memory 240464 kb
Host smart-c802db0d-b643-49d9-80f7-ea3221f7af86
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3966421174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3966421174
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.274863916
Short name T489
Test name
Test status
Simulation time 1064938341 ps
CPU time 58.97 seconds
Started Jun 07 07:45:22 PM PDT 24
Finished Jun 07 07:46:23 PM PDT 24
Peak memory 256900 kb
Host smart-738a268b-9630-4149-a02b-c5b05eff93f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27486
3916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.274863916
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.4170997006
Short name T510
Test name
Test status
Simulation time 1254313028 ps
CPU time 24.06 seconds
Started Jun 07 07:45:20 PM PDT 24
Finished Jun 07 07:45:46 PM PDT 24
Peak memory 255752 kb
Host smart-bc4751e1-ec0e-4943-bd50-2db43580e92a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41709
97006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.4170997006
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.4044429462
Short name T412
Test name
Test status
Simulation time 10298970929 ps
CPU time 1085.44 seconds
Started Jun 07 07:45:21 PM PDT 24
Finished Jun 07 08:03:29 PM PDT 24
Peak memory 286320 kb
Host smart-e1946ca8-4623-4728-806f-32eac347b277
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044429462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.4044429462
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3164092376
Short name T307
Test name
Test status
Simulation time 6803753702 ps
CPU time 288.94 seconds
Started Jun 07 07:45:18 PM PDT 24
Finished Jun 07 07:50:09 PM PDT 24
Peak memory 255520 kb
Host smart-2e650564-96bf-4de7-9367-c6a2599b05a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164092376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3164092376
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.1899210953
Short name T358
Test name
Test status
Simulation time 256177184 ps
CPU time 23.3 seconds
Started Jun 07 07:45:19 PM PDT 24
Finished Jun 07 07:45:45 PM PDT 24
Peak memory 248700 kb
Host smart-450a6321-5c1c-483b-b7fa-b3859e38feb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18992
10953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.1899210953
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2496116428
Short name T445
Test name
Test status
Simulation time 1042821448 ps
CPU time 14.78 seconds
Started Jun 07 07:45:20 PM PDT 24
Finished Jun 07 07:45:38 PM PDT 24
Peak memory 255520 kb
Host smart-93145cae-3e74-4b12-8fc1-223b3ad1dd18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24961
16428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2496116428
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.291345362
Short name T414
Test name
Test status
Simulation time 2337759255 ps
CPU time 36.61 seconds
Started Jun 07 07:45:22 PM PDT 24
Finished Jun 07 07:46:01 PM PDT 24
Peak memory 256632 kb
Host smart-a9c388f3-b750-4b10-b62c-3616696badaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29134
5362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.291345362
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1808716666
Short name T584
Test name
Test status
Simulation time 215676156270 ps
CPU time 1764.71 seconds
Started Jun 07 07:45:18 PM PDT 24
Finished Jun 07 08:14:45 PM PDT 24
Peak memory 303260 kb
Host smart-c19ec6d4-99a0-4482-9411-fbb0641fe2e5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808716666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1808716666
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3193119753
Short name T198
Test name
Test status
Simulation time 31599127 ps
CPU time 2.61 seconds
Started Jun 07 07:45:26 PM PDT 24
Finished Jun 07 07:45:31 PM PDT 24
Peak memory 248876 kb
Host smart-862656af-e37e-4950-810c-e6c6b07c15c1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3193119753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3193119753
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.1478489382
Short name T597
Test name
Test status
Simulation time 13724462832 ps
CPU time 1237.74 seconds
Started Jun 07 07:45:26 PM PDT 24
Finished Jun 07 08:06:06 PM PDT 24
Peak memory 281472 kb
Host smart-8b94ff25-efe6-4897-9c37-f7d42ff84a5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478489382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1478489382
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.4237754730
Short name T431
Test name
Test status
Simulation time 3441103667 ps
CPU time 33.76 seconds
Started Jun 07 07:45:27 PM PDT 24
Finished Jun 07 07:46:02 PM PDT 24
Peak memory 248800 kb
Host smart-cb406c40-bfab-447d-812a-d4aa8d22b84c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4237754730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.4237754730
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.2706891406
Short name T425
Test name
Test status
Simulation time 257043003 ps
CPU time 15.34 seconds
Started Jun 07 07:45:25 PM PDT 24
Finished Jun 07 07:45:42 PM PDT 24
Peak memory 248636 kb
Host smart-1dc3f1eb-3fd4-4008-815d-b2a45bdc1000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27068
91406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.2706891406
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.66391573
Short name T580
Test name
Test status
Simulation time 1576774254 ps
CPU time 27.52 seconds
Started Jun 07 07:45:26 PM PDT 24
Finished Jun 07 07:45:56 PM PDT 24
Peak memory 255644 kb
Host smart-916e9b89-23c0-4213-9196-2ba356a6a663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66391
573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.66391573
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3770593887
Short name T471
Test name
Test status
Simulation time 10586241004 ps
CPU time 655.35 seconds
Started Jun 07 07:45:27 PM PDT 24
Finished Jun 07 07:56:25 PM PDT 24
Peak memory 265192 kb
Host smart-a6dd6f31-2468-4cc1-90e5-85b8b4198e04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770593887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3770593887
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3596641949
Short name T324
Test name
Test status
Simulation time 4366116325 ps
CPU time 171.59 seconds
Started Jun 07 07:45:26 PM PDT 24
Finished Jun 07 07:48:20 PM PDT 24
Peak memory 248224 kb
Host smart-72ecd0e5-0533-441c-aa1f-e1da7ab8b410
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596641949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3596641949
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1040848072
Short name T378
Test name
Test status
Simulation time 353371292 ps
CPU time 29.03 seconds
Started Jun 07 07:45:27 PM PDT 24
Finished Jun 07 07:45:58 PM PDT 24
Peak memory 248652 kb
Host smart-11c3a424-afc5-420f-a5da-0221af22d69d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10408
48072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1040848072
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.350921746
Short name T504
Test name
Test status
Simulation time 532712849 ps
CPU time 33.14 seconds
Started Jun 07 07:45:25 PM PDT 24
Finished Jun 07 07:46:00 PM PDT 24
Peak memory 247528 kb
Host smart-b978f893-c069-4a83-bf8e-a54f97b24d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35092
1746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.350921746
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1115312112
Short name T369
Test name
Test status
Simulation time 66031531 ps
CPU time 8.43 seconds
Started Jun 07 07:45:25 PM PDT 24
Finished Jun 07 07:45:35 PM PDT 24
Peak memory 249128 kb
Host smart-e515421f-625b-4283-95fe-36cf02aea341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11153
12112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1115312112
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1750346242
Short name T653
Test name
Test status
Simulation time 3894377944 ps
CPU time 53.22 seconds
Started Jun 07 07:45:27 PM PDT 24
Finished Jun 07 07:46:22 PM PDT 24
Peak memory 256992 kb
Host smart-929f9856-7d91-4726-9faa-8a69b3a5892a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17503
46242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1750346242
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.2116807010
Short name T416
Test name
Test status
Simulation time 20772386184 ps
CPU time 1415.98 seconds
Started Jun 07 07:45:33 PM PDT 24
Finished Jun 07 08:09:10 PM PDT 24
Peak memory 288880 kb
Host smart-16683d02-f178-4978-80c1-9bf07b1159f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116807010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.2116807010
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.3228744386
Short name T492
Test name
Test status
Simulation time 488389493 ps
CPU time 11.27 seconds
Started Jun 07 07:45:35 PM PDT 24
Finished Jun 07 07:45:48 PM PDT 24
Peak memory 248740 kb
Host smart-c99649b1-3cb3-4948-84c8-cc388577d1b8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3228744386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3228744386
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3728383662
Short name T460
Test name
Test status
Simulation time 361541222 ps
CPU time 4.08 seconds
Started Jun 07 07:45:25 PM PDT 24
Finished Jun 07 07:45:30 PM PDT 24
Peak memory 239440 kb
Host smart-6810c466-d6fe-4642-a425-a54638424651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37283
83662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3728383662
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.452547727
Short name T626
Test name
Test status
Simulation time 3984689445 ps
CPU time 62.9 seconds
Started Jun 07 07:45:28 PM PDT 24
Finished Jun 07 07:46:33 PM PDT 24
Peak memory 255824 kb
Host smart-c2edd65e-3482-4e15-a1d3-e6d8622bdb48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45254
7727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.452547727
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.4246967998
Short name T341
Test name
Test status
Simulation time 26941865396 ps
CPU time 1646.53 seconds
Started Jun 07 07:45:34 PM PDT 24
Finished Jun 07 08:13:03 PM PDT 24
Peak memory 289640 kb
Host smart-77117e96-a597-4c0b-863b-1ddb31960e77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246967998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.4246967998
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.3711115421
Short name T615
Test name
Test status
Simulation time 40298482669 ps
CPU time 1385.41 seconds
Started Jun 07 07:45:31 PM PDT 24
Finished Jun 07 08:08:37 PM PDT 24
Peak memory 272740 kb
Host smart-5f3589fe-8fd6-4830-bfc1-de06c13858e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711115421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3711115421
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1493598926
Short name T505
Test name
Test status
Simulation time 30111511247 ps
CPU time 309.9 seconds
Started Jun 07 07:45:33 PM PDT 24
Finished Jun 07 07:50:44 PM PDT 24
Peak memory 248496 kb
Host smart-ef9cb601-085f-4797-9bf7-7a5d0afada17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493598926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1493598926
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2865805229
Short name T16
Test name
Test status
Simulation time 529956859 ps
CPU time 23.56 seconds
Started Jun 07 07:45:26 PM PDT 24
Finished Jun 07 07:45:52 PM PDT 24
Peak memory 248684 kb
Host smart-914628d6-361f-4131-9b95-6f9694b16d20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28658
05229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2865805229
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3227289121
Short name T643
Test name
Test status
Simulation time 371690458 ps
CPU time 10.78 seconds
Started Jun 07 07:45:27 PM PDT 24
Finished Jun 07 07:45:40 PM PDT 24
Peak memory 248824 kb
Host smart-23af14d1-e4cc-4087-ab1a-376c4b7840e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32272
89121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3227289121
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3971515998
Short name T665
Test name
Test status
Simulation time 925944605 ps
CPU time 30.04 seconds
Started Jun 07 07:45:34 PM PDT 24
Finished Jun 07 07:46:06 PM PDT 24
Peak memory 256668 kb
Host smart-6d95e6cd-307c-4257-ac6b-2373ce86f203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39715
15998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3971515998
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1038584015
Short name T682
Test name
Test status
Simulation time 214854279 ps
CPU time 17.58 seconds
Started Jun 07 07:45:25 PM PDT 24
Finished Jun 07 07:45:44 PM PDT 24
Peak memory 256884 kb
Host smart-16f08337-47c5-453c-867b-14c8661c7cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10385
84015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1038584015
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.3027127947
Short name T476
Test name
Test status
Simulation time 5258132659 ps
CPU time 137.83 seconds
Started Jun 07 07:45:34 PM PDT 24
Finished Jun 07 07:47:54 PM PDT 24
Peak memory 256928 kb
Host smart-98ccefee-0de6-4dc0-b355-ee6324da8725
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027127947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.3027127947
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3367625957
Short name T3
Test name
Test status
Simulation time 44406905 ps
CPU time 3.85 seconds
Started Jun 07 07:45:47 PM PDT 24
Finished Jun 07 07:45:52 PM PDT 24
Peak memory 248900 kb
Host smart-cf5cb1a9-5771-4730-99f6-0bb54193ed72
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3367625957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3367625957
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3463389818
Short name T568
Test name
Test status
Simulation time 23294534762 ps
CPU time 1299.39 seconds
Started Jun 07 07:45:42 PM PDT 24
Finished Jun 07 08:07:23 PM PDT 24
Peak memory 289032 kb
Host smart-bd975b3d-34a6-40f4-85ab-a121737b8203
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463389818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3463389818
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.892450279
Short name T466
Test name
Test status
Simulation time 154049521 ps
CPU time 8.75 seconds
Started Jun 07 07:45:41 PM PDT 24
Finished Jun 07 07:45:52 PM PDT 24
Peak memory 248728 kb
Host smart-e6c35f65-41d8-4234-bc59-33095f399390
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=892450279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.892450279
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1876935713
Short name T453
Test name
Test status
Simulation time 10599613779 ps
CPU time 153.82 seconds
Started Jun 07 07:45:40 PM PDT 24
Finished Jun 07 07:48:16 PM PDT 24
Peak memory 249348 kb
Host smart-6d1afdb3-11c2-4867-87c2-3dbb8f300903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18769
35713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1876935713
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2869508630
Short name T376
Test name
Test status
Simulation time 375189748 ps
CPU time 14.29 seconds
Started Jun 07 07:45:43 PM PDT 24
Finished Jun 07 07:45:58 PM PDT 24
Peak memory 253776 kb
Host smart-36b0bbb1-078f-4daf-b92d-80562115b4f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28695
08630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2869508630
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3374697772
Short name T411
Test name
Test status
Simulation time 133332011175 ps
CPU time 2385.08 seconds
Started Jun 07 07:45:40 PM PDT 24
Finished Jun 07 08:25:28 PM PDT 24
Peak memory 281384 kb
Host smart-5e3f2715-8c24-4f08-8f14-063a96a3386b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374697772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3374697772
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3887777239
Short name T513
Test name
Test status
Simulation time 1018979899 ps
CPU time 26.91 seconds
Started Jun 07 07:45:31 PM PDT 24
Finished Jun 07 07:45:58 PM PDT 24
Peak memory 248736 kb
Host smart-c80e20d7-95c6-4f74-b3a2-9dff4df16a10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38877
77239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3887777239
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.842783899
Short name T663
Test name
Test status
Simulation time 843494439 ps
CPU time 42.71 seconds
Started Jun 07 07:45:39 PM PDT 24
Finished Jun 07 07:46:25 PM PDT 24
Peak memory 256616 kb
Host smart-2c44490e-f166-404b-904b-0e93fc77ed08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84278
3899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.842783899
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.2941851465
Short name T684
Test name
Test status
Simulation time 607188063 ps
CPU time 34.29 seconds
Started Jun 07 07:45:40 PM PDT 24
Finished Jun 07 07:46:17 PM PDT 24
Peak memory 248960 kb
Host smart-29d32ff5-0582-4462-8692-4975052becdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29418
51465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2941851465
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.2621123946
Short name T75
Test name
Test status
Simulation time 1476945961 ps
CPU time 32.55 seconds
Started Jun 07 07:45:34 PM PDT 24
Finished Jun 07 07:46:08 PM PDT 24
Peak memory 255716 kb
Host smart-92c30ad6-b35a-4973-b86e-f6f78d0d899d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26211
23946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2621123946
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.3531932385
Short name T507
Test name
Test status
Simulation time 5825128535 ps
CPU time 46.44 seconds
Started Jun 07 07:45:40 PM PDT 24
Finished Jun 07 07:46:29 PM PDT 24
Peak memory 256964 kb
Host smart-1aa6d073-ac30-4c34-9167-8acd06ef4408
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531932385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.3531932385
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1804451140
Short name T214
Test name
Test status
Simulation time 65481379 ps
CPU time 3.81 seconds
Started Jun 07 07:45:47 PM PDT 24
Finished Jun 07 07:45:53 PM PDT 24
Peak memory 248860 kb
Host smart-1e9b099f-9038-4d7d-bfde-9eb2068691fd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1804451140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1804451140
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1898852968
Short name T693
Test name
Test status
Simulation time 104636922240 ps
CPU time 1551.26 seconds
Started Jun 07 07:45:47 PM PDT 24
Finished Jun 07 08:11:40 PM PDT 24
Peak memory 282076 kb
Host smart-8de86d2e-1df6-438e-b2dc-75d9bf45e290
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898852968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1898852968
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.3565940093
Short name T593
Test name
Test status
Simulation time 5027044846 ps
CPU time 28.49 seconds
Started Jun 07 07:45:47 PM PDT 24
Finished Jun 07 07:46:17 PM PDT 24
Peak memory 248780 kb
Host smart-828ff843-7674-4975-a737-6e618be566b2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3565940093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3565940093
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1136827131
Short name T17
Test name
Test status
Simulation time 2232858701 ps
CPU time 34.37 seconds
Started Jun 07 07:45:47 PM PDT 24
Finished Jun 07 07:46:22 PM PDT 24
Peak memory 256204 kb
Host smart-6dc77f34-5cf7-488d-b095-8db65b8c2ba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11368
27131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1136827131
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.1574146012
Short name T403
Test name
Test status
Simulation time 3468034212 ps
CPU time 65.34 seconds
Started Jun 07 07:45:48 PM PDT 24
Finished Jun 07 07:46:55 PM PDT 24
Peak memory 255852 kb
Host smart-31489598-eb30-4250-94ea-df463478f00c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15741
46012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.1574146012
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.4287596074
Short name T348
Test name
Test status
Simulation time 518389336121 ps
CPU time 2522.15 seconds
Started Jun 07 07:45:48 PM PDT 24
Finished Jun 07 08:27:51 PM PDT 24
Peak memory 286588 kb
Host smart-47b0b6f7-75e8-4cf5-b7e2-2a190a2eb6a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287596074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.4287596074
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.3340064818
Short name T317
Test name
Test status
Simulation time 4702466016 ps
CPU time 195.31 seconds
Started Jun 07 07:45:46 PM PDT 24
Finished Jun 07 07:49:03 PM PDT 24
Peak memory 247212 kb
Host smart-624543e1-12fa-4722-bb5f-fb32f6eaf570
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340064818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.3340064818
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.3935985607
Short name T678
Test name
Test status
Simulation time 5181492540 ps
CPU time 31.04 seconds
Started Jun 07 07:45:47 PM PDT 24
Finished Jun 07 07:46:19 PM PDT 24
Peak memory 248712 kb
Host smart-eb5a267d-5a7c-4a1d-bca2-9c8cda7d0102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39359
85607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3935985607
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.170210483
Short name T18
Test name
Test status
Simulation time 367106224 ps
CPU time 30.4 seconds
Started Jun 07 07:45:48 PM PDT 24
Finished Jun 07 07:46:19 PM PDT 24
Peak memory 256084 kb
Host smart-b522625a-55e3-4120-96a2-edaea51ffee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17021
0483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.170210483
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.50377438
Short name T683
Test name
Test status
Simulation time 1410016561 ps
CPU time 19.27 seconds
Started Jun 07 07:45:46 PM PDT 24
Finished Jun 07 07:46:06 PM PDT 24
Peak memory 248752 kb
Host smart-2e146318-0ef5-4c8c-b12e-d6b508e58941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50377
438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.50377438
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.4004265361
Short name T270
Test name
Test status
Simulation time 37019791736 ps
CPU time 2370.14 seconds
Started Jun 07 07:45:47 PM PDT 24
Finished Jun 07 08:25:19 PM PDT 24
Peak memory 289060 kb
Host smart-9d63be00-a669-4010-9c75-15a041696f69
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004265361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.4004265361
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2879629877
Short name T208
Test name
Test status
Simulation time 54899819 ps
CPU time 2.99 seconds
Started Jun 07 07:45:58 PM PDT 24
Finished Jun 07 07:46:02 PM PDT 24
Peak memory 248840 kb
Host smart-98b26bb0-a90e-491f-a415-8c9f1cad872b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2879629877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2879629877
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2136030786
Short name T426
Test name
Test status
Simulation time 63161378719 ps
CPU time 1006.66 seconds
Started Jun 07 07:45:56 PM PDT 24
Finished Jun 07 08:02:44 PM PDT 24
Peak memory 272616 kb
Host smart-3ae7e208-9b42-4972-a8a6-c6255df93722
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136030786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2136030786
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.771173666
Short name T365
Test name
Test status
Simulation time 3820311631 ps
CPU time 44.14 seconds
Started Jun 07 07:45:55 PM PDT 24
Finished Jun 07 07:46:41 PM PDT 24
Peak memory 248780 kb
Host smart-2773fcb8-8a03-4658-840c-08394f611e31
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=771173666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.771173666
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.54843032
Short name T691
Test name
Test status
Simulation time 2136106406 ps
CPU time 67.22 seconds
Started Jun 07 07:45:55 PM PDT 24
Finished Jun 07 07:47:03 PM PDT 24
Peak memory 255832 kb
Host smart-35ee8adb-1cc9-4a0f-826d-b0e0d90d886b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54843
032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.54843032
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.1211442691
Short name T495
Test name
Test status
Simulation time 428776764 ps
CPU time 27.36 seconds
Started Jun 07 07:45:55 PM PDT 24
Finished Jun 07 07:46:24 PM PDT 24
Peak memory 255628 kb
Host smart-1504b339-1ed5-4ebe-ab68-ff3e193c2c13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12114
42691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1211442691
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2917120583
Short name T105
Test name
Test status
Simulation time 27778423456 ps
CPU time 1863.47 seconds
Started Jun 07 07:45:55 PM PDT 24
Finished Jun 07 08:17:00 PM PDT 24
Peak memory 281068 kb
Host smart-5adbb224-3beb-4a98-8bdd-e7c79ad58eb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917120583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2917120583
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.920906347
Short name T699
Test name
Test status
Simulation time 77644044745 ps
CPU time 1311.98 seconds
Started Jun 07 07:45:55 PM PDT 24
Finished Jun 07 08:07:49 PM PDT 24
Peak memory 273252 kb
Host smart-efa56778-d1fd-49d8-988a-90ed0e40ed43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920906347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.920906347
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.135289372
Short name T304
Test name
Test status
Simulation time 9751219228 ps
CPU time 415.42 seconds
Started Jun 07 07:45:54 PM PDT 24
Finished Jun 07 07:52:51 PM PDT 24
Peak memory 248452 kb
Host smart-e8ec29fa-a60d-4bd7-9e30-f69c2170c40b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135289372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.135289372
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.703036772
Short name T705
Test name
Test status
Simulation time 5817154065 ps
CPU time 34.72 seconds
Started Jun 07 07:45:57 PM PDT 24
Finished Jun 07 07:46:33 PM PDT 24
Peak memory 248788 kb
Host smart-abef9a36-aec4-409a-b411-7ca6898c008d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70303
6772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.703036772
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.4253327973
Short name T251
Test name
Test status
Simulation time 2521198235 ps
CPU time 73.2 seconds
Started Jun 07 07:45:54 PM PDT 24
Finished Jun 07 07:47:09 PM PDT 24
Peak memory 248112 kb
Host smart-85b36ed8-2e3b-4ee8-8852-5b635d503fdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42533
27973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.4253327973
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.173424826
Short name T291
Test name
Test status
Simulation time 2045491476 ps
CPU time 64.6 seconds
Started Jun 07 07:45:58 PM PDT 24
Finished Jun 07 07:47:04 PM PDT 24
Peak memory 256812 kb
Host smart-71b56082-f718-40b8-b68b-f39fa0cfe373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17342
4826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.173424826
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2230002636
Short name T490
Test name
Test status
Simulation time 1722362733 ps
CPU time 47.67 seconds
Started Jun 07 07:45:48 PM PDT 24
Finished Jun 07 07:46:37 PM PDT 24
Peak memory 256132 kb
Host smart-489fcb20-ef21-4156-a5ee-8c4d78cc34e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22300
02636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2230002636
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.2202752230
Short name T59
Test name
Test status
Simulation time 27746673038 ps
CPU time 2859.29 seconds
Started Jun 07 07:45:54 PM PDT 24
Finished Jun 07 08:33:34 PM PDT 24
Peak memory 321204 kb
Host smart-2d3c7b51-e1c5-45ea-885b-f7423ad00f36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202752230 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.2202752230
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2467025718
Short name T204
Test name
Test status
Simulation time 42099303 ps
CPU time 3.81 seconds
Started Jun 07 07:44:49 PM PDT 24
Finished Jun 07 07:44:55 PM PDT 24
Peak memory 248836 kb
Host smart-d21838ab-229c-4f40-a363-3624066b6f68
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2467025718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2467025718
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2538202689
Short name T429
Test name
Test status
Simulation time 41912077360 ps
CPU time 758.21 seconds
Started Jun 07 07:44:46 PM PDT 24
Finished Jun 07 07:57:26 PM PDT 24
Peak memory 273284 kb
Host smart-bb9257d1-599b-4a53-a0a0-15dd118902d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538202689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2538202689
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2445736082
Short name T628
Test name
Test status
Simulation time 5294870621 ps
CPU time 57.17 seconds
Started Jun 07 07:44:47 PM PDT 24
Finished Jun 07 07:45:47 PM PDT 24
Peak memory 240540 kb
Host smart-40d80a32-a982-4b44-9fc6-33e8890cf0be
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2445736082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2445736082
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2459516195
Short name T385
Test name
Test status
Simulation time 25865054059 ps
CPU time 216.34 seconds
Started Jun 07 07:44:47 PM PDT 24
Finished Jun 07 07:48:26 PM PDT 24
Peak memory 249928 kb
Host smart-92b55314-d7c5-42a9-b52a-8c9c38111a0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24595
16195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2459516195
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.4271744265
Short name T639
Test name
Test status
Simulation time 972967853 ps
CPU time 19.25 seconds
Started Jun 07 07:44:50 PM PDT 24
Finished Jun 07 07:45:11 PM PDT 24
Peak memory 254984 kb
Host smart-a6884cbd-3da4-499b-929e-97f8e1b785eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42717
44265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.4271744265
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.2055107918
Short name T346
Test name
Test status
Simulation time 18943372450 ps
CPU time 1157.38 seconds
Started Jun 07 07:44:47 PM PDT 24
Finished Jun 07 08:04:07 PM PDT 24
Peak memory 265112 kb
Host smart-859f5fdb-6142-464d-91f4-fff883f9eb8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055107918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2055107918
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2952720427
Short name T623
Test name
Test status
Simulation time 91471147238 ps
CPU time 1315.35 seconds
Started Jun 07 07:44:47 PM PDT 24
Finished Jun 07 08:06:45 PM PDT 24
Peak memory 272736 kb
Host smart-4d5d89a2-0985-46fd-92a7-3ed60269d868
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952720427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2952720427
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1014389346
Short name T548
Test name
Test status
Simulation time 491831582 ps
CPU time 15.25 seconds
Started Jun 07 07:44:46 PM PDT 24
Finished Jun 07 07:45:04 PM PDT 24
Peak memory 248840 kb
Host smart-5bf6df12-81ee-4441-ab56-de09189cc4f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10143
89346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1014389346
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.3498925797
Short name T501
Test name
Test status
Simulation time 299028894 ps
CPU time 5.52 seconds
Started Jun 07 07:44:48 PM PDT 24
Finished Jun 07 07:44:56 PM PDT 24
Peak memory 239368 kb
Host smart-48e96092-4450-4366-bc1d-8c2b3aba8f14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34989
25797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.3498925797
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.1459413968
Short name T12
Test name
Test status
Simulation time 1550423657 ps
CPU time 11.33 seconds
Started Jun 07 07:44:50 PM PDT 24
Finished Jun 07 07:45:03 PM PDT 24
Peak memory 275304 kb
Host smart-3e0771c3-a3e6-4b96-a145-873113e3ce91
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1459413968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.1459413968
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3601413460
Short name T578
Test name
Test status
Simulation time 484353462 ps
CPU time 29.89 seconds
Started Jun 07 07:44:49 PM PDT 24
Finished Jun 07 07:45:21 PM PDT 24
Peak memory 256920 kb
Host smart-2184ebdc-1672-471b-aa66-b1b604a0eefb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36014
13460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3601413460
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.3479544790
Short name T679
Test name
Test status
Simulation time 18768796987 ps
CPU time 1719.29 seconds
Started Jun 07 07:44:45 PM PDT 24
Finished Jun 07 08:13:26 PM PDT 24
Peak memory 299104 kb
Host smart-c5034778-bfdb-4d88-bab0-9e0d9c62ee99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479544790 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.3479544790
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.2848536473
Short name T470
Test name
Test status
Simulation time 43748540814 ps
CPU time 2543.98 seconds
Started Jun 07 07:46:10 PM PDT 24
Finished Jun 07 08:28:35 PM PDT 24
Peak memory 281560 kb
Host smart-ca2657bf-5691-47c7-b74b-9c59e03c8d78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848536473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2848536473
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1433026626
Short name T451
Test name
Test status
Simulation time 1517061957 ps
CPU time 44.58 seconds
Started Jun 07 07:45:54 PM PDT 24
Finished Jun 07 07:46:39 PM PDT 24
Peak memory 248944 kb
Host smart-f485291d-2cce-4322-b4c0-63f3d9d23f02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14330
26626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1433026626
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.2834991889
Short name T690
Test name
Test status
Simulation time 34403478 ps
CPU time 5.92 seconds
Started Jun 07 07:45:55 PM PDT 24
Finished Jun 07 07:46:02 PM PDT 24
Peak memory 249900 kb
Host smart-696187e4-406f-425d-9ec5-e57b02b502c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28349
91889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.2834991889
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1221900427
Short name T121
Test name
Test status
Simulation time 136901801059 ps
CPU time 1209.11 seconds
Started Jun 07 07:46:05 PM PDT 24
Finished Jun 07 08:06:17 PM PDT 24
Peak memory 288836 kb
Host smart-5b7154f3-f84f-470e-9432-efa68b4f4a35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221900427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1221900427
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.5595755
Short name T713
Test name
Test status
Simulation time 12497628281 ps
CPU time 1026.39 seconds
Started Jun 07 07:46:07 PM PDT 24
Finished Jun 07 08:03:15 PM PDT 24
Peak memory 272764 kb
Host smart-77710be4-4ab7-4846-9189-0d38916b1b19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5595755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.5595755
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.4089421579
Short name T302
Test name
Test status
Simulation time 15497617317 ps
CPU time 611.39 seconds
Started Jun 07 07:46:05 PM PDT 24
Finished Jun 07 07:56:19 PM PDT 24
Peak memory 256508 kb
Host smart-0aa74006-c0ce-4744-95fa-7890d4b05768
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089421579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.4089421579
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.2708006440
Short name T195
Test name
Test status
Simulation time 1144346102 ps
CPU time 41.54 seconds
Started Jun 07 07:45:54 PM PDT 24
Finished Jun 07 07:46:37 PM PDT 24
Peak memory 256192 kb
Host smart-a15b7402-298d-4a6d-8d31-54bad20beff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27080
06440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2708006440
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1510244653
Short name T488
Test name
Test status
Simulation time 981016232 ps
CPU time 50.05 seconds
Started Jun 07 07:45:56 PM PDT 24
Finished Jun 07 07:46:47 PM PDT 24
Peak memory 255548 kb
Host smart-32a8144f-445b-4333-8d54-98ce59c405a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15102
44653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1510244653
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1578967711
Short name T31
Test name
Test status
Simulation time 718353631 ps
CPU time 27.86 seconds
Started Jun 07 07:45:57 PM PDT 24
Finished Jun 07 07:46:26 PM PDT 24
Peak memory 248744 kb
Host smart-81c1223e-15dc-48ef-b1af-abf6cb685483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15789
67711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1578967711
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1628160592
Short name T477
Test name
Test status
Simulation time 671722821 ps
CPU time 35.45 seconds
Started Jun 07 07:45:53 PM PDT 24
Finished Jun 07 07:46:29 PM PDT 24
Peak memory 256900 kb
Host smart-83f92431-cfd0-4fb5-b940-95d0c889ab3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16281
60592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1628160592
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.4145237865
Short name T595
Test name
Test status
Simulation time 4522929775 ps
CPU time 167.67 seconds
Started Jun 07 07:46:06 PM PDT 24
Finished Jun 07 07:48:56 PM PDT 24
Peak memory 252776 kb
Host smart-c1884acd-5d25-412e-aee5-983d1b050666
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145237865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.4145237865
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.4013146884
Short name T609
Test name
Test status
Simulation time 52038174067 ps
CPU time 1809.19 seconds
Started Jun 07 07:46:05 PM PDT 24
Finished Jun 07 08:16:16 PM PDT 24
Peak memory 281264 kb
Host smart-bb2e8daf-c74d-479c-91a4-3d9a797b078e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013146884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.4013146884
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.829827899
Short name T45
Test name
Test status
Simulation time 347045477 ps
CPU time 21.52 seconds
Started Jun 07 07:46:06 PM PDT 24
Finished Jun 07 07:46:30 PM PDT 24
Peak memory 256612 kb
Host smart-e7b12020-284a-4eae-9a6e-e48835fe5390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82982
7899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.829827899
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.981077955
Short name T576
Test name
Test status
Simulation time 2613559131 ps
CPU time 38.24 seconds
Started Jun 07 07:46:04 PM PDT 24
Finished Jun 07 07:46:43 PM PDT 24
Peak memory 248920 kb
Host smart-6f3f7c55-0a92-452f-86d0-c1f7afd0af3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98107
7955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.981077955
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.3537095722
Short name T344
Test name
Test status
Simulation time 21059901746 ps
CPU time 1665.79 seconds
Started Jun 07 07:46:07 PM PDT 24
Finished Jun 07 08:13:54 PM PDT 24
Peak memory 288688 kb
Host smart-d06098fe-33ed-4cda-9f85-c26f5635cbde
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537095722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3537095722
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.4051484283
Short name T651
Test name
Test status
Simulation time 42305065882 ps
CPU time 2515.7 seconds
Started Jun 07 07:46:06 PM PDT 24
Finished Jun 07 08:28:04 PM PDT 24
Peak memory 273124 kb
Host smart-6ba1982b-85d2-40e0-af6f-6d58727533ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051484283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.4051484283
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.2854096897
Short name T586
Test name
Test status
Simulation time 30831340463 ps
CPU time 332.74 seconds
Started Jun 07 07:46:05 PM PDT 24
Finished Jun 07 07:51:40 PM PDT 24
Peak memory 248368 kb
Host smart-f126749a-f7f4-4fee-9bc3-396e026bcadd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854096897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2854096897
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2887592820
Short name T571
Test name
Test status
Simulation time 2842285112 ps
CPU time 51.12 seconds
Started Jun 07 07:46:05 PM PDT 24
Finished Jun 07 07:46:59 PM PDT 24
Peak memory 248784 kb
Host smart-51c4e67e-bf18-4348-916f-29f5962bcfca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28875
92820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2887592820
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3405804813
Short name T552
Test name
Test status
Simulation time 3669095333 ps
CPU time 29.25 seconds
Started Jun 07 07:46:05 PM PDT 24
Finished Jun 07 07:46:36 PM PDT 24
Peak memory 256260 kb
Host smart-d24a0d24-fe93-4608-9b00-d6f4357639f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34058
04813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3405804813
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.3588096157
Short name T381
Test name
Test status
Simulation time 3198335608 ps
CPU time 49.88 seconds
Started Jun 07 07:46:06 PM PDT 24
Finished Jun 07 07:46:58 PM PDT 24
Peak memory 256196 kb
Host smart-a2ba2290-7b68-4b0d-8e80-271c6d7a237e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35880
96157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3588096157
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.1895516081
Short name T399
Test name
Test status
Simulation time 2382163567 ps
CPU time 37.74 seconds
Started Jun 07 07:46:06 PM PDT 24
Finished Jun 07 07:46:46 PM PDT 24
Peak memory 255808 kb
Host smart-f3c64409-0685-4245-bd33-7acaa3294770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18955
16081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1895516081
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3954477025
Short name T409
Test name
Test status
Simulation time 126850699264 ps
CPU time 2763.76 seconds
Started Jun 07 07:46:06 PM PDT 24
Finished Jun 07 08:32:12 PM PDT 24
Peak memory 299908 kb
Host smart-00fe673b-6579-4521-a6e8-885691e517b0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954477025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3954477025
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.654057038
Short name T687
Test name
Test status
Simulation time 245085399807 ps
CPU time 3893.3 seconds
Started Jun 07 07:46:05 PM PDT 24
Finished Jun 07 08:51:01 PM PDT 24
Peak memory 339080 kb
Host smart-4a453ce2-5dc0-4def-b2eb-43c98f37cbf7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654057038 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.654057038
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1258664610
Short name T673
Test name
Test status
Simulation time 185977814964 ps
CPU time 2705.52 seconds
Started Jun 07 07:46:17 PM PDT 24
Finished Jun 07 08:31:24 PM PDT 24
Peak memory 288296 kb
Host smart-7e2f114b-7318-4e00-8218-d2af31e2be34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258664610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1258664610
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.3529553294
Short name T590
Test name
Test status
Simulation time 3782806571 ps
CPU time 231.58 seconds
Started Jun 07 07:46:15 PM PDT 24
Finished Jun 07 07:50:08 PM PDT 24
Peak memory 256804 kb
Host smart-e9a681f5-d477-42c2-a3f4-30b6c26fbda7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35295
53294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3529553294
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2403145839
Short name T474
Test name
Test status
Simulation time 164560931 ps
CPU time 5.56 seconds
Started Jun 07 07:46:15 PM PDT 24
Finished Jun 07 07:46:22 PM PDT 24
Peak memory 248652 kb
Host smart-c10e77ea-c829-4046-beb3-e3935a23acc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24031
45839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2403145839
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.2996154223
Short name T332
Test name
Test status
Simulation time 14344676801 ps
CPU time 1441.42 seconds
Started Jun 07 07:46:19 PM PDT 24
Finished Jun 07 08:10:22 PM PDT 24
Peak memory 288296 kb
Host smart-19c293d0-5588-4847-b0f2-4af2839c85a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996154223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2996154223
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3962485548
Short name T491
Test name
Test status
Simulation time 215182432384 ps
CPU time 2442 seconds
Started Jun 07 07:46:14 PM PDT 24
Finished Jun 07 08:26:58 PM PDT 24
Peak memory 285124 kb
Host smart-fa8ac3d6-e671-4bdd-a15e-5cf4e06c874a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962485548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3962485548
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.616629469
Short name T315
Test name
Test status
Simulation time 29143246659 ps
CPU time 258.03 seconds
Started Jun 07 07:46:16 PM PDT 24
Finished Jun 07 07:50:35 PM PDT 24
Peak memory 248372 kb
Host smart-bf208a2e-7a5b-4a6c-b5a7-4a86437e797a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616629469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.616629469
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.3408709529
Short name T39
Test name
Test status
Simulation time 218182064 ps
CPU time 17.46 seconds
Started Jun 07 07:46:16 PM PDT 24
Finished Jun 07 07:46:36 PM PDT 24
Peak memory 256156 kb
Host smart-00e9e343-ce8f-4efa-af1a-ff52a1786965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34087
09529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3408709529
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.580109028
Short name T29
Test name
Test status
Simulation time 2850722676 ps
CPU time 52.01 seconds
Started Jun 07 07:46:16 PM PDT 24
Finished Jun 07 07:47:10 PM PDT 24
Peak memory 256896 kb
Host smart-eb973751-66fd-4fc0-a34d-60eb79941e89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58010
9028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.580109028
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.2417935614
Short name T281
Test name
Test status
Simulation time 568764601 ps
CPU time 19.01 seconds
Started Jun 07 07:46:30 PM PDT 24
Finished Jun 07 07:46:51 PM PDT 24
Peak memory 248968 kb
Host smart-65422511-4c6c-4c10-b0a9-655d99e45f40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24179
35614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.2417935614
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.535837607
Short name T475
Test name
Test status
Simulation time 1913642936 ps
CPU time 38.34 seconds
Started Jun 07 07:46:29 PM PDT 24
Finished Jun 07 07:47:10 PM PDT 24
Peak memory 248712 kb
Host smart-dae020c1-47fe-4386-a3de-27dbad9b2e68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53583
7607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.535837607
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.3379201310
Short name T443
Test name
Test status
Simulation time 73246774349 ps
CPU time 1601.34 seconds
Started Jun 07 07:46:14 PM PDT 24
Finished Jun 07 08:12:57 PM PDT 24
Peak memory 289020 kb
Host smart-add31a4b-47b6-457f-b010-1384aaaa62a2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379201310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.3379201310
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.3673156548
Short name T218
Test name
Test status
Simulation time 210998127593 ps
CPU time 2630.19 seconds
Started Jun 07 07:46:15 PM PDT 24
Finished Jun 07 08:30:07 PM PDT 24
Peak memory 289264 kb
Host smart-d193c874-2856-48e7-a1b5-72d2ca5792bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673156548 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.3673156548
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.625164596
Short name T89
Test name
Test status
Simulation time 50611432842 ps
CPU time 2868.55 seconds
Started Jun 07 07:46:13 PM PDT 24
Finished Jun 07 08:34:03 PM PDT 24
Peak memory 288332 kb
Host smart-caed5388-a4bc-46fb-a72c-30c79629e29f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625164596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.625164596
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.3505889149
Short name T377
Test name
Test status
Simulation time 85588157 ps
CPU time 13.31 seconds
Started Jun 07 07:46:30 PM PDT 24
Finished Jun 07 07:46:46 PM PDT 24
Peak memory 256816 kb
Host smart-0057be2a-7466-44cd-9dc3-6e2a5f379029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35058
89149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3505889149
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.3123484500
Short name T557
Test name
Test status
Simulation time 1511941441 ps
CPU time 29.3 seconds
Started Jun 07 07:46:14 PM PDT 24
Finished Jun 07 07:46:44 PM PDT 24
Peak memory 255116 kb
Host smart-01cc58aa-9c54-4304-bbf8-579fac394bcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31234
84500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.3123484500
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.4079328068
Short name T258
Test name
Test status
Simulation time 30470613474 ps
CPU time 1227.12 seconds
Started Jun 07 07:46:18 PM PDT 24
Finished Jun 07 08:06:46 PM PDT 24
Peak memory 283592 kb
Host smart-5d16da9a-d922-4d3c-9216-9ffc7bde3b81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079328068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.4079328068
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2885269644
Short name T375
Test name
Test status
Simulation time 61334706224 ps
CPU time 1206.32 seconds
Started Jun 07 07:46:19 PM PDT 24
Finished Jun 07 08:06:26 PM PDT 24
Peak memory 287684 kb
Host smart-2cb8e0f7-d227-405e-89b4-dfd6671399c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885269644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2885269644
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3734909309
Short name T309
Test name
Test status
Simulation time 8961301725 ps
CPU time 372.27 seconds
Started Jun 07 07:46:18 PM PDT 24
Finished Jun 07 07:52:32 PM PDT 24
Peak memory 254968 kb
Host smart-561d0e94-29b7-4cae-83c2-7005ad4043f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734909309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3734909309
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.401223934
Short name T542
Test name
Test status
Simulation time 756119017 ps
CPU time 14.1 seconds
Started Jun 07 07:46:19 PM PDT 24
Finished Jun 07 07:46:34 PM PDT 24
Peak memory 248712 kb
Host smart-8b31d155-8ccf-4039-ab69-851575ea68c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40122
3934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.401223934
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.2113909669
Short name T711
Test name
Test status
Simulation time 2202967179 ps
CPU time 32.97 seconds
Started Jun 07 07:46:16 PM PDT 24
Finished Jun 07 07:46:50 PM PDT 24
Peak memory 255532 kb
Host smart-c05a82b6-21d7-4906-a62f-7218ac27e421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21139
09669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.2113909669
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.626746490
Short name T428
Test name
Test status
Simulation time 236749658 ps
CPU time 15.34 seconds
Started Jun 07 07:46:16 PM PDT 24
Finished Jun 07 07:46:32 PM PDT 24
Peak memory 248880 kb
Host smart-e4d55150-94b1-4f6f-a73c-8c9fe65fa5e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62674
6490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.626746490
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.4228731311
Short name T579
Test name
Test status
Simulation time 53247142 ps
CPU time 4.3 seconds
Started Jun 07 07:46:14 PM PDT 24
Finished Jun 07 07:46:20 PM PDT 24
Peak memory 240456 kb
Host smart-6f59cc3a-d3d6-4adf-a1f1-45b31b5ae3df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42287
31311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.4228731311
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2721227977
Short name T274
Test name
Test status
Simulation time 152183511509 ps
CPU time 1451.45 seconds
Started Jun 07 07:46:29 PM PDT 24
Finished Jun 07 08:10:42 PM PDT 24
Peak memory 289556 kb
Host smart-09bf176b-1546-4b20-8a76-e89f42ea868e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721227977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2721227977
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.3791404682
Short name T58
Test name
Test status
Simulation time 179076712089 ps
CPU time 8037.07 seconds
Started Jun 07 07:46:30 PM PDT 24
Finished Jun 07 10:00:30 PM PDT 24
Peak memory 354404 kb
Host smart-7de6368c-7cf4-4cbe-9b70-f7ab083ed9b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791404682 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.3791404682
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.3771867943
Short name T90
Test name
Test status
Simulation time 14195603323 ps
CPU time 1099.83 seconds
Started Jun 07 07:46:29 PM PDT 24
Finished Jun 07 08:04:51 PM PDT 24
Peak memory 288776 kb
Host smart-addd99af-1547-47d3-ba19-7bed824ca98c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771867943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3771867943
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.706698620
Short name T520
Test name
Test status
Simulation time 825759753 ps
CPU time 33.87 seconds
Started Jun 07 07:46:30 PM PDT 24
Finished Jun 07 07:47:07 PM PDT 24
Peak memory 256112 kb
Host smart-cb8ca421-21b9-4f89-a74b-ab203a641bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70669
8620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.706698620
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2322805391
Short name T582
Test name
Test status
Simulation time 465889345 ps
CPU time 43.66 seconds
Started Jun 07 07:46:30 PM PDT 24
Finished Jun 07 07:47:16 PM PDT 24
Peak memory 255060 kb
Host smart-63c4b2c7-4825-4ae4-9102-398c972187dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23228
05391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2322805391
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.3708601397
Short name T7
Test name
Test status
Simulation time 12302452261 ps
CPU time 796.67 seconds
Started Jun 07 07:46:29 PM PDT 24
Finished Jun 07 07:59:47 PM PDT 24
Peak memory 265100 kb
Host smart-a2cd2b04-42b8-4e47-b126-72f2d90187b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708601397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.3708601397
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.3294724755
Short name T452
Test name
Test status
Simulation time 7940715730 ps
CPU time 808.83 seconds
Started Jun 07 07:46:20 PM PDT 24
Finished Jun 07 07:59:50 PM PDT 24
Peak memory 272352 kb
Host smart-b4e1ab33-5d6b-4167-80d6-34a61be82112
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294724755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3294724755
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2588376738
Short name T325
Test name
Test status
Simulation time 9384143409 ps
CPU time 348.45 seconds
Started Jun 07 07:46:29 PM PDT 24
Finished Jun 07 07:52:20 PM PDT 24
Peak memory 247204 kb
Host smart-48344eca-fd35-4263-a9ad-28fcb410b979
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588376738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2588376738
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1170130218
Short name T100
Test name
Test status
Simulation time 3153093966 ps
CPU time 50.34 seconds
Started Jun 07 07:46:19 PM PDT 24
Finished Jun 07 07:47:10 PM PDT 24
Peak memory 256920 kb
Host smart-6187a237-ce35-4ac4-9414-50f857ff6af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11701
30218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1170130218
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2924604888
Short name T516
Test name
Test status
Simulation time 423642628 ps
CPU time 32.27 seconds
Started Jun 07 07:46:18 PM PDT 24
Finished Jun 07 07:46:52 PM PDT 24
Peak memory 256836 kb
Host smart-33bb4645-8c44-4268-8c76-5d9cee756da0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29246
04888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2924604888
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.2510623175
Short name T287
Test name
Test status
Simulation time 593970424 ps
CPU time 12.59 seconds
Started Jun 07 07:46:14 PM PDT 24
Finished Jun 07 07:46:28 PM PDT 24
Peak memory 248628 kb
Host smart-c38fade8-27a3-4e15-9667-c1e4e858037f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25106
23175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.2510623175
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3057735364
Short name T188
Test name
Test status
Simulation time 1190339859 ps
CPU time 17 seconds
Started Jun 07 07:46:18 PM PDT 24
Finished Jun 07 07:46:36 PM PDT 24
Peak memory 256900 kb
Host smart-a3a6b372-064e-42a0-a9b0-dc52567fdfde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30577
35364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3057735364
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.113829685
Short name T250
Test name
Test status
Simulation time 42705998436 ps
CPU time 1980.76 seconds
Started Jun 07 07:46:20 PM PDT 24
Finished Jun 07 08:19:22 PM PDT 24
Peak memory 305576 kb
Host smart-575d37b6-426d-4852-8fa2-e49e3636b6d0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113829685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_han
dler_stress_all.113829685
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.440645825
Short name T640
Test name
Test status
Simulation time 126347890588 ps
CPU time 7590.88 seconds
Started Jun 07 07:46:22 PM PDT 24
Finished Jun 07 09:52:56 PM PDT 24
Peak memory 338864 kb
Host smart-5eb12b01-126d-407b-bbeb-1b0bcc2b1e2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440645825 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.440645825
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.1772770003
Short name T589
Test name
Test status
Simulation time 112312945089 ps
CPU time 2030.75 seconds
Started Jun 07 07:46:21 PM PDT 24
Finished Jun 07 08:20:13 PM PDT 24
Peak memory 273352 kb
Host smart-5ca2493b-4b9f-443c-b8e7-c6a82918e7b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772770003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1772770003
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.894086869
Short name T540
Test name
Test status
Simulation time 36512121638 ps
CPU time 141.4 seconds
Started Jun 07 07:46:22 PM PDT 24
Finished Jun 07 07:48:45 PM PDT 24
Peak memory 256928 kb
Host smart-4955e289-b32d-445c-b2f1-486516aa1666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89408
6869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.894086869
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2645089031
Short name T618
Test name
Test status
Simulation time 295348770 ps
CPU time 22.98 seconds
Started Jun 07 07:46:20 PM PDT 24
Finished Jun 07 07:46:44 PM PDT 24
Peak memory 255568 kb
Host smart-6ab31dcd-b1f5-461e-befb-ece855f8df34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26450
89031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2645089031
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.2060334868
Short name T686
Test name
Test status
Simulation time 13507853936 ps
CPU time 1454.97 seconds
Started Jun 07 07:46:20 PM PDT 24
Finished Jun 07 08:10:37 PM PDT 24
Peak memory 286084 kb
Host smart-7d0d49da-928f-43f8-98be-924d1753225e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060334868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2060334868
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3280345611
Short name T514
Test name
Test status
Simulation time 2257453905 ps
CPU time 94.33 seconds
Started Jun 07 07:46:22 PM PDT 24
Finished Jun 07 07:47:58 PM PDT 24
Peak memory 248444 kb
Host smart-5c184aae-a465-48a2-9fe8-ade000b1e325
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280345611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3280345611
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3763439936
Short name T49
Test name
Test status
Simulation time 461472889 ps
CPU time 30.32 seconds
Started Jun 07 07:46:19 PM PDT 24
Finished Jun 07 07:46:51 PM PDT 24
Peak memory 256352 kb
Host smart-bef68f4e-744f-4860-8782-958200a10306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37634
39936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3763439936
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.4032575136
Short name T264
Test name
Test status
Simulation time 530592909 ps
CPU time 12.82 seconds
Started Jun 07 07:46:20 PM PDT 24
Finished Jun 07 07:46:34 PM PDT 24
Peak memory 255272 kb
Host smart-60c4907b-b778-41dd-b502-baa032fe5b06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40325
75136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.4032575136
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1178980957
Short name T641
Test name
Test status
Simulation time 309418549 ps
CPU time 42.86 seconds
Started Jun 07 07:46:21 PM PDT 24
Finished Jun 07 07:47:06 PM PDT 24
Peak memory 248552 kb
Host smart-74f76287-2d14-42da-a2d3-b0db63317674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11789
80957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1178980957
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3370353083
Short name T581
Test name
Test status
Simulation time 278853097 ps
CPU time 27.94 seconds
Started Jun 07 07:46:21 PM PDT 24
Finished Jun 07 07:46:50 PM PDT 24
Peak memory 248716 kb
Host smart-d555127e-0e0b-49fe-97a3-b7e9cd8f2cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33703
53083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3370353083
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.3852705060
Short name T55
Test name
Test status
Simulation time 193681965107 ps
CPU time 9775.26 seconds
Started Jun 07 07:46:23 PM PDT 24
Finished Jun 07 10:29:21 PM PDT 24
Peak memory 404576 kb
Host smart-4574180a-67d3-4fe4-964a-1af799b8b125
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852705060 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.3852705060
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.3231792219
Short name T386
Test name
Test status
Simulation time 138421557103 ps
CPU time 2119.67 seconds
Started Jun 07 07:46:29 PM PDT 24
Finished Jun 07 08:21:51 PM PDT 24
Peak memory 268612 kb
Host smart-06064861-6491-43d7-9fad-7fb1b1c5305b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231792219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.3231792219
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2138098328
Short name T43
Test name
Test status
Simulation time 2014086348 ps
CPU time 113.45 seconds
Started Jun 07 07:46:29 PM PDT 24
Finished Jun 07 07:48:25 PM PDT 24
Peak memory 256852 kb
Host smart-f89bd51e-ab37-47e2-9a07-a392274dee56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21380
98328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2138098328
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.2041172804
Short name T527
Test name
Test status
Simulation time 1878755201 ps
CPU time 62.86 seconds
Started Jun 07 07:46:33 PM PDT 24
Finished Jun 07 07:47:39 PM PDT 24
Peak memory 248860 kb
Host smart-b3d9bb49-7b28-40a0-834a-764e4b32c52b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20411
72804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.2041172804
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1500223821
Short name T340
Test name
Test status
Simulation time 223900667000 ps
CPU time 3331.75 seconds
Started Jun 07 07:46:33 PM PDT 24
Finished Jun 07 08:42:08 PM PDT 24
Peak memory 281632 kb
Host smart-dd4ef553-07de-441a-a97b-35b321202e30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500223821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1500223821
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.3949729144
Short name T569
Test name
Test status
Simulation time 12881753260 ps
CPU time 1162 seconds
Started Jun 07 07:46:31 PM PDT 24
Finished Jun 07 08:05:55 PM PDT 24
Peak memory 273312 kb
Host smart-8f3981c5-46da-4dc6-b1a6-807d4cca3530
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949729144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3949729144
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.3879660007
Short name T190
Test name
Test status
Simulation time 10396135820 ps
CPU time 105.9 seconds
Started Jun 07 07:46:32 PM PDT 24
Finished Jun 07 07:48:20 PM PDT 24
Peak memory 248368 kb
Host smart-dc3710bd-ff6a-4c87-ada4-d30f588b41ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879660007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3879660007
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.493422564
Short name T612
Test name
Test status
Simulation time 381763271 ps
CPU time 13 seconds
Started Jun 07 07:46:21 PM PDT 24
Finished Jun 07 07:46:35 PM PDT 24
Peak memory 253880 kb
Host smart-d33f2713-4706-4036-9d7d-d979331cd64c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49342
2564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.493422564
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2630727280
Short name T86
Test name
Test status
Simulation time 1336383300 ps
CPU time 37.92 seconds
Started Jun 07 07:46:32 PM PDT 24
Finished Jun 07 07:47:12 PM PDT 24
Peak memory 248660 kb
Host smart-89ecee35-c2fb-4934-b719-bc8fae9f2516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26307
27280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2630727280
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.2703200701
Short name T254
Test name
Test status
Simulation time 387576779 ps
CPU time 33.16 seconds
Started Jun 07 07:46:28 PM PDT 24
Finished Jun 07 07:47:03 PM PDT 24
Peak memory 247576 kb
Host smart-41eeca1e-ed99-4a7a-a681-029984d7b0d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27032
00701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2703200701
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1994127592
Short name T379
Test name
Test status
Simulation time 1846244414 ps
CPU time 30.62 seconds
Started Jun 07 07:46:22 PM PDT 24
Finished Jun 07 07:46:55 PM PDT 24
Peak memory 256884 kb
Host smart-4cfc2674-fc87-4c62-99e0-aebea8176e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19941
27592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1994127592
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2252386453
Short name T455
Test name
Test status
Simulation time 9099080761 ps
CPU time 924.33 seconds
Started Jun 07 07:46:30 PM PDT 24
Finished Jun 07 08:01:57 PM PDT 24
Peak memory 281600 kb
Host smart-9e81b0f8-7440-4c7b-848b-c60b27df8909
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252386453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2252386453
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3992410912
Short name T547
Test name
Test status
Simulation time 9083060336 ps
CPU time 1051.89 seconds
Started Jun 07 07:46:30 PM PDT 24
Finished Jun 07 08:04:05 PM PDT 24
Peak memory 284672 kb
Host smart-397247d7-14c4-44d4-92e7-9c5cabf4e3ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992410912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3992410912
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3204020269
Short name T625
Test name
Test status
Simulation time 32189469281 ps
CPU time 316.77 seconds
Started Jun 07 07:46:29 PM PDT 24
Finished Jun 07 07:51:48 PM PDT 24
Peak memory 256832 kb
Host smart-15b111c2-c2cf-4da9-83d6-b2873183e86d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32040
20269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3204020269
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1988071920
Short name T448
Test name
Test status
Simulation time 10340547692 ps
CPU time 53.44 seconds
Started Jun 07 07:46:33 PM PDT 24
Finished Jun 07 07:47:29 PM PDT 24
Peak memory 255384 kb
Host smart-8e158c5d-5b77-46fd-afc8-743b93c97eb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19880
71920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1988071920
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3039730789
Short name T494
Test name
Test status
Simulation time 19505006230 ps
CPU time 1471.05 seconds
Started Jun 07 07:46:30 PM PDT 24
Finished Jun 07 08:11:04 PM PDT 24
Peak memory 281572 kb
Host smart-46d1b394-937b-4371-a0a1-76e8e69a0793
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039730789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3039730789
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3526432500
Short name T573
Test name
Test status
Simulation time 102941844121 ps
CPU time 3125.53 seconds
Started Jun 07 07:46:32 PM PDT 24
Finished Jun 07 08:38:40 PM PDT 24
Peak memory 289224 kb
Host smart-b7d42ddb-062f-4153-ae1f-f0b5d674f26c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526432500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3526432500
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.4224987792
Short name T10
Test name
Test status
Simulation time 144446102220 ps
CPU time 293.25 seconds
Started Jun 07 07:46:33 PM PDT 24
Finished Jun 07 07:51:29 PM PDT 24
Peak memory 253884 kb
Host smart-1c82bba4-304f-439f-a285-8485bcdd8f0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224987792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.4224987792
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.2209737475
Short name T71
Test name
Test status
Simulation time 229726752 ps
CPU time 20.11 seconds
Started Jun 07 07:46:27 PM PDT 24
Finished Jun 07 07:46:48 PM PDT 24
Peak memory 248708 kb
Host smart-59b6a1ef-4b78-4644-ba01-580c6c663945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22097
37475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2209737475
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.713733046
Short name T408
Test name
Test status
Simulation time 3744070301 ps
CPU time 32.74 seconds
Started Jun 07 07:46:30 PM PDT 24
Finished Jun 07 07:47:06 PM PDT 24
Peak memory 255288 kb
Host smart-17347d5b-9716-4d19-bc9e-c17ada31c49b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71373
3046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.713733046
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1395083693
Short name T630
Test name
Test status
Simulation time 264691212 ps
CPU time 17.75 seconds
Started Jun 07 07:46:33 PM PDT 24
Finished Jun 07 07:46:54 PM PDT 24
Peak memory 247324 kb
Host smart-fc613a49-155e-446b-a4d3-72394e624055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13950
83693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1395083693
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3732580586
Short name T703
Test name
Test status
Simulation time 654003057 ps
CPU time 40.93 seconds
Started Jun 07 07:46:29 PM PDT 24
Finished Jun 07 07:47:12 PM PDT 24
Peak memory 248728 kb
Host smart-53113479-e479-4c61-aab1-57cb52d218a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37325
80586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3732580586
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.2072130904
Short name T79
Test name
Test status
Simulation time 3180546574 ps
CPU time 85.58 seconds
Started Jun 07 07:46:36 PM PDT 24
Finished Jun 07 07:48:05 PM PDT 24
Peak memory 256980 kb
Host smart-f6404c41-ddbe-4441-bf32-9ef1af292895
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072130904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.2072130904
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.2551514466
Short name T260
Test name
Test status
Simulation time 114584023321 ps
CPU time 2943.95 seconds
Started Jun 07 07:46:39 PM PDT 24
Finished Jun 07 08:35:46 PM PDT 24
Peak memory 322544 kb
Host smart-ee40cbdf-0765-49fd-8acf-32b9ef0a4a05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551514466 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.2551514466
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.4001639495
Short name T262
Test name
Test status
Simulation time 48389533830 ps
CPU time 2928.5 seconds
Started Jun 07 07:46:36 PM PDT 24
Finished Jun 07 08:35:28 PM PDT 24
Peak memory 288020 kb
Host smart-22c636ee-ef8a-4db1-9a7c-f0ed72e7387a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001639495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.4001639495
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1233391988
Short name T523
Test name
Test status
Simulation time 1493430314 ps
CPU time 146.54 seconds
Started Jun 07 07:46:38 PM PDT 24
Finished Jun 07 07:49:08 PM PDT 24
Peak memory 256892 kb
Host smart-e6bc3237-968c-49ea-932e-a80d73581519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12333
91988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1233391988
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.711775811
Short name T282
Test name
Test status
Simulation time 173689766 ps
CPU time 14.32 seconds
Started Jun 07 07:46:39 PM PDT 24
Finished Jun 07 07:46:56 PM PDT 24
Peak memory 248916 kb
Host smart-bf409de5-9357-4a37-a93c-cb160a1360db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71177
5811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.711775811
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2376938540
Short name T708
Test name
Test status
Simulation time 101557900130 ps
CPU time 1549.32 seconds
Started Jun 07 07:46:37 PM PDT 24
Finished Jun 07 08:12:30 PM PDT 24
Peak memory 265220 kb
Host smart-58040208-85ef-4b27-b6e0-5b8f1394e851
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376938540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2376938540
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.3176687934
Short name T564
Test name
Test status
Simulation time 136895002965 ps
CPU time 2298.02 seconds
Started Jun 07 07:46:37 PM PDT 24
Finished Jun 07 08:24:59 PM PDT 24
Peak memory 287556 kb
Host smart-d3cd075b-5f18-4f8c-aa29-945be524d03d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176687934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3176687934
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1134439710
Short name T329
Test name
Test status
Simulation time 1962648453 ps
CPU time 82.02 seconds
Started Jun 07 07:46:37 PM PDT 24
Finished Jun 07 07:48:03 PM PDT 24
Peak memory 248388 kb
Host smart-b528b994-5d45-4219-b16a-005db2e8d3de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134439710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1134439710
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2809720563
Short name T413
Test name
Test status
Simulation time 5859693386 ps
CPU time 40.29 seconds
Started Jun 07 07:46:39 PM PDT 24
Finished Jun 07 07:47:22 PM PDT 24
Peak memory 256516 kb
Host smart-beb3c59f-1498-47db-b86a-68357af86251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28097
20563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2809720563
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.1585277118
Short name T656
Test name
Test status
Simulation time 1705120682 ps
CPU time 67.24 seconds
Started Jun 07 07:46:38 PM PDT 24
Finished Jun 07 07:47:48 PM PDT 24
Peak memory 256860 kb
Host smart-c122a313-0968-4644-aefb-57a321b6adf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15852
77118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1585277118
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.2476299212
Short name T392
Test name
Test status
Simulation time 4190384691 ps
CPU time 39.75 seconds
Started Jun 07 07:46:36 PM PDT 24
Finished Jun 07 07:47:19 PM PDT 24
Peak memory 256032 kb
Host smart-9e633d6a-a914-41c6-9edf-385d07e3308a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24762
99212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2476299212
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2305242900
Short name T484
Test name
Test status
Simulation time 4327599025 ps
CPU time 62.54 seconds
Started Jun 07 07:46:37 PM PDT 24
Finished Jun 07 07:47:43 PM PDT 24
Peak memory 256912 kb
Host smart-b9392cdf-07df-44e7-b11f-4e1e27220638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23052
42900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2305242900
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2386120067
Short name T296
Test name
Test status
Simulation time 153629588787 ps
CPU time 2385.71 seconds
Started Jun 07 07:46:38 PM PDT 24
Finished Jun 07 08:26:27 PM PDT 24
Peak memory 289512 kb
Host smart-b1b7021c-e9ef-4d4b-bf78-d213e22494da
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386120067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2386120067
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.3739712910
Short name T393
Test name
Test status
Simulation time 16166122704 ps
CPU time 268.45 seconds
Started Jun 07 07:46:46 PM PDT 24
Finished Jun 07 07:51:16 PM PDT 24
Peak memory 256916 kb
Host smart-a3284d6b-f399-40af-bd7f-f50d7faa8593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37397
12910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3739712910
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2059488101
Short name T186
Test name
Test status
Simulation time 98459401 ps
CPU time 4.43 seconds
Started Jun 07 07:46:37 PM PDT 24
Finished Jun 07 07:46:45 PM PDT 24
Peak memory 239304 kb
Host smart-10157cef-239c-41e1-bfd0-22193eb21cc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20594
88101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2059488101
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.3449185506
Short name T327
Test name
Test status
Simulation time 94479078279 ps
CPU time 2752.01 seconds
Started Jun 07 07:46:42 PM PDT 24
Finished Jun 07 08:32:37 PM PDT 24
Peak memory 289648 kb
Host smart-6d949c2c-b066-42fd-913b-d272fa0bc5d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449185506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3449185506
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.109770774
Short name T622
Test name
Test status
Simulation time 83674295702 ps
CPU time 1107.78 seconds
Started Jun 07 07:46:44 PM PDT 24
Finished Jun 07 08:05:14 PM PDT 24
Peak memory 272492 kb
Host smart-5b3c2d54-059a-41a4-abb4-157fce886c9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109770774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.109770774
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.1633977043
Short name T34
Test name
Test status
Simulation time 5863628985 ps
CPU time 245.22 seconds
Started Jun 07 07:46:45 PM PDT 24
Finished Jun 07 07:50:53 PM PDT 24
Peak memory 254580 kb
Host smart-34fc9315-3d9f-4c4c-9f5c-ac26600c5088
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633977043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1633977043
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1773189261
Short name T697
Test name
Test status
Simulation time 930578252 ps
CPU time 25.63 seconds
Started Jun 07 07:46:39 PM PDT 24
Finished Jun 07 07:47:07 PM PDT 24
Peak memory 256168 kb
Host smart-cfd21dcd-de59-421f-8c45-1c61ac3e3230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17731
89261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1773189261
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2249396403
Short name T463
Test name
Test status
Simulation time 8011373079 ps
CPU time 90.41 seconds
Started Jun 07 07:46:37 PM PDT 24
Finished Jun 07 07:48:11 PM PDT 24
Peak memory 256912 kb
Host smart-62e8cbba-ff7a-441f-8971-06a63744f022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22493
96403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2249396403
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.951854622
Short name T70
Test name
Test status
Simulation time 1749982544 ps
CPU time 34.2 seconds
Started Jun 07 07:46:45 PM PDT 24
Finished Jun 07 07:47:21 PM PDT 24
Peak memory 256176 kb
Host smart-d66cc134-a48d-4bf1-851f-fca47fc79d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95185
4622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.951854622
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1593648811
Short name T644
Test name
Test status
Simulation time 327596250 ps
CPU time 18.95 seconds
Started Jun 07 07:46:36 PM PDT 24
Finished Jun 07 07:46:58 PM PDT 24
Peak memory 248720 kb
Host smart-75e26766-e513-4257-8058-79f4c69387f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15936
48811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1593648811
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.3226497284
Short name T46
Test name
Test status
Simulation time 38971851868 ps
CPU time 1021.87 seconds
Started Jun 07 07:46:46 PM PDT 24
Finished Jun 07 08:03:50 PM PDT 24
Peak memory 288564 kb
Host smart-2a579969-d20b-4194-b97c-9937fb11d501
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226497284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3226497284
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.3929910349
Short name T201
Test name
Test status
Simulation time 73697238 ps
CPU time 3.37 seconds
Started Jun 07 07:44:53 PM PDT 24
Finished Jun 07 07:44:58 PM PDT 24
Peak memory 248920 kb
Host smart-8582d1cf-03dd-4123-8d60-4f3f19ae4f6c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3929910349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.3929910349
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1922757248
Short name T536
Test name
Test status
Simulation time 138594303986 ps
CPU time 2024.57 seconds
Started Jun 07 07:44:50 PM PDT 24
Finished Jun 07 08:18:37 PM PDT 24
Peak memory 282648 kb
Host smart-655947f0-ec5c-4719-a620-1a4752eaa1c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922757248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1922757248
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.3642905624
Short name T217
Test name
Test status
Simulation time 286788538 ps
CPU time 14.5 seconds
Started Jun 07 07:44:47 PM PDT 24
Finished Jun 07 07:45:04 PM PDT 24
Peak memory 240488 kb
Host smart-d5261cff-22b1-42f8-b0e5-9cddbe87452d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3642905624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3642905624
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.2159165942
Short name T567
Test name
Test status
Simulation time 4376364654 ps
CPU time 236.1 seconds
Started Jun 07 07:44:48 PM PDT 24
Finished Jun 07 07:48:46 PM PDT 24
Peak memory 256996 kb
Host smart-8f1c80c9-d11b-4e84-8f10-b2ac0baa7828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21591
65942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2159165942
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.1318528567
Short name T698
Test name
Test status
Simulation time 224561877 ps
CPU time 7.9 seconds
Started Jun 07 07:44:46 PM PDT 24
Finished Jun 07 07:44:56 PM PDT 24
Peak memory 248680 kb
Host smart-e08e9df0-4d5e-43db-aa85-e9999c07c417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13185
28567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1318528567
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3235456794
Short name T228
Test name
Test status
Simulation time 9870352245 ps
CPU time 993.06 seconds
Started Jun 07 07:44:51 PM PDT 24
Finished Jun 07 08:01:27 PM PDT 24
Peak memory 281592 kb
Host smart-8687933f-05ee-4acd-bc23-ef7af5e5725c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235456794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3235456794
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.527251001
Short name T469
Test name
Test status
Simulation time 18089803594 ps
CPU time 1418.04 seconds
Started Jun 07 07:44:46 PM PDT 24
Finished Jun 07 08:08:27 PM PDT 24
Peak memory 288768 kb
Host smart-4229d2e4-7c3e-4ad4-8422-318be377b68a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527251001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.527251001
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3688486265
Short name T322
Test name
Test status
Simulation time 24962911952 ps
CPU time 225.24 seconds
Started Jun 07 07:44:50 PM PDT 24
Finished Jun 07 07:48:38 PM PDT 24
Peak memory 248372 kb
Host smart-99ba6c19-27d7-4d03-a096-9564a26abf40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688486265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3688486265
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2285791043
Short name T380
Test name
Test status
Simulation time 126910000 ps
CPU time 13.64 seconds
Started Jun 07 07:44:48 PM PDT 24
Finished Jun 07 07:45:04 PM PDT 24
Peak memory 248748 kb
Host smart-ae04458f-4554-43c4-8601-3f0c3e7a5039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22857
91043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2285791043
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2873123801
Short name T621
Test name
Test status
Simulation time 2200679622 ps
CPU time 40.53 seconds
Started Jun 07 07:44:47 PM PDT 24
Finished Jun 07 07:45:30 PM PDT 24
Peak memory 256888 kb
Host smart-9cdff303-8db4-413b-915a-1969df4e7107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28731
23801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2873123801
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1825013758
Short name T14
Test name
Test status
Simulation time 1706330143 ps
CPU time 70.31 seconds
Started Jun 07 07:44:52 PM PDT 24
Finished Jun 07 07:46:04 PM PDT 24
Peak memory 270080 kb
Host smart-ffc80809-3f58-4494-8151-78d1f739a932
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1825013758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1825013758
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2703786883
Short name T543
Test name
Test status
Simulation time 451429786 ps
CPU time 17 seconds
Started Jun 07 07:44:47 PM PDT 24
Finished Jun 07 07:45:06 PM PDT 24
Peak memory 253092 kb
Host smart-f59201d9-c416-4ac8-a0be-76d60ddc9ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27037
86883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2703786883
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2990797204
Short name T404
Test name
Test status
Simulation time 717913745 ps
CPU time 44.8 seconds
Started Jun 07 07:44:49 PM PDT 24
Finished Jun 07 07:45:36 PM PDT 24
Peak memory 248696 kb
Host smart-6f67ee21-cac7-4007-a993-56ff9a973ccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29907
97204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2990797204
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.3209811758
Short name T680
Test name
Test status
Simulation time 34899642481 ps
CPU time 3539.48 seconds
Started Jun 07 07:44:46 PM PDT 24
Finished Jun 07 08:43:49 PM PDT 24
Peak memory 322156 kb
Host smart-046e3c98-9c59-400a-9196-fada860867f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209811758 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.3209811758
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.2123245918
Short name T67
Test name
Test status
Simulation time 9137280868 ps
CPU time 689.95 seconds
Started Jun 07 07:46:43 PM PDT 24
Finished Jun 07 07:58:15 PM PDT 24
Peak memory 272992 kb
Host smart-c2c5adb1-fb4d-403e-8f23-8768e1554800
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123245918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2123245918
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.2057387602
Short name T566
Test name
Test status
Simulation time 1861487180 ps
CPU time 175.65 seconds
Started Jun 07 07:46:43 PM PDT 24
Finished Jun 07 07:49:42 PM PDT 24
Peak memory 256844 kb
Host smart-cbec806c-2d4e-4dbc-bd84-d25efeab1ac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20573
87602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.2057387602
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.2500392268
Short name T533
Test name
Test status
Simulation time 142536400 ps
CPU time 5.51 seconds
Started Jun 07 07:46:47 PM PDT 24
Finished Jun 07 07:46:54 PM PDT 24
Peak memory 240480 kb
Host smart-ebd495dc-af2d-4a69-a712-ce38d537244c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25003
92268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2500392268
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1403290273
Short name T328
Test name
Test status
Simulation time 122490378104 ps
CPU time 2699.17 seconds
Started Jun 07 07:46:45 PM PDT 24
Finished Jun 07 08:31:47 PM PDT 24
Peak memory 285604 kb
Host smart-7edefc2f-9b5c-484f-bd8d-8779932c5fd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403290273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1403290273
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.2017826726
Short name T522
Test name
Test status
Simulation time 37911077218 ps
CPU time 867.39 seconds
Started Jun 07 07:46:51 PM PDT 24
Finished Jun 07 08:01:20 PM PDT 24
Peak memory 271924 kb
Host smart-8aace0c5-65c0-4982-b915-ac0de5f19481
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017826726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2017826726
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.3813273718
Short name T314
Test name
Test status
Simulation time 6004158815 ps
CPU time 245.44 seconds
Started Jun 07 07:46:44 PM PDT 24
Finished Jun 07 07:50:52 PM PDT 24
Peak memory 248364 kb
Host smart-2b510221-5734-4be9-b028-750e9f0644a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813273718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3813273718
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.4282918148
Short name T107
Test name
Test status
Simulation time 129741634 ps
CPU time 4.63 seconds
Started Jun 07 07:46:45 PM PDT 24
Finished Jun 07 07:46:52 PM PDT 24
Peak memory 240716 kb
Host smart-a28eda74-dbc4-40a3-804c-7391fc26fa1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42829
18148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.4282918148
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.1842682891
Short name T591
Test name
Test status
Simulation time 855993481 ps
CPU time 56.02 seconds
Started Jun 07 07:46:44 PM PDT 24
Finished Jun 07 07:47:43 PM PDT 24
Peak memory 255616 kb
Host smart-57057bbe-47c4-427b-8614-52cb2da39f62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18426
82891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.1842682891
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.682287477
Short name T290
Test name
Test status
Simulation time 209719753 ps
CPU time 30.2 seconds
Started Jun 07 07:46:42 PM PDT 24
Finished Jun 07 07:47:15 PM PDT 24
Peak memory 247708 kb
Host smart-b93a3c62-f2c7-448f-b871-b1ae643d8168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68228
7477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.682287477
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2442637561
Short name T707
Test name
Test status
Simulation time 2567800395 ps
CPU time 46.04 seconds
Started Jun 07 07:46:43 PM PDT 24
Finished Jun 07 07:47:32 PM PDT 24
Peak memory 248764 kb
Host smart-77acf8d3-ce62-4e61-95ba-7e4386acf0e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24426
37561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2442637561
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2578885526
Short name T417
Test name
Test status
Simulation time 70565084075 ps
CPU time 1780.77 seconds
Started Jun 07 07:46:52 PM PDT 24
Finished Jun 07 08:16:34 PM PDT 24
Peak memory 299988 kb
Host smart-1836e72f-5149-4f32-a458-728cfb2e2216
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578885526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2578885526
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.1381322524
Short name T502
Test name
Test status
Simulation time 320785234067 ps
CPU time 5605.4 seconds
Started Jun 07 07:46:54 PM PDT 24
Finished Jun 07 09:20:21 PM PDT 24
Peak memory 321916 kb
Host smart-6e811950-d4cb-4fac-8478-db2c697cd1bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381322524 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.1381322524
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.1356040196
Short name T541
Test name
Test status
Simulation time 5273557791 ps
CPU time 273.12 seconds
Started Jun 07 07:46:51 PM PDT 24
Finished Jun 07 07:51:25 PM PDT 24
Peak memory 256932 kb
Host smart-b390e819-163b-4c06-9233-6985feaca0fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13560
40196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.1356040196
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1741755339
Short name T436
Test name
Test status
Simulation time 56787808 ps
CPU time 8.92 seconds
Started Jun 07 07:46:53 PM PDT 24
Finished Jun 07 07:47:04 PM PDT 24
Peak memory 254952 kb
Host smart-f916c59a-0a67-4f03-b280-bf68494c5554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17417
55339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1741755339
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1075796835
Short name T338
Test name
Test status
Simulation time 139630184732 ps
CPU time 1169.37 seconds
Started Jun 07 07:47:00 PM PDT 24
Finished Jun 07 08:06:30 PM PDT 24
Peak memory 270880 kb
Host smart-db69b2ef-d76f-42a8-a429-23268638002b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075796835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1075796835
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.3923109066
Short name T366
Test name
Test status
Simulation time 36759355342 ps
CPU time 2068.49 seconds
Started Jun 07 07:46:59 PM PDT 24
Finished Jun 07 08:21:29 PM PDT 24
Peak memory 272696 kb
Host smart-09cce35f-ba81-43ab-81b5-0ef867b37828
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923109066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.3923109066
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.696028485
Short name T608
Test name
Test status
Simulation time 7827524196 ps
CPU time 83.45 seconds
Started Jun 07 07:46:52 PM PDT 24
Finished Jun 07 07:48:17 PM PDT 24
Peak memory 248384 kb
Host smart-81c21f37-61e0-4fce-b4b2-fd047c5dce3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696028485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.696028485
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3262472080
Short name T517
Test name
Test status
Simulation time 6061392335 ps
CPU time 71.75 seconds
Started Jun 07 07:46:52 PM PDT 24
Finished Jun 07 07:48:05 PM PDT 24
Peak memory 256964 kb
Host smart-06001443-61c6-4a5b-bd01-741845cf9aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32624
72080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3262472080
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2427952557
Short name T286
Test name
Test status
Simulation time 682034581 ps
CPU time 19.22 seconds
Started Jun 07 07:46:53 PM PDT 24
Finished Jun 07 07:47:13 PM PDT 24
Peak memory 247772 kb
Host smart-a25729be-12ea-41a8-924b-3e6af104c728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24279
52557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2427952557
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.696950053
Short name T396
Test name
Test status
Simulation time 261611936 ps
CPU time 10.69 seconds
Started Jun 07 07:46:52 PM PDT 24
Finished Jun 07 07:47:03 PM PDT 24
Peak memory 256892 kb
Host smart-cb5ada0a-a59d-4113-b425-4d909d7f075a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69695
0053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.696950053
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2063779186
Short name T512
Test name
Test status
Simulation time 178208958843 ps
CPU time 1397.24 seconds
Started Jun 07 07:46:59 PM PDT 24
Finished Jun 07 08:10:18 PM PDT 24
Peak memory 289532 kb
Host smart-b2488c85-3182-4c39-8d2a-7bde4d67bf95
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063779186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2063779186
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.662188357
Short name T559
Test name
Test status
Simulation time 18743102746 ps
CPU time 942.41 seconds
Started Jun 07 07:46:58 PM PDT 24
Finished Jun 07 08:02:42 PM PDT 24
Peak memory 268240 kb
Host smart-c2274511-cf55-452a-ae7a-32ee955f77d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662188357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.662188357
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1206614726
Short name T94
Test name
Test status
Simulation time 21977831556 ps
CPU time 334.75 seconds
Started Jun 07 07:46:59 PM PDT 24
Finished Jun 07 07:52:35 PM PDT 24
Peak memory 256808 kb
Host smart-d99d0d43-662f-4a7f-81a5-147fefe2f423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12066
14726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1206614726
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.3088386283
Short name T387
Test name
Test status
Simulation time 140918630 ps
CPU time 15.54 seconds
Started Jun 07 07:46:58 PM PDT 24
Finished Jun 07 07:47:14 PM PDT 24
Peak memory 249048 kb
Host smart-0de4de1f-9da6-403e-826d-570186ab5c57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30883
86283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.3088386283
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.259998315
Short name T468
Test name
Test status
Simulation time 46394277138 ps
CPU time 872.51 seconds
Started Jun 07 07:47:09 PM PDT 24
Finished Jun 07 08:01:42 PM PDT 24
Peak memory 267720 kb
Host smart-a7e5e1d5-f563-42af-ad66-99879a157b4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259998315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.259998315
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.3189642719
Short name T551
Test name
Test status
Simulation time 49108479691 ps
CPU time 1303.1 seconds
Started Jun 07 07:47:07 PM PDT 24
Finished Jun 07 08:08:52 PM PDT 24
Peak memory 286356 kb
Host smart-99597896-d955-454f-b603-5120420c42e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189642719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3189642719
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.3184887011
Short name T364
Test name
Test status
Simulation time 454531220 ps
CPU time 25.26 seconds
Started Jun 07 07:47:00 PM PDT 24
Finished Jun 07 07:47:26 PM PDT 24
Peak memory 248768 kb
Host smart-3a2f2fc3-86ea-4dfd-9f8a-6a37213523b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31848
87011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3184887011
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2262581234
Short name T583
Test name
Test status
Simulation time 763658761 ps
CPU time 18.35 seconds
Started Jun 07 07:46:59 PM PDT 24
Finished Jun 07 07:47:19 PM PDT 24
Peak memory 248864 kb
Host smart-58a38a76-32ad-4087-b4d7-c747d1126a55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22625
81234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2262581234
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.2930623192
Short name T390
Test name
Test status
Simulation time 123379648 ps
CPU time 13.73 seconds
Started Jun 07 07:47:00 PM PDT 24
Finished Jun 07 07:47:15 PM PDT 24
Peak memory 256816 kb
Host smart-0eea9e6c-3c04-46ce-871b-a1e6cd09e161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29306
23192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.2930623192
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1934952700
Short name T695
Test name
Test status
Simulation time 346794026 ps
CPU time 21.02 seconds
Started Jun 07 07:47:00 PM PDT 24
Finished Jun 07 07:47:22 PM PDT 24
Peak memory 248728 kb
Host smart-eaa807b5-4ccc-40bd-a097-0c51501fb79b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19349
52700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1934952700
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3102888825
Short name T577
Test name
Test status
Simulation time 28935487469 ps
CPU time 1758.13 seconds
Started Jun 07 07:47:08 PM PDT 24
Finished Jun 07 08:16:27 PM PDT 24
Peak memory 272152 kb
Host smart-7fb553c9-0b1c-45bf-919b-ebd1076d8c6e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102888825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3102888825
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.499023540
Short name T84
Test name
Test status
Simulation time 35371433461 ps
CPU time 3691.26 seconds
Started Jun 07 07:47:07 PM PDT 24
Finished Jun 07 08:48:40 PM PDT 24
Peak memory 322068 kb
Host smart-684c671f-f563-48a5-be8c-0f2ea8a4805e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499023540 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.499023540
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2076657385
Short name T440
Test name
Test status
Simulation time 44506020727 ps
CPU time 1100.08 seconds
Started Jun 07 07:47:07 PM PDT 24
Finished Jun 07 08:05:28 PM PDT 24
Peak memory 265332 kb
Host smart-f99379b4-46be-4733-aede-1e577ebad967
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076657385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2076657385
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.3766956742
Short name T384
Test name
Test status
Simulation time 8892595514 ps
CPU time 144.74 seconds
Started Jun 07 07:47:07 PM PDT 24
Finished Jun 07 07:49:33 PM PDT 24
Peak memory 256924 kb
Host smart-afa8db40-daec-485e-af0f-e67cd9f26d62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37669
56742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3766956742
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.1081643155
Short name T427
Test name
Test status
Simulation time 2479628619 ps
CPU time 45.02 seconds
Started Jun 07 07:47:08 PM PDT 24
Finished Jun 07 07:47:54 PM PDT 24
Peak memory 249032 kb
Host smart-2dbe057c-215d-4b2d-b6d6-542d877718b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10816
43155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1081643155
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.1762209313
Short name T549
Test name
Test status
Simulation time 116637134185 ps
CPU time 1685.67 seconds
Started Jun 07 07:47:16 PM PDT 24
Finished Jun 07 08:15:23 PM PDT 24
Peak memory 272580 kb
Host smart-c1254da3-f1c1-458e-be69-2926aa129cb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762209313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.1762209313
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.4276737480
Short name T594
Test name
Test status
Simulation time 128487205372 ps
CPU time 2259.63 seconds
Started Jun 07 07:47:17 PM PDT 24
Finished Jun 07 08:24:58 PM PDT 24
Peak memory 286808 kb
Host smart-6bdbec72-8755-41e8-aec3-926b3c06a29e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276737480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.4276737480
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3298254230
Short name T642
Test name
Test status
Simulation time 13868994447 ps
CPU time 161.16 seconds
Started Jun 07 07:47:18 PM PDT 24
Finished Jun 07 07:50:00 PM PDT 24
Peak memory 248308 kb
Host smart-630efc17-c692-443d-b9f9-68fe17e3aad4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298254230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3298254230
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1749572877
Short name T56
Test name
Test status
Simulation time 3718487501 ps
CPU time 62.62 seconds
Started Jun 07 07:47:08 PM PDT 24
Finished Jun 07 07:48:12 PM PDT 24
Peak memory 256960 kb
Host smart-4394ca49-d621-48e1-b42d-529952eb61ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17495
72877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1749572877
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.117550537
Short name T670
Test name
Test status
Simulation time 1929457667 ps
CPU time 54.89 seconds
Started Jun 07 07:47:10 PM PDT 24
Finished Jun 07 07:48:05 PM PDT 24
Peak memory 248004 kb
Host smart-49b672b6-3b44-4597-9e9d-cb5895b46423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11755
0537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.117550537
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.313939175
Short name T243
Test name
Test status
Simulation time 850385203 ps
CPU time 29.33 seconds
Started Jun 07 07:47:06 PM PDT 24
Finished Jun 07 07:47:36 PM PDT 24
Peak memory 248824 kb
Host smart-1408cede-a272-44aa-be34-510e68da02c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31393
9175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.313939175
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.4289121102
Short name T464
Test name
Test status
Simulation time 491740871 ps
CPU time 38.26 seconds
Started Jun 07 07:47:06 PM PDT 24
Finished Jun 07 07:47:45 PM PDT 24
Peak memory 248660 kb
Host smart-df34f672-167a-48f6-a963-c0c2dc5dbe74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42891
21102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.4289121102
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3739723448
Short name T598
Test name
Test status
Simulation time 13030135490 ps
CPU time 1439.51 seconds
Started Jun 07 07:47:16 PM PDT 24
Finished Jun 07 08:11:16 PM PDT 24
Peak memory 289400 kb
Host smart-03270d17-0efa-41b8-ac9c-6aafef40e83a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739723448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3739723448
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.530442238
Short name T97
Test name
Test status
Simulation time 26981328040 ps
CPU time 1296.9 seconds
Started Jun 07 07:47:15 PM PDT 24
Finished Jun 07 08:08:53 PM PDT 24
Peak memory 289892 kb
Host smart-b386beaa-d376-45a0-8ea7-53ad66eb1b71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530442238 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.530442238
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1244626934
Short name T244
Test name
Test status
Simulation time 38948153274 ps
CPU time 2316.03 seconds
Started Jun 07 07:47:16 PM PDT 24
Finished Jun 07 08:25:53 PM PDT 24
Peak memory 287268 kb
Host smart-efade919-307c-4ef7-8e95-36e3dfb1d312
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244626934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1244626934
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1645846023
Short name T73
Test name
Test status
Simulation time 5769689089 ps
CPU time 149.38 seconds
Started Jun 07 07:47:18 PM PDT 24
Finished Jun 07 07:49:49 PM PDT 24
Peak memory 249904 kb
Host smart-c76d4cbf-c035-4f70-b11f-d3acb9ae00b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16458
46023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1645846023
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3678504558
Short name T400
Test name
Test status
Simulation time 2317644521 ps
CPU time 18.88 seconds
Started Jun 07 07:47:16 PM PDT 24
Finished Jun 07 07:47:36 PM PDT 24
Peak memory 248848 kb
Host smart-a5ec444f-8df5-449b-a16a-20bde6f17e7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36785
04558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3678504558
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.642764013
Short name T120
Test name
Test status
Simulation time 56960254482 ps
CPU time 1505.03 seconds
Started Jun 07 07:47:15 PM PDT 24
Finished Jun 07 08:12:22 PM PDT 24
Peak memory 289272 kb
Host smart-471e0639-e377-492a-868d-aa385448e035
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642764013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.642764013
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.1333026387
Short name T370
Test name
Test status
Simulation time 504983062 ps
CPU time 32.25 seconds
Started Jun 07 07:47:17 PM PDT 24
Finished Jun 07 07:47:50 PM PDT 24
Peak memory 256128 kb
Host smart-b9b399d8-1685-4e86-9515-19c81db6ef38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13330
26387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1333026387
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.2826510363
Short name T362
Test name
Test status
Simulation time 2645024274 ps
CPU time 49.97 seconds
Started Jun 07 07:47:16 PM PDT 24
Finished Jun 07 07:48:07 PM PDT 24
Peak memory 255724 kb
Host smart-2ee056fa-e84b-4c34-95f6-071f51485a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28265
10363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.2826510363
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2613543671
Short name T301
Test name
Test status
Simulation time 350574906 ps
CPU time 19.01 seconds
Started Jun 07 07:47:16 PM PDT 24
Finished Jun 07 07:47:37 PM PDT 24
Peak memory 256104 kb
Host smart-6cf8bb21-2f36-49bf-95b1-f5705556cf79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26135
43671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2613543671
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1079969769
Short name T550
Test name
Test status
Simulation time 175727977 ps
CPU time 11.53 seconds
Started Jun 07 07:47:17 PM PDT 24
Finished Jun 07 07:47:29 PM PDT 24
Peak memory 248716 kb
Host smart-16808f4d-4a80-447c-829c-d8b32aa1e07c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10799
69769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1079969769
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.3375598696
Short name T650
Test name
Test status
Simulation time 45063924083 ps
CPU time 1124.9 seconds
Started Jun 07 07:47:23 PM PDT 24
Finished Jun 07 08:06:09 PM PDT 24
Peak memory 284000 kb
Host smart-65eba226-7667-4577-96c8-f127373ed186
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375598696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.3375598696
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.2880264759
Short name T481
Test name
Test status
Simulation time 4995538541 ps
CPU time 87.91 seconds
Started Jun 07 07:47:24 PM PDT 24
Finished Jun 07 07:48:54 PM PDT 24
Peak memory 256880 kb
Host smart-d3c5f2df-6d96-4886-85fa-6ad7750af10e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28802
64759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2880264759
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.623720428
Short name T675
Test name
Test status
Simulation time 314602610 ps
CPU time 44.77 seconds
Started Jun 07 07:47:23 PM PDT 24
Finished Jun 07 07:48:09 PM PDT 24
Peak memory 254804 kb
Host smart-9197b4ef-129c-435b-9284-7d927291fd95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62372
0428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.623720428
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1428884313
Short name T37
Test name
Test status
Simulation time 30384963646 ps
CPU time 1197.74 seconds
Started Jun 07 07:47:23 PM PDT 24
Finished Jun 07 08:07:22 PM PDT 24
Peak memory 281572 kb
Host smart-3a57bfe8-a6b2-4d5a-b09f-c7af4ad0fc77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428884313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1428884313
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1736045666
Short name T271
Test name
Test status
Simulation time 54562029231 ps
CPU time 1856.64 seconds
Started Jun 07 07:47:22 PM PDT 24
Finished Jun 07 08:18:20 PM PDT 24
Peak memory 281080 kb
Host smart-08fd2a95-6495-47b4-a98c-29de5aae8d33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736045666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1736045666
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.610509701
Short name T462
Test name
Test status
Simulation time 2031220360 ps
CPU time 79.09 seconds
Started Jun 07 07:47:23 PM PDT 24
Finished Jun 07 07:48:43 PM PDT 24
Peak memory 248632 kb
Host smart-39da6a82-5c7c-4d68-8375-170385c31531
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610509701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.610509701
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.257928875
Short name T419
Test name
Test status
Simulation time 61560246 ps
CPU time 5.23 seconds
Started Jun 07 07:47:24 PM PDT 24
Finished Jun 07 07:47:30 PM PDT 24
Peak memory 240564 kb
Host smart-9ab58b07-84a2-4200-b888-2234ea4192a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25792
8875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.257928875
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3631074877
Short name T283
Test name
Test status
Simulation time 2194640334 ps
CPU time 34.23 seconds
Started Jun 07 07:47:23 PM PDT 24
Finished Jun 07 07:47:59 PM PDT 24
Peak memory 254224 kb
Host smart-b49bd395-b62e-4388-99df-d90d5c64da1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36310
74877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3631074877
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.3443181691
Short name T438
Test name
Test status
Simulation time 1188840797 ps
CPU time 28.87 seconds
Started Jun 07 07:47:16 PM PDT 24
Finished Jun 07 07:47:46 PM PDT 24
Peak memory 248708 kb
Host smart-65476603-adea-4d32-858c-76401d61fcd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34431
81691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.3443181691
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.1587614804
Short name T35
Test name
Test status
Simulation time 83751122178 ps
CPU time 2071.65 seconds
Started Jun 07 07:47:24 PM PDT 24
Finished Jun 07 08:21:57 PM PDT 24
Peak memory 297908 kb
Host smart-4a35accb-8054-4dc0-9410-5f240be12488
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587614804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.1587614804
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.4001111090
Short name T42
Test name
Test status
Simulation time 86360906612 ps
CPU time 2545.07 seconds
Started Jun 07 07:47:32 PM PDT 24
Finished Jun 07 08:29:58 PM PDT 24
Peak memory 289328 kb
Host smart-9f5ee5be-eb95-4904-8834-2a4538d60c8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001111090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.4001111090
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.4126633718
Short name T398
Test name
Test status
Simulation time 21591701998 ps
CPU time 110.84 seconds
Started Jun 07 07:47:32 PM PDT 24
Finished Jun 07 07:49:24 PM PDT 24
Peak memory 249836 kb
Host smart-239dc808-03a7-41b0-b0c7-9d6b3ef52f8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41266
33718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.4126633718
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2100185281
Short name T288
Test name
Test status
Simulation time 944784226 ps
CPU time 49.24 seconds
Started Jun 07 07:47:31 PM PDT 24
Finished Jun 07 07:48:21 PM PDT 24
Peak memory 255192 kb
Host smart-d4429d4a-9c51-4871-8879-ba5c2bf9418c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21001
85281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2100185281
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.1771463005
Short name T192
Test name
Test status
Simulation time 63553037770 ps
CPU time 1377.43 seconds
Started Jun 07 07:47:33 PM PDT 24
Finished Jun 07 08:10:31 PM PDT 24
Peak memory 289716 kb
Host smart-4cfe0b8c-1547-4de8-a515-d639c9be107a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771463005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.1771463005
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.467695009
Short name T563
Test name
Test status
Simulation time 24146918303 ps
CPU time 1371.51 seconds
Started Jun 07 07:47:32 PM PDT 24
Finished Jun 07 08:10:24 PM PDT 24
Peak memory 272900 kb
Host smart-dda65fc5-6edc-4ecc-b98d-e55789ccb601
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467695009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.467695009
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.2214092479
Short name T316
Test name
Test status
Simulation time 10340869681 ps
CPU time 221.98 seconds
Started Jun 07 07:47:31 PM PDT 24
Finished Jun 07 07:51:13 PM PDT 24
Peak memory 248188 kb
Host smart-cabc6916-e4b2-4f98-a267-5dd6a8b5834b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214092479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2214092479
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2260890729
Short name T108
Test name
Test status
Simulation time 1924637392 ps
CPU time 25.38 seconds
Started Jun 07 07:47:23 PM PDT 24
Finished Jun 07 07:47:50 PM PDT 24
Peak memory 248744 kb
Host smart-95689aa4-5b05-418f-adc4-49f4a7688924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22608
90729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2260890729
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.1901045255
Short name T423
Test name
Test status
Simulation time 1848960940 ps
CPU time 31.05 seconds
Started Jun 07 07:47:23 PM PDT 24
Finished Jun 07 07:47:56 PM PDT 24
Peak memory 248648 kb
Host smart-a8a2e059-d947-4b81-84d3-7f33f969bee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19010
45255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.1901045255
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.3391739854
Short name T278
Test name
Test status
Simulation time 722957855 ps
CPU time 22.34 seconds
Started Jun 07 07:47:32 PM PDT 24
Finished Jun 07 07:47:56 PM PDT 24
Peak memory 255684 kb
Host smart-0a027def-48be-4590-9a23-fccacbfff0e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33917
39854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3391739854
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1267157560
Short name T503
Test name
Test status
Simulation time 393587011 ps
CPU time 47.95 seconds
Started Jun 07 07:47:22 PM PDT 24
Finished Jun 07 07:48:12 PM PDT 24
Peak memory 255884 kb
Host smart-1dc3b9b3-2993-4b04-9d39-a4c508c9cad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12671
57560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1267157560
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1134108644
Short name T253
Test name
Test status
Simulation time 9179782931 ps
CPU time 512.1 seconds
Started Jun 07 07:47:31 PM PDT 24
Finished Jun 07 07:56:04 PM PDT 24
Peak memory 265188 kb
Host smart-bd92948e-539f-4b07-8c55-75be329318b4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134108644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1134108644
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.3451837681
Short name T657
Test name
Test status
Simulation time 63266084160 ps
CPU time 980.07 seconds
Started Jun 07 07:47:32 PM PDT 24
Finished Jun 07 08:03:53 PM PDT 24
Peak memory 284348 kb
Host smart-9b331fc8-e71a-4234-afe3-b575283f2cb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451837681 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.3451837681
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.250334288
Short name T604
Test name
Test status
Simulation time 46894925390 ps
CPU time 1192.82 seconds
Started Jun 07 07:47:37 PM PDT 24
Finished Jun 07 08:07:31 PM PDT 24
Peak memory 281084 kb
Host smart-9d903754-e7c1-4719-87f6-2cb2e7a00a89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250334288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.250334288
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.154769913
Short name T391
Test name
Test status
Simulation time 2146569118 ps
CPU time 75.08 seconds
Started Jun 07 07:47:31 PM PDT 24
Finished Jun 07 07:48:48 PM PDT 24
Peak memory 248880 kb
Host smart-3200445f-a381-44c3-9a56-8efa1e8652f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15476
9913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.154769913
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3598738109
Short name T407
Test name
Test status
Simulation time 2060914564 ps
CPU time 51.52 seconds
Started Jun 07 07:47:32 PM PDT 24
Finished Jun 07 07:48:24 PM PDT 24
Peak memory 255632 kb
Host smart-7bda678a-4b71-4a91-ba41-8dec8ab8dc8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35987
38109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3598738109
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.1060010608
Short name T6
Test name
Test status
Simulation time 36315895802 ps
CPU time 861.18 seconds
Started Jun 07 07:47:38 PM PDT 24
Finished Jun 07 08:02:02 PM PDT 24
Peak memory 267296 kb
Host smart-9746aae5-f97a-4a5a-8809-5e64f83fc4aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060010608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1060010608
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.3612316252
Short name T266
Test name
Test status
Simulation time 8850758634 ps
CPU time 368.47 seconds
Started Jun 07 07:47:36 PM PDT 24
Finished Jun 07 07:53:46 PM PDT 24
Peak memory 254984 kb
Host smart-2fe5a696-b8e4-46fe-866b-0abc80bb8165
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612316252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.3612316252
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.718494647
Short name T605
Test name
Test status
Simulation time 605716103 ps
CPU time 33.07 seconds
Started Jun 07 07:47:32 PM PDT 24
Finished Jun 07 07:48:06 PM PDT 24
Peak memory 248760 kb
Host smart-9e8544c4-0be4-46e8-95bd-76d231a44d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71849
4647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.718494647
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.4214411122
Short name T671
Test name
Test status
Simulation time 1233109734 ps
CPU time 49.68 seconds
Started Jun 07 07:47:31 PM PDT 24
Finished Jun 07 07:48:21 PM PDT 24
Peak memory 256796 kb
Host smart-42ee5157-77c9-4e28-9938-5b969b443e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42144
11122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.4214411122
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3556975330
Short name T624
Test name
Test status
Simulation time 718027151 ps
CPU time 40.83 seconds
Started Jun 07 07:47:39 PM PDT 24
Finished Jun 07 07:48:22 PM PDT 24
Peak memory 255364 kb
Host smart-20fbc1f4-8500-46e1-8a96-8cb4b98fac67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35569
75330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3556975330
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.1924334138
Short name T447
Test name
Test status
Simulation time 583954662 ps
CPU time 35.17 seconds
Started Jun 07 07:47:32 PM PDT 24
Finished Jun 07 07:48:08 PM PDT 24
Peak memory 256892 kb
Host smart-7a0ecc33-ab9d-47db-acab-12b01c2829b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19243
34138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1924334138
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.636615551
Short name T44
Test name
Test status
Simulation time 12305339714 ps
CPU time 868.9 seconds
Started Jun 07 07:47:38 PM PDT 24
Finished Jun 07 08:02:09 PM PDT 24
Peak memory 273152 kb
Host smart-780b0cb8-5b44-4e6f-bb85-b6598a917ea2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636615551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_han
dler_stress_all.636615551
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.700542357
Short name T601
Test name
Test status
Simulation time 16166356188 ps
CPU time 1374.59 seconds
Started Jun 07 07:47:38 PM PDT 24
Finished Jun 07 08:10:35 PM PDT 24
Peak memory 283664 kb
Host smart-cefd7515-b2b0-44e3-9b36-10f8e5a217d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700542357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.700542357
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.1741218583
Short name T457
Test name
Test status
Simulation time 3202898742 ps
CPU time 88.18 seconds
Started Jun 07 07:47:38 PM PDT 24
Finished Jun 07 07:49:08 PM PDT 24
Peak memory 256904 kb
Host smart-8adf86b2-3188-4d66-bee7-c1aede8701d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17412
18583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1741218583
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.2504616345
Short name T80
Test name
Test status
Simulation time 1345563823 ps
CPU time 12.9 seconds
Started Jun 07 07:47:39 PM PDT 24
Finished Jun 07 07:47:54 PM PDT 24
Peak memory 253928 kb
Host smart-4a232b65-20a1-4d25-b4aa-b0532546f8b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25046
16345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.2504616345
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.125330849
Short name T603
Test name
Test status
Simulation time 74896620066 ps
CPU time 1525.07 seconds
Started Jun 07 07:47:37 PM PDT 24
Finished Jun 07 08:13:04 PM PDT 24
Peak memory 288768 kb
Host smart-f20ddb98-b69d-4cf1-91ef-5bf006c537df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125330849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.125330849
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.3109861872
Short name T637
Test name
Test status
Simulation time 26179177537 ps
CPU time 1431.5 seconds
Started Jun 07 07:47:38 PM PDT 24
Finished Jun 07 08:11:32 PM PDT 24
Peak memory 273272 kb
Host smart-320a4c7e-ab8b-4576-816d-4864c4a80690
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109861872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3109861872
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.202372268
Short name T664
Test name
Test status
Simulation time 9629677592 ps
CPU time 316.46 seconds
Started Jun 07 07:47:37 PM PDT 24
Finished Jun 07 07:52:56 PM PDT 24
Peak memory 248348 kb
Host smart-8445826e-72d8-48ff-be29-ce693ce8275b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202372268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.202372268
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.3615133605
Short name T692
Test name
Test status
Simulation time 4552535959 ps
CPU time 63.51 seconds
Started Jun 07 07:47:39 PM PDT 24
Finished Jun 07 07:48:44 PM PDT 24
Peak memory 248784 kb
Host smart-319304dd-b9a1-4277-b874-a95d5bc16a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36151
33605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3615133605
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.777259106
Short name T221
Test name
Test status
Simulation time 1194391649 ps
CPU time 11.44 seconds
Started Jun 07 07:47:37 PM PDT 24
Finished Jun 07 07:47:51 PM PDT 24
Peak memory 253984 kb
Host smart-cbfa6205-c8e4-4186-89e0-05db5fee6bfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77725
9106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.777259106
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3713782010
Short name T72
Test name
Test status
Simulation time 838331337 ps
CPU time 48.08 seconds
Started Jun 07 07:47:38 PM PDT 24
Finished Jun 07 07:48:28 PM PDT 24
Peak memory 255760 kb
Host smart-f1a8a7d4-ce24-41e1-9bab-64357f662547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37137
82010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3713782010
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3329418458
Short name T450
Test name
Test status
Simulation time 72637303 ps
CPU time 7.89 seconds
Started Jun 07 07:47:38 PM PDT 24
Finished Jun 07 07:47:48 PM PDT 24
Peak memory 248680 kb
Host smart-b3663fd0-7900-4b7a-9a3e-58d61c985a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33294
18458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3329418458
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.2549997337
Short name T530
Test name
Test status
Simulation time 67085639689 ps
CPU time 2340.73 seconds
Started Jun 07 07:47:47 PM PDT 24
Finished Jun 07 08:26:50 PM PDT 24
Peak memory 289568 kb
Host smart-665aa8a4-3e70-4f05-845e-62283964b7cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549997337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2549997337
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.3774664357
Short name T696
Test name
Test status
Simulation time 7157170574 ps
CPU time 264.54 seconds
Started Jun 07 07:47:48 PM PDT 24
Finished Jun 07 07:52:15 PM PDT 24
Peak memory 256872 kb
Host smart-99ae5b23-d02e-4899-9ae8-bdffe665dc92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37746
64357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.3774664357
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.951577969
Short name T558
Test name
Test status
Simulation time 412381983 ps
CPU time 11.72 seconds
Started Jun 07 07:47:47 PM PDT 24
Finished Jun 07 07:48:01 PM PDT 24
Peak memory 248920 kb
Host smart-1bdad73f-8cd1-4591-8aaf-b2f0aa547c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95157
7969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.951577969
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.1210892313
Short name T62
Test name
Test status
Simulation time 11355845093 ps
CPU time 1147.73 seconds
Started Jun 07 07:47:50 PM PDT 24
Finished Jun 07 08:07:00 PM PDT 24
Peak memory 273300 kb
Host smart-a4c9a48c-33d4-4b00-b1ff-4969708d3d95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210892313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1210892313
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.450191239
Short name T669
Test name
Test status
Simulation time 43575103452 ps
CPU time 2762.46 seconds
Started Jun 07 07:47:48 PM PDT 24
Finished Jun 07 08:33:53 PM PDT 24
Peak memory 289500 kb
Host smart-e7c02a9b-6d7b-4bc6-9a56-6a097b2b7075
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450191239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.450191239
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.2535514415
Short name T313
Test name
Test status
Simulation time 30515612565 ps
CPU time 636.95 seconds
Started Jun 07 07:47:48 PM PDT 24
Finished Jun 07 07:58:27 PM PDT 24
Peak memory 248000 kb
Host smart-0020b38a-2f0b-4e8a-9750-1ffd50298518
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535514415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.2535514415
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.181287906
Short name T374
Test name
Test status
Simulation time 2388840032 ps
CPU time 22.09 seconds
Started Jun 07 07:47:38 PM PDT 24
Finished Jun 07 07:48:02 PM PDT 24
Peak memory 249000 kb
Host smart-0c8d8d9e-d3e9-4dd7-833f-147aaa0c81f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18128
7906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.181287906
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1074378748
Short name T420
Test name
Test status
Simulation time 809033952 ps
CPU time 40.11 seconds
Started Jun 07 07:47:48 PM PDT 24
Finished Jun 07 07:48:30 PM PDT 24
Peak memory 255704 kb
Host smart-8ab120d5-2564-470e-a2e7-9b2ad7f68a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10743
78748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1074378748
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3221885798
Short name T667
Test name
Test status
Simulation time 792197932 ps
CPU time 49.89 seconds
Started Jun 07 07:47:48 PM PDT 24
Finished Jun 07 07:48:39 PM PDT 24
Peak memory 255920 kb
Host smart-5066ffff-18be-44ca-ad85-e4d68211c69c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32218
85798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3221885798
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3542797385
Short name T524
Test name
Test status
Simulation time 286900822 ps
CPU time 17.18 seconds
Started Jun 07 07:47:39 PM PDT 24
Finished Jun 07 07:47:58 PM PDT 24
Peak memory 248708 kb
Host smart-88778a26-ace6-454b-a766-265d32e06281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35427
97385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3542797385
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1129159040
Short name T106
Test name
Test status
Simulation time 90148715562 ps
CPU time 2533.46 seconds
Started Jun 07 07:47:49 PM PDT 24
Finished Jun 07 08:30:05 PM PDT 24
Peak memory 286368 kb
Host smart-f19080fe-59e3-4520-8d7c-47a5f0b9b072
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129159040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1129159040
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.3545392882
Short name T213
Test name
Test status
Simulation time 45010466 ps
CPU time 3.95 seconds
Started Jun 07 07:45:03 PM PDT 24
Finished Jun 07 07:45:08 PM PDT 24
Peak memory 248844 kb
Host smart-388e9b7c-d52e-4540-a96e-357f33ac0bd0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3545392882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3545392882
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2012627683
Short name T117
Test name
Test status
Simulation time 50526994779 ps
CPU time 1527.05 seconds
Started Jun 07 07:44:53 PM PDT 24
Finished Jun 07 08:10:22 PM PDT 24
Peak memory 272504 kb
Host smart-10403fed-9f82-4cc9-a430-636d6591f25d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012627683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2012627683
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.3198801292
Short name T226
Test name
Test status
Simulation time 2015057954 ps
CPU time 24.43 seconds
Started Jun 07 07:45:02 PM PDT 24
Finished Jun 07 07:45:28 PM PDT 24
Peak memory 248724 kb
Host smart-dd4a2dab-4d6f-4949-8ea1-2fafb9e30aaa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3198801292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3198801292
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.900074929
Short name T607
Test name
Test status
Simulation time 1379012038 ps
CPU time 33.32 seconds
Started Jun 07 07:45:03 PM PDT 24
Finished Jun 07 07:45:38 PM PDT 24
Peak memory 248856 kb
Host smart-df79bd04-3bed-4734-b46c-aa8b98e835cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90007
4929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.900074929
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.737934640
Short name T280
Test name
Test status
Simulation time 3478692794 ps
CPU time 48.94 seconds
Started Jun 07 07:44:59 PM PDT 24
Finished Jun 07 07:45:49 PM PDT 24
Peak memory 255712 kb
Host smart-81d26f2e-4716-49b3-bfbf-f6ccd748fe19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73793
4640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.737934640
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2593751065
Short name T335
Test name
Test status
Simulation time 47407331648 ps
CPU time 2701.63 seconds
Started Jun 07 07:44:54 PM PDT 24
Finished Jun 07 08:29:57 PM PDT 24
Peak memory 288612 kb
Host smart-df36edb2-0616-45b6-9187-e17df0e799e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593751065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2593751065
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.3205926015
Short name T191
Test name
Test status
Simulation time 150664054663 ps
CPU time 1977.67 seconds
Started Jun 07 07:44:53 PM PDT 24
Finished Jun 07 08:17:53 PM PDT 24
Peak memory 288816 kb
Host smart-afb6d824-d154-45b3-b793-935f094fd96d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205926015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3205926015
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2830111768
Short name T300
Test name
Test status
Simulation time 10418555857 ps
CPU time 117.44 seconds
Started Jun 07 07:44:59 PM PDT 24
Finished Jun 07 07:46:58 PM PDT 24
Peak memory 255444 kb
Host smart-5d4082bb-3138-4d97-aefd-9578347512ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830111768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2830111768
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3074398611
Short name T415
Test name
Test status
Simulation time 364124035 ps
CPU time 22.86 seconds
Started Jun 07 07:44:55 PM PDT 24
Finished Jun 07 07:45:20 PM PDT 24
Peak memory 248816 kb
Host smart-4200bd0c-020a-475e-bafb-04aa11d2a018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30743
98611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3074398611
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1640370628
Short name T606
Test name
Test status
Simulation time 380022261 ps
CPU time 40.21 seconds
Started Jun 07 07:44:57 PM PDT 24
Finished Jun 07 07:45:39 PM PDT 24
Peak memory 255828 kb
Host smart-52b28303-54f4-4d38-a3aa-b74905765c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16403
70628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1640370628
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.2427507056
Short name T285
Test name
Test status
Simulation time 1449934782 ps
CPU time 24.88 seconds
Started Jun 07 07:45:03 PM PDT 24
Finished Jun 07 07:45:30 PM PDT 24
Peak memory 256544 kb
Host smart-c173b666-6eb5-4fcb-909e-66001271c580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24275
07056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2427507056
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.2482564133
Short name T649
Test name
Test status
Simulation time 1207914976 ps
CPU time 34.23 seconds
Started Jun 07 07:45:07 PM PDT 24
Finished Jun 07 07:45:44 PM PDT 24
Peak memory 256132 kb
Host smart-24c08ce4-c9ff-455a-818a-8bf7e2f2704d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24825
64133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.2482564133
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.2403465303
Short name T249
Test name
Test status
Simulation time 925488002 ps
CPU time 69.57 seconds
Started Jun 07 07:44:54 PM PDT 24
Finished Jun 07 07:46:05 PM PDT 24
Peak memory 249912 kb
Host smart-e3122570-dfef-4fd2-886c-e5346aed08c4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403465303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.2403465303
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.4057006714
Short name T596
Test name
Test status
Simulation time 410079229400 ps
CPU time 3695.22 seconds
Started Jun 07 07:45:04 PM PDT 24
Finished Jun 07 08:46:41 PM PDT 24
Peak memory 298076 kb
Host smart-44898b15-a87c-42f2-9aca-d083d80e955b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057006714 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.4057006714
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3504238095
Short name T60
Test name
Test status
Simulation time 70975019783 ps
CPU time 2380.84 seconds
Started Jun 07 07:47:58 PM PDT 24
Finished Jun 07 08:27:40 PM PDT 24
Peak memory 289008 kb
Host smart-3fa43d97-2787-4c4b-a905-ccc368f1581e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504238095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3504238095
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3563486886
Short name T65
Test name
Test status
Simulation time 2138722759 ps
CPU time 68.56 seconds
Started Jun 07 07:47:59 PM PDT 24
Finished Jun 07 07:49:08 PM PDT 24
Peak memory 256644 kb
Host smart-4f155420-cf04-4b2e-9c71-e860affa589b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35634
86886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3563486886
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.3923065780
Short name T553
Test name
Test status
Simulation time 3009334603 ps
CPU time 45.91 seconds
Started Jun 07 07:48:03 PM PDT 24
Finished Jun 07 07:48:50 PM PDT 24
Peak memory 255684 kb
Host smart-371157de-319f-4baf-a274-c89845cf2670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39230
65780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3923065780
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.3223109703
Short name T422
Test name
Test status
Simulation time 77048585657 ps
CPU time 1104.12 seconds
Started Jun 07 07:48:01 PM PDT 24
Finished Jun 07 08:06:26 PM PDT 24
Peak memory 288756 kb
Host smart-c06986cb-d64b-4f90-b786-3b21515302bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223109703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3223109703
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1198036737
Short name T5
Test name
Test status
Simulation time 12706340839 ps
CPU time 132.08 seconds
Started Jun 07 07:48:00 PM PDT 24
Finished Jun 07 07:50:14 PM PDT 24
Peak memory 248356 kb
Host smart-571f4990-8999-4435-bbd6-7ec5f77b1f15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198036737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1198036737
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3352838303
Short name T433
Test name
Test status
Simulation time 11721994317 ps
CPU time 64.75 seconds
Started Jun 07 07:47:50 PM PDT 24
Finished Jun 07 07:48:56 PM PDT 24
Peak memory 256932 kb
Host smart-8e656e6e-8aa1-4abb-b1d3-e6bde1757feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33528
38303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3352838303
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.2547970197
Short name T98
Test name
Test status
Simulation time 751560707 ps
CPU time 44.9 seconds
Started Jun 07 07:47:48 PM PDT 24
Finished Jun 07 07:48:35 PM PDT 24
Peak memory 256920 kb
Host smart-d6a9b13e-6592-42f8-b6f9-942a3729bbdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25479
70197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.2547970197
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.1115122541
Short name T295
Test name
Test status
Simulation time 216131400 ps
CPU time 36.5 seconds
Started Jun 07 07:48:01 PM PDT 24
Finished Jun 07 07:48:39 PM PDT 24
Peak memory 247736 kb
Host smart-01319cc7-d51b-4729-ba09-9b91eb601352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11151
22541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.1115122541
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.104212595
Short name T518
Test name
Test status
Simulation time 140010201 ps
CPU time 14.15 seconds
Started Jun 07 07:47:48 PM PDT 24
Finished Jun 07 07:48:04 PM PDT 24
Peak memory 256920 kb
Host smart-4be3e521-3a20-4972-99e1-499cbd5439a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10421
2595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.104212595
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.1189204687
Short name T113
Test name
Test status
Simulation time 1073766509 ps
CPU time 90.59 seconds
Started Jun 07 07:48:02 PM PDT 24
Finished Jun 07 07:49:33 PM PDT 24
Peak memory 256900 kb
Host smart-2e5f71cb-6d3a-4295-84d2-c6578aa22a12
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189204687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.1189204687
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.2858282040
Short name T194
Test name
Test status
Simulation time 47188829257 ps
CPU time 2265.89 seconds
Started Jun 07 07:48:01 PM PDT 24
Finished Jun 07 08:25:48 PM PDT 24
Peak memory 297544 kb
Host smart-02ef5442-414b-406e-8451-a915c437d9f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858282040 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.2858282040
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.881018621
Short name T525
Test name
Test status
Simulation time 6960328239 ps
CPU time 919.05 seconds
Started Jun 07 07:47:59 PM PDT 24
Finished Jun 07 08:03:19 PM PDT 24
Peak memory 270648 kb
Host smart-8a4f9ae1-2b87-456b-a79c-8ce143cf502d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881018621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.881018621
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2856641502
Short name T602
Test name
Test status
Simulation time 537345775 ps
CPU time 53.03 seconds
Started Jun 07 07:47:59 PM PDT 24
Finished Jun 07 07:48:53 PM PDT 24
Peak memory 248680 kb
Host smart-542d5e1e-66f4-4369-b867-e898feaf2042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28566
41502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2856641502
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.636694867
Short name T456
Test name
Test status
Simulation time 686653984 ps
CPU time 34 seconds
Started Jun 07 07:48:00 PM PDT 24
Finished Jun 07 07:48:35 PM PDT 24
Peak memory 255752 kb
Host smart-e3ed487d-10c7-4211-9649-541981f5d9f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63669
4867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.636694867
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.4278366489
Short name T333
Test name
Test status
Simulation time 834399617208 ps
CPU time 2734.5 seconds
Started Jun 07 07:47:58 PM PDT 24
Finished Jun 07 08:33:34 PM PDT 24
Peak memory 281536 kb
Host smart-8ec6ffe8-7cfb-4d8e-9da4-7479a71bcf63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278366489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.4278366489
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2360057981
Short name T441
Test name
Test status
Simulation time 316771073642 ps
CPU time 1401.81 seconds
Started Jun 07 07:48:03 PM PDT 24
Finished Jun 07 08:11:26 PM PDT 24
Peak memory 267244 kb
Host smart-a3497e72-38c2-4a83-bfed-517fd69154e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360057981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2360057981
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3323526477
Short name T638
Test name
Test status
Simulation time 448602615 ps
CPU time 15.4 seconds
Started Jun 07 07:48:01 PM PDT 24
Finished Jun 07 07:48:17 PM PDT 24
Peak memory 254780 kb
Host smart-04bc20c3-e0e1-49ea-af57-3936d4e1f9cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33235
26477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3323526477
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.251164365
Short name T88
Test name
Test status
Simulation time 527130272 ps
CPU time 16.66 seconds
Started Jun 07 07:47:59 PM PDT 24
Finished Jun 07 07:48:16 PM PDT 24
Peak memory 247792 kb
Host smart-adb3d949-26a2-48c1-b08c-6bae72f135fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25116
4365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.251164365
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.6802178
Short name T511
Test name
Test status
Simulation time 1030388225 ps
CPU time 58.27 seconds
Started Jun 07 07:47:59 PM PDT 24
Finished Jun 07 07:48:59 PM PDT 24
Peak memory 256812 kb
Host smart-49001207-c6f7-4724-be54-6cc3f8f570f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68021
78 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.6802178
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1240758915
Short name T406
Test name
Test status
Simulation time 266099604 ps
CPU time 6.49 seconds
Started Jun 07 07:48:00 PM PDT 24
Finished Jun 07 07:48:07 PM PDT 24
Peak memory 248732 kb
Host smart-b18b1a3e-313c-4d15-90c1-6316e5c213ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12407
58915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1240758915
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1913651035
Short name T261
Test name
Test status
Simulation time 56688152614 ps
CPU time 1497.49 seconds
Started Jun 07 07:48:08 PM PDT 24
Finished Jun 07 08:13:07 PM PDT 24
Peak memory 287284 kb
Host smart-0f4f9a56-b118-4e93-92e9-bf565978e583
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913651035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1913651035
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.1461232451
Short name T633
Test name
Test status
Simulation time 431245235536 ps
CPU time 2044.33 seconds
Started Jun 07 07:48:09 PM PDT 24
Finished Jun 07 08:22:15 PM PDT 24
Peak memory 273328 kb
Host smart-71823da2-be98-48ed-a6d4-373b812e974c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461232451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1461232451
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.97293909
Short name T636
Test name
Test status
Simulation time 3613604133 ps
CPU time 210.38 seconds
Started Jun 07 07:48:09 PM PDT 24
Finished Jun 07 07:51:40 PM PDT 24
Peak memory 256656 kb
Host smart-56d01347-eb32-4f51-afbe-24dab73b713e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97293
909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.97293909
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1756600833
Short name T269
Test name
Test status
Simulation time 5033966968 ps
CPU time 80.78 seconds
Started Jun 07 07:48:10 PM PDT 24
Finished Jun 07 07:49:32 PM PDT 24
Peak memory 255228 kb
Host smart-73b287a1-2e88-4b0c-920a-ec12a5f339ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17566
00833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1756600833
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1824070301
Short name T339
Test name
Test status
Simulation time 108901369151 ps
CPU time 1782.93 seconds
Started Jun 07 07:48:09 PM PDT 24
Finished Jun 07 08:17:54 PM PDT 24
Peak memory 273392 kb
Host smart-1b56d3bc-03f4-4863-8739-29a7942a292d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824070301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1824070301
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.216462932
Short name T554
Test name
Test status
Simulation time 70243083736 ps
CPU time 1095.59 seconds
Started Jun 07 07:48:09 PM PDT 24
Finished Jun 07 08:06:26 PM PDT 24
Peak memory 272360 kb
Host smart-3facd085-cb46-4e8f-b154-afabd7f4c864
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216462932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.216462932
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.378901762
Short name T99
Test name
Test status
Simulation time 21061449169 ps
CPU time 226.4 seconds
Started Jun 07 07:48:10 PM PDT 24
Finished Jun 07 07:51:58 PM PDT 24
Peak memory 253820 kb
Host smart-08341a39-be75-497b-a1a7-497d68c4773f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378901762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.378901762
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.466486843
Short name T363
Test name
Test status
Simulation time 267530526 ps
CPU time 7.92 seconds
Started Jun 07 07:48:08 PM PDT 24
Finished Jun 07 07:48:17 PM PDT 24
Peak memory 252444 kb
Host smart-927c65de-a062-4fb2-b52e-819a53be0a8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46648
6843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.466486843
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2457339078
Short name T91
Test name
Test status
Simulation time 2215332849 ps
CPU time 64.72 seconds
Started Jun 07 07:48:10 PM PDT 24
Finished Jun 07 07:49:16 PM PDT 24
Peak memory 255740 kb
Host smart-dad4effc-3ae9-4e42-8673-d3f027820ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24573
39078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2457339078
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.256529737
Short name T63
Test name
Test status
Simulation time 991966658 ps
CPU time 36 seconds
Started Jun 07 07:48:08 PM PDT 24
Finished Jun 07 07:48:45 PM PDT 24
Peak memory 256824 kb
Host smart-9a99d9c2-0bec-48e7-af47-95ee3abc85b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25652
9737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.256529737
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.568888740
Short name T449
Test name
Test status
Simulation time 262203126 ps
CPU time 30.14 seconds
Started Jun 07 07:48:09 PM PDT 24
Finished Jun 07 07:48:41 PM PDT 24
Peak memory 256840 kb
Host smart-6d2ebe55-876a-4331-bfe9-2ac29b699def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56888
8740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.568888740
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.1002819078
Short name T616
Test name
Test status
Simulation time 98040791919 ps
CPU time 1666.63 seconds
Started Jun 07 07:48:20 PM PDT 24
Finished Jun 07 08:16:08 PM PDT 24
Peak memory 272652 kb
Host smart-b9fd86de-aa0d-4b49-b015-a0f773acfe3a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002819078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.1002819078
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.2498840713
Short name T284
Test name
Test status
Simulation time 126947355683 ps
CPU time 3233.14 seconds
Started Jun 07 07:48:18 PM PDT 24
Finished Jun 07 08:42:13 PM PDT 24
Peak memory 333356 kb
Host smart-6ef71cd8-6a9d-4b0f-9bae-bab9e60afa70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498840713 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.2498840713
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1790186737
Short name T467
Test name
Test status
Simulation time 71629313201 ps
CPU time 1414.08 seconds
Started Jun 07 07:48:19 PM PDT 24
Finished Jun 07 08:11:54 PM PDT 24
Peak memory 266384 kb
Host smart-cbc2963f-4916-4e1b-b6e6-70f66bf7cff6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790186737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1790186737
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.395935508
Short name T712
Test name
Test status
Simulation time 16704690344 ps
CPU time 95.32 seconds
Started Jun 07 07:48:20 PM PDT 24
Finished Jun 07 07:49:56 PM PDT 24
Peak memory 256836 kb
Host smart-93c76fdc-6668-4a9c-80d2-d16ee9095ef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39593
5508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.395935508
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.1323159201
Short name T21
Test name
Test status
Simulation time 176692051 ps
CPU time 17.1 seconds
Started Jun 07 07:48:18 PM PDT 24
Finished Jun 07 07:48:36 PM PDT 24
Peak memory 248676 kb
Host smart-84bc164e-2ade-448b-97b2-8cb93e2f3131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13231
59201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.1323159201
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3688132580
Short name T561
Test name
Test status
Simulation time 18026286164 ps
CPU time 1324.43 seconds
Started Jun 07 07:48:16 PM PDT 24
Finished Jun 07 08:10:22 PM PDT 24
Peak memory 281640 kb
Host smart-80b78a8e-61f7-46d5-b41e-c3653949e5f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688132580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3688132580
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.835958592
Short name T509
Test name
Test status
Simulation time 49180951543 ps
CPU time 1544.37 seconds
Started Jun 07 07:48:19 PM PDT 24
Finished Jun 07 08:14:04 PM PDT 24
Peak memory 289080 kb
Host smart-ebd63768-e8c0-4c39-a8fe-54b42d9bcacf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835958592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.835958592
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2795882266
Short name T459
Test name
Test status
Simulation time 2642069191 ps
CPU time 20.41 seconds
Started Jun 07 07:48:25 PM PDT 24
Finished Jun 07 07:48:46 PM PDT 24
Peak memory 256988 kb
Host smart-0fb806bd-97ec-4115-b081-e1810f1fd569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27958
82266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2795882266
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.4170443012
Short name T111
Test name
Test status
Simulation time 190715929 ps
CPU time 10.05 seconds
Started Jun 07 07:48:23 PM PDT 24
Finished Jun 07 07:48:34 PM PDT 24
Peak memory 255728 kb
Host smart-76e4a029-22e8-4d92-a3a1-e00ddc086213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41704
43012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.4170443012
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1991131604
Short name T688
Test name
Test status
Simulation time 613140200 ps
CPU time 13.76 seconds
Started Jun 07 07:48:18 PM PDT 24
Finished Jun 07 07:48:33 PM PDT 24
Peak memory 247528 kb
Host smart-df725e1e-ef6e-45ce-b78b-deb6fe709764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19911
31604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1991131604
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.1406137445
Short name T555
Test name
Test status
Simulation time 2512764936 ps
CPU time 17.9 seconds
Started Jun 07 07:48:18 PM PDT 24
Finished Jun 07 07:48:37 PM PDT 24
Peak memory 256924 kb
Host smart-73cb9b54-87e6-4353-aee1-c5dc533082d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14061
37445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.1406137445
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.950570313
Short name T646
Test name
Test status
Simulation time 70114081769 ps
CPU time 2172.47 seconds
Started Jun 07 07:48:35 PM PDT 24
Finished Jun 07 08:24:50 PM PDT 24
Peak memory 289224 kb
Host smart-0486bf26-4e7d-4ff1-8691-6482e85da92b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950570313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.950570313
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1124660069
Short name T236
Test name
Test status
Simulation time 10138132595 ps
CPU time 139.83 seconds
Started Jun 07 07:48:37 PM PDT 24
Finished Jun 07 07:50:59 PM PDT 24
Peak memory 256964 kb
Host smart-530e76f0-aca1-4c5b-ac47-ab3f131fa19e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11246
60069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1124660069
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3557044563
Short name T367
Test name
Test status
Simulation time 713177824 ps
CPU time 18.42 seconds
Started Jun 07 07:48:27 PM PDT 24
Finished Jun 07 07:48:46 PM PDT 24
Peak memory 255116 kb
Host smart-bf19108e-202c-439a-b1f0-5ae46332eceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35570
44563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3557044563
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.3632009045
Short name T430
Test name
Test status
Simulation time 139816816968 ps
CPU time 1801.55 seconds
Started Jun 07 07:48:36 PM PDT 24
Finished Jun 07 08:18:40 PM PDT 24
Peak memory 272900 kb
Host smart-b428469f-ba55-47e9-8d5b-aaf37094fee5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632009045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3632009045
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.4092048511
Short name T483
Test name
Test status
Simulation time 22292956090 ps
CPU time 422.31 seconds
Started Jun 07 07:48:36 PM PDT 24
Finished Jun 07 07:55:40 PM PDT 24
Peak memory 248332 kb
Host smart-b0c189d6-c32e-4a05-85df-e603792e20fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092048511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.4092048511
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.4157291094
Short name T537
Test name
Test status
Simulation time 256104627 ps
CPU time 23.36 seconds
Started Jun 07 07:48:27 PM PDT 24
Finished Jun 07 07:48:51 PM PDT 24
Peak memory 248652 kb
Host smart-3c48c01b-acef-403c-aec5-4bed9de01518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41572
91094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.4157291094
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.554891722
Short name T397
Test name
Test status
Simulation time 1033415762 ps
CPU time 28.56 seconds
Started Jun 07 07:48:27 PM PDT 24
Finished Jun 07 07:48:57 PM PDT 24
Peak memory 255536 kb
Host smart-337a5978-e1f3-446e-8319-5d068fbc6091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55489
1722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.554891722
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.1948174942
Short name T421
Test name
Test status
Simulation time 1048016756 ps
CPU time 68.98 seconds
Started Jun 07 07:48:38 PM PDT 24
Finished Jun 07 07:49:48 PM PDT 24
Peak memory 256596 kb
Host smart-45131b85-31b0-404e-a960-16bcb283fb72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19481
74942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1948174942
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2035783695
Short name T405
Test name
Test status
Simulation time 821525059 ps
CPU time 56.65 seconds
Started Jun 07 07:48:27 PM PDT 24
Finished Jun 07 07:49:24 PM PDT 24
Peak memory 248728 kb
Host smart-a00dc7f1-823e-467b-a6fa-c15b63ab7e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20357
83695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2035783695
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.684506819
Short name T114
Test name
Test status
Simulation time 195584226483 ps
CPU time 2637.88 seconds
Started Jun 07 07:48:34 PM PDT 24
Finished Jun 07 08:32:33 PM PDT 24
Peak memory 289628 kb
Host smart-c07b8124-91b0-4717-84d6-17cac21067d2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684506819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_han
dler_stress_all.684506819
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.1668668799
Short name T85
Test name
Test status
Simulation time 88037058911 ps
CPU time 4112.02 seconds
Started Jun 07 07:48:36 PM PDT 24
Finished Jun 07 08:57:10 PM PDT 24
Peak memory 338824 kb
Host smart-d78887f8-96cd-4eb5-a188-147a13fe6cab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668668799 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.1668668799
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.4279207684
Short name T521
Test name
Test status
Simulation time 319114201 ps
CPU time 19.48 seconds
Started Jun 07 07:48:38 PM PDT 24
Finished Jun 07 07:48:59 PM PDT 24
Peak memory 255176 kb
Host smart-3f720bc7-e543-4b2e-b52a-fbe749b6a6ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42792
07684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.4279207684
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2566041863
Short name T647
Test name
Test status
Simulation time 3292990285 ps
CPU time 29.43 seconds
Started Jun 07 07:48:36 PM PDT 24
Finished Jun 07 07:49:07 PM PDT 24
Peak memory 255204 kb
Host smart-e00e9ca2-0818-4fd5-b1e7-f4e009f62799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25660
41863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2566041863
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3212695956
Short name T627
Test name
Test status
Simulation time 11397993308 ps
CPU time 885.49 seconds
Started Jun 07 07:48:36 PM PDT 24
Finished Jun 07 08:03:23 PM PDT 24
Peak memory 272692 kb
Host smart-a9179031-df5f-42b4-b936-13896ebf44d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212695956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3212695956
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1014377072
Short name T546
Test name
Test status
Simulation time 24227822936 ps
CPU time 1636.67 seconds
Started Jun 07 07:48:35 PM PDT 24
Finished Jun 07 08:15:54 PM PDT 24
Peak memory 268292 kb
Host smart-7b3b724b-5c6f-42a2-8d38-7dc3535f4914
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014377072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1014377072
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1493136942
Short name T498
Test name
Test status
Simulation time 16886401785 ps
CPU time 180.26 seconds
Started Jun 07 07:48:37 PM PDT 24
Finished Jun 07 07:51:40 PM PDT 24
Peak memory 248160 kb
Host smart-c802591f-a3d9-4f65-8570-2e7998f3cb54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493136942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1493136942
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3558678202
Short name T222
Test name
Test status
Simulation time 2344851042 ps
CPU time 18.71 seconds
Started Jun 07 07:48:36 PM PDT 24
Finished Jun 07 07:48:56 PM PDT 24
Peak memory 256608 kb
Host smart-76bf2949-6d86-43e7-a941-377314bb4043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35586
78202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3558678202
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.2976339471
Short name T539
Test name
Test status
Simulation time 1712516981 ps
CPU time 31.37 seconds
Started Jun 07 07:48:38 PM PDT 24
Finished Jun 07 07:49:11 PM PDT 24
Peak memory 248896 kb
Host smart-89bc2160-224d-4477-8652-78289fd574d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29763
39471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.2976339471
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.851665167
Short name T76
Test name
Test status
Simulation time 726219036 ps
CPU time 45.78 seconds
Started Jun 07 07:48:34 PM PDT 24
Finished Jun 07 07:49:20 PM PDT 24
Peak memory 256068 kb
Host smart-638bdb27-d9c5-499d-bb77-8b2162e7b111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85166
5167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.851665167
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2091401540
Short name T473
Test name
Test status
Simulation time 7505791883 ps
CPU time 34.25 seconds
Started Jun 07 07:48:37 PM PDT 24
Finished Jun 07 07:49:13 PM PDT 24
Peak memory 248996 kb
Host smart-763f49d5-8b95-418d-853d-3c977643e5f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20914
01540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2091401540
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.1740205540
Short name T710
Test name
Test status
Simulation time 132917381321 ps
CPU time 2191.72 seconds
Started Jun 07 07:48:36 PM PDT 24
Finished Jun 07 08:25:10 PM PDT 24
Peak memory 273356 kb
Host smart-77995f34-5e02-46ef-8f61-fda11f290aa7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740205540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.1740205540
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.4285723162
Short name T531
Test name
Test status
Simulation time 8197218566 ps
CPU time 860.56 seconds
Started Jun 07 07:48:50 PM PDT 24
Finished Jun 07 08:03:13 PM PDT 24
Peak memory 272420 kb
Host smart-dde72c8d-76c3-436a-9da9-e26cea476f14
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285723162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.4285723162
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.3387662766
Short name T101
Test name
Test status
Simulation time 676638969 ps
CPU time 10.32 seconds
Started Jun 07 07:48:45 PM PDT 24
Finished Jun 07 07:48:57 PM PDT 24
Peak memory 254216 kb
Host smart-e3798073-3f3d-42fa-a09b-bd7eee0856ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33876
62766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3387662766
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1960818296
Short name T359
Test name
Test status
Simulation time 420811381 ps
CPU time 29.73 seconds
Started Jun 07 07:48:50 PM PDT 24
Finished Jun 07 07:49:22 PM PDT 24
Peak memory 255404 kb
Host smart-79b62b2d-c6f8-4e92-bcad-4bba54afe85e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19608
18296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1960818296
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.3057629194
Short name T706
Test name
Test status
Simulation time 24821418883 ps
CPU time 1051.01 seconds
Started Jun 07 07:48:50 PM PDT 24
Finished Jun 07 08:06:22 PM PDT 24
Peak memory 273372 kb
Host smart-9b615aea-ea35-49c2-a827-89430e6ac92f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057629194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3057629194
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.3265627548
Short name T308
Test name
Test status
Simulation time 67071602959 ps
CPU time 426.35 seconds
Started Jun 07 07:48:45 PM PDT 24
Finished Jun 07 07:55:53 PM PDT 24
Peak memory 248476 kb
Host smart-36afcf94-54ab-420c-8043-862a84508fe9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265627548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3265627548
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1758315786
Short name T588
Test name
Test status
Simulation time 756735824 ps
CPU time 29.3 seconds
Started Jun 07 07:48:46 PM PDT 24
Finished Jun 07 07:49:18 PM PDT 24
Peak memory 256824 kb
Host smart-2388a3c7-e3ac-4574-b708-1f8691ccd0ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17583
15786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1758315786
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.1409853454
Short name T69
Test name
Test status
Simulation time 304063621 ps
CPU time 12.89 seconds
Started Jun 07 07:48:45 PM PDT 24
Finished Jun 07 07:48:59 PM PDT 24
Peak memory 248664 kb
Host smart-8c811a77-8290-4e3a-a7a6-146d3746fd83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14098
53454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.1409853454
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.1063670365
Short name T267
Test name
Test status
Simulation time 335735444 ps
CPU time 24.62 seconds
Started Jun 07 07:48:51 PM PDT 24
Finished Jun 07 07:49:18 PM PDT 24
Peak memory 256012 kb
Host smart-37781de2-0e4d-4729-94a2-e7f0f195358f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10636
70365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1063670365
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.3152548935
Short name T371
Test name
Test status
Simulation time 113424261 ps
CPU time 10.4 seconds
Started Jun 07 07:48:36 PM PDT 24
Finished Jun 07 07:48:48 PM PDT 24
Peak memory 256936 kb
Host smart-307b0979-4e91-460c-9379-ab019c173272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31525
48935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3152548935
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1844224102
Short name T119
Test name
Test status
Simulation time 23188923222 ps
CPU time 1017.83 seconds
Started Jun 07 07:48:49 PM PDT 24
Finished Jun 07 08:05:49 PM PDT 24
Peak memory 289788 kb
Host smart-dd2f7458-e451-4714-9c27-f20308b9cf31
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844224102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1844224102
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2160868965
Short name T257
Test name
Test status
Simulation time 59591072402 ps
CPU time 1859 seconds
Started Jun 07 07:48:52 PM PDT 24
Finished Jun 07 08:19:55 PM PDT 24
Peak memory 272688 kb
Host smart-b43eefd5-9d20-4fe6-9a8f-1af8444845ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160868965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2160868965
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.2715183550
Short name T389
Test name
Test status
Simulation time 36305572752 ps
CPU time 319.21 seconds
Started Jun 07 07:48:51 PM PDT 24
Finished Jun 07 07:54:13 PM PDT 24
Peak memory 256944 kb
Host smart-f13b88a7-640d-4eb9-a666-7730f7236667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27151
83550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.2715183550
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.705531726
Short name T402
Test name
Test status
Simulation time 144789952 ps
CPU time 10.78 seconds
Started Jun 07 07:48:51 PM PDT 24
Finished Jun 07 07:49:04 PM PDT 24
Peak memory 253372 kb
Host smart-c39d0524-6faa-4102-bb5d-39c294e54ca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70553
1726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.705531726
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.838161232
Short name T634
Test name
Test status
Simulation time 14075583216 ps
CPU time 678.42 seconds
Started Jun 07 07:48:53 PM PDT 24
Finished Jun 07 08:00:15 PM PDT 24
Peak memory 266224 kb
Host smart-751f5fb5-3c21-4d92-b8b6-069ff0daed35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838161232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.838161232
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3263259486
Short name T613
Test name
Test status
Simulation time 55967828827 ps
CPU time 3118.56 seconds
Started Jun 07 07:48:52 PM PDT 24
Finished Jun 07 08:40:54 PM PDT 24
Peak memory 288712 kb
Host smart-ca91cdf8-c285-4848-adcd-8e73e43245c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263259486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3263259486
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3061262585
Short name T599
Test name
Test status
Simulation time 1935774724 ps
CPU time 76.93 seconds
Started Jun 07 07:48:54 PM PDT 24
Finished Jun 07 07:50:14 PM PDT 24
Peak memory 248204 kb
Host smart-eff782c3-72c5-4ca6-871d-3761a7276b22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061262585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3061262585
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.1201712177
Short name T535
Test name
Test status
Simulation time 813940807 ps
CPU time 20.71 seconds
Started Jun 07 07:48:45 PM PDT 24
Finished Jun 07 07:49:08 PM PDT 24
Peak memory 248724 kb
Host smart-14c2b7cc-c90c-42d7-82ab-3747e676ab2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12017
12177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1201712177
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.134451877
Short name T373
Test name
Test status
Simulation time 231320501 ps
CPU time 11.95 seconds
Started Jun 07 07:48:51 PM PDT 24
Finished Jun 07 07:49:05 PM PDT 24
Peak memory 247648 kb
Host smart-407154ae-c300-476c-8861-6360d1689dc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13445
1877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.134451877
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.4214918614
Short name T631
Test name
Test status
Simulation time 332276669 ps
CPU time 5.2 seconds
Started Jun 07 07:48:52 PM PDT 24
Finished Jun 07 07:49:00 PM PDT 24
Peak memory 239328 kb
Host smart-c154d5ac-fb71-419b-a1fa-0cf4af5e171e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42149
18614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.4214918614
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.4117225057
Short name T532
Test name
Test status
Simulation time 380171318 ps
CPU time 14.43 seconds
Started Jun 07 07:48:45 PM PDT 24
Finished Jun 07 07:49:01 PM PDT 24
Peak memory 256908 kb
Host smart-4fc0abf8-7e50-46db-9905-166f8c49102a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41172
25057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.4117225057
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2111775364
Short name T277
Test name
Test status
Simulation time 61958313913 ps
CPU time 3158.36 seconds
Started Jun 07 07:48:52 PM PDT 24
Finished Jun 07 08:41:34 PM PDT 24
Peak memory 289764 kb
Host smart-8a3335b9-1ea3-4fbb-af8f-ccc313b7f5d2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111775364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2111775364
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.3396641272
Short name T57
Test name
Test status
Simulation time 73031022074 ps
CPU time 3273.36 seconds
Started Jun 07 07:48:51 PM PDT 24
Finished Jun 07 08:43:28 PM PDT 24
Peak memory 322064 kb
Host smart-e6847b90-d2d5-45a6-98f7-734198b9fd82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396641272 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.3396641272
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.863210898
Short name T245
Test name
Test status
Simulation time 205752301047 ps
CPU time 1570.96 seconds
Started Jun 07 07:49:00 PM PDT 24
Finished Jun 07 08:15:13 PM PDT 24
Peak memory 289156 kb
Host smart-b479041b-4e0e-4300-9d6d-e355b5d3e542
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863210898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.863210898
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3772073418
Short name T223
Test name
Test status
Simulation time 6489653593 ps
CPU time 301.23 seconds
Started Jun 07 07:49:01 PM PDT 24
Finished Jun 07 07:54:04 PM PDT 24
Peak memory 256944 kb
Host smart-a6b43f3b-0d54-4827-b7ba-83a028ebf401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37720
73418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3772073418
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.696848602
Short name T529
Test name
Test status
Simulation time 130326758 ps
CPU time 8.16 seconds
Started Jun 07 07:48:58 PM PDT 24
Finished Jun 07 07:49:08 PM PDT 24
Peak memory 251720 kb
Host smart-fba8d447-0b77-46ee-82b6-02070b3c635f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69684
8602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.696848602
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3320689108
Short name T248
Test name
Test status
Simulation time 70321116246 ps
CPU time 1097.83 seconds
Started Jun 07 07:49:01 PM PDT 24
Finished Jun 07 08:07:21 PM PDT 24
Peak memory 270952 kb
Host smart-dc4c0aec-d4b1-4017-9e1f-25d8b3f26c07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320689108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3320689108
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2216916099
Short name T611
Test name
Test status
Simulation time 54117396292 ps
CPU time 1258.42 seconds
Started Jun 07 07:49:01 PM PDT 24
Finished Jun 07 08:10:01 PM PDT 24
Peak memory 288960 kb
Host smart-51eb7757-5b89-4597-b8f6-8cc0dad0a0c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216916099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2216916099
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3317762438
Short name T319
Test name
Test status
Simulation time 9508729392 ps
CPU time 412.47 seconds
Started Jun 07 07:49:00 PM PDT 24
Finished Jun 07 07:55:55 PM PDT 24
Peak memory 248212 kb
Host smart-8e7a6010-7c1a-4887-98db-4b444f25edee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317762438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3317762438
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3478848474
Short name T587
Test name
Test status
Simulation time 247393594 ps
CPU time 13.22 seconds
Started Jun 07 07:48:52 PM PDT 24
Finished Jun 07 07:49:08 PM PDT 24
Peak memory 248652 kb
Host smart-12cb6c22-6172-4b41-b170-1a39217ea9d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34788
48474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3478848474
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.4103781577
Short name T574
Test name
Test status
Simulation time 506200827 ps
CPU time 32.36 seconds
Started Jun 07 07:48:54 PM PDT 24
Finished Jun 07 07:49:29 PM PDT 24
Peak memory 256568 kb
Host smart-bf158ca3-d6d9-4aa7-a487-513db8395b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41037
81577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.4103781577
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2937565422
Short name T293
Test name
Test status
Simulation time 12319976617 ps
CPU time 44.78 seconds
Started Jun 07 07:49:00 PM PDT 24
Finished Jun 07 07:49:47 PM PDT 24
Peak memory 255428 kb
Host smart-93bef504-cf12-46ed-bbca-d696ae7af48a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29375
65422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2937565422
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.1008615412
Short name T652
Test name
Test status
Simulation time 253896467 ps
CPU time 5.59 seconds
Started Jun 07 07:48:51 PM PDT 24
Finished Jun 07 07:48:59 PM PDT 24
Peak memory 240444 kb
Host smart-d35590c6-5206-44dc-9049-4577cc18d13f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10086
15412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.1008615412
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.838857757
Short name T479
Test name
Test status
Simulation time 188846871675 ps
CPU time 3809.29 seconds
Started Jun 07 07:48:59 PM PDT 24
Finished Jun 07 08:52:31 PM PDT 24
Peak memory 306172 kb
Host smart-5fc1a651-f13d-416f-816d-c9902cac45d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838857757 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.838857757
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.1715600626
Short name T709
Test name
Test status
Simulation time 125943680432 ps
CPU time 1462.55 seconds
Started Jun 07 07:49:06 PM PDT 24
Finished Jun 07 08:13:31 PM PDT 24
Peak memory 267240 kb
Host smart-38d87c03-a1b5-4bd1-b42b-43cd3cb0fe6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715600626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1715600626
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.4273577345
Short name T465
Test name
Test status
Simulation time 4905709425 ps
CPU time 147.01 seconds
Started Jun 07 07:49:07 PM PDT 24
Finished Jun 07 07:51:36 PM PDT 24
Peak memory 256788 kb
Host smart-23f14a71-5ad5-4e95-9d75-275712e17834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42735
77345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.4273577345
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.86860412
Short name T620
Test name
Test status
Simulation time 939164904 ps
CPU time 54.42 seconds
Started Jun 07 07:49:02 PM PDT 24
Finished Jun 07 07:49:58 PM PDT 24
Peak memory 248648 kb
Host smart-6e378093-8599-4600-973a-032153c97c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86860
412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.86860412
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.4179579157
Short name T331
Test name
Test status
Simulation time 46964797155 ps
CPU time 1342.64 seconds
Started Jun 07 07:49:07 PM PDT 24
Finished Jun 07 08:11:31 PM PDT 24
Peak memory 281556 kb
Host smart-86272026-b350-48e9-b061-be79d75a39ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179579157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.4179579157
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.3254619128
Short name T394
Test name
Test status
Simulation time 7227026939 ps
CPU time 789.71 seconds
Started Jun 07 07:49:07 PM PDT 24
Finished Jun 07 08:02:19 PM PDT 24
Peak memory 273336 kb
Host smart-1afd6ae8-df95-4723-bc33-39ea5014d836
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254619128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3254619128
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.232808599
Short name T326
Test name
Test status
Simulation time 5582735369 ps
CPU time 217.09 seconds
Started Jun 07 07:49:07 PM PDT 24
Finished Jun 07 07:52:46 PM PDT 24
Peak memory 248044 kb
Host smart-2bbd6f1f-b8a4-428d-9196-0a45408fc986
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232808599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.232808599
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1477036576
Short name T382
Test name
Test status
Simulation time 9686962319 ps
CPU time 36.52 seconds
Started Jun 07 07:48:58 PM PDT 24
Finished Jun 07 07:49:37 PM PDT 24
Peak memory 256236 kb
Host smart-b2c9ade5-d373-476b-bd7a-6e9a4ae219fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14770
36576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1477036576
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.2365639815
Short name T496
Test name
Test status
Simulation time 417042916 ps
CPU time 14.55 seconds
Started Jun 07 07:49:00 PM PDT 24
Finished Jun 07 07:49:17 PM PDT 24
Peak memory 248996 kb
Host smart-71d61f0c-fb90-4737-b938-ee99b4d7490a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23656
39815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2365639815
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.2953038938
Short name T275
Test name
Test status
Simulation time 116383197 ps
CPU time 6.4 seconds
Started Jun 07 07:49:07 PM PDT 24
Finished Jun 07 07:49:15 PM PDT 24
Peak memory 239436 kb
Host smart-e81d9373-3ebb-4139-8bb5-165f114a2b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29530
38938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2953038938
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.872855415
Short name T82
Test name
Test status
Simulation time 747522965 ps
CPU time 8.91 seconds
Started Jun 07 07:48:58 PM PDT 24
Finished Jun 07 07:49:09 PM PDT 24
Peak memory 250864 kb
Host smart-86f16cc9-c582-4020-a698-16a48ecfe328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87285
5415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.872855415
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2965039030
Short name T347
Test name
Test status
Simulation time 27043969433 ps
CPU time 1638.74 seconds
Started Jun 07 07:49:08 PM PDT 24
Finished Jun 07 08:16:29 PM PDT 24
Peak memory 281564 kb
Host smart-37ddaf51-697b-47bc-a5fc-f3e8b4e9a924
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965039030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2965039030
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.2243269200
Short name T26
Test name
Test status
Simulation time 66301909516 ps
CPU time 1913.13 seconds
Started Jun 07 07:49:07 PM PDT 24
Finished Jun 07 08:21:02 PM PDT 24
Peak memory 305324 kb
Host smart-8033367c-792c-400b-9d4d-afc39435efe1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243269200 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.2243269200
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.4125457978
Short name T212
Test name
Test status
Simulation time 55936614 ps
CPU time 2.6 seconds
Started Jun 07 07:45:02 PM PDT 24
Finished Jun 07 07:45:05 PM PDT 24
Peak memory 248884 kb
Host smart-af7a8635-f98a-4c83-8274-81a5de8e9e4d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4125457978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.4125457978
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3071805897
Short name T92
Test name
Test status
Simulation time 45049953216 ps
CPU time 2829.65 seconds
Started Jun 07 07:45:07 PM PDT 24
Finished Jun 07 08:32:20 PM PDT 24
Peak memory 288792 kb
Host smart-bfa8bd28-f766-45d8-bdce-8060e02e76a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071805897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3071805897
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1330849424
Short name T701
Test name
Test status
Simulation time 358183672 ps
CPU time 11.97 seconds
Started Jun 07 07:44:57 PM PDT 24
Finished Jun 07 07:45:10 PM PDT 24
Peak memory 248684 kb
Host smart-3a68791a-5a8b-42af-8c7a-9c42a4807809
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1330849424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1330849424
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.1580550396
Short name T560
Test name
Test status
Simulation time 59749160328 ps
CPU time 236.68 seconds
Started Jun 07 07:44:56 PM PDT 24
Finished Jun 07 07:48:54 PM PDT 24
Peak memory 256964 kb
Host smart-960ac284-3662-41c4-a5ea-3fca2543c68b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15805
50396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.1580550396
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.606154408
Short name T225
Test name
Test status
Simulation time 1708659256 ps
CPU time 50.02 seconds
Started Jun 07 07:44:54 PM PDT 24
Finished Jun 07 07:45:45 PM PDT 24
Peak memory 247796 kb
Host smart-65c7843d-f6d7-425f-9a4d-1f08552a4992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60615
4408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.606154408
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2490836514
Short name T544
Test name
Test status
Simulation time 44189930944 ps
CPU time 950.89 seconds
Started Jun 07 07:45:06 PM PDT 24
Finished Jun 07 08:00:59 PM PDT 24
Peak memory 272648 kb
Host smart-c178dea5-d9d5-4747-880f-e90216acea21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490836514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2490836514
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.4143449593
Short name T526
Test name
Test status
Simulation time 32499174751 ps
CPU time 724.96 seconds
Started Jun 07 07:45:00 PM PDT 24
Finished Jun 07 07:57:06 PM PDT 24
Peak memory 265200 kb
Host smart-4dbcadb7-1145-43a9-a73a-1ea90d34a3fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143449593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.4143449593
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1761059950
Short name T645
Test name
Test status
Simulation time 11172435749 ps
CPU time 468.16 seconds
Started Jun 07 07:45:06 PM PDT 24
Finished Jun 07 07:52:57 PM PDT 24
Peak memory 256568 kb
Host smart-8646d61a-a378-4a15-8a01-a3e84e55a15f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761059950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1761059950
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1256959402
Short name T81
Test name
Test status
Simulation time 28741356 ps
CPU time 4.14 seconds
Started Jun 07 07:44:55 PM PDT 24
Finished Jun 07 07:45:01 PM PDT 24
Peak memory 240488 kb
Host smart-fc622a8a-a300-4866-a0ab-3923b3eb7093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12569
59402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1256959402
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.620035901
Short name T538
Test name
Test status
Simulation time 1179967336 ps
CPU time 7.4 seconds
Started Jun 07 07:45:06 PM PDT 24
Finished Jun 07 07:45:15 PM PDT 24
Peak memory 252456 kb
Host smart-d214f715-2c5e-4a49-9c4f-487066c3d6b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62003
5901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.620035901
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.4264175439
Short name T289
Test name
Test status
Simulation time 585594048 ps
CPU time 19.06 seconds
Started Jun 07 07:45:02 PM PDT 24
Finished Jun 07 07:45:23 PM PDT 24
Peak memory 254920 kb
Host smart-6e838ce4-e843-404f-b7a6-4383c677753a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42641
75439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.4264175439
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2134676710
Short name T654
Test name
Test status
Simulation time 212616351 ps
CPU time 6.21 seconds
Started Jun 07 07:45:04 PM PDT 24
Finished Jun 07 07:45:13 PM PDT 24
Peak memory 248684 kb
Host smart-d3e0b708-e64f-4b5c-b901-d418048ac08e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21346
76710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2134676710
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.1239306302
Short name T268
Test name
Test status
Simulation time 134030744906 ps
CPU time 3803.78 seconds
Started Jun 07 07:44:55 PM PDT 24
Finished Jun 07 08:48:21 PM PDT 24
Peak memory 305724 kb
Host smart-12189fb7-907b-435f-a554-9b52485ac02a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239306302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.1239306302
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.2743578362
Short name T570
Test name
Test status
Simulation time 56415350432 ps
CPU time 1906.56 seconds
Started Jun 07 07:45:04 PM PDT 24
Finished Jun 07 08:16:52 PM PDT 24
Peak memory 289888 kb
Host smart-92f52a05-08b4-49a4-a6b2-7671923af9c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743578362 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.2743578362
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.140785103
Short name T118
Test name
Test status
Simulation time 68790294 ps
CPU time 3.11 seconds
Started Jun 07 07:45:03 PM PDT 24
Finished Jun 07 07:45:08 PM PDT 24
Peak memory 248940 kb
Host smart-5be170e3-61c8-419a-adc0-6d87ea38d4f7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=140785103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.140785103
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1050142450
Short name T4
Test name
Test status
Simulation time 13652024793 ps
CPU time 692.26 seconds
Started Jun 07 07:44:56 PM PDT 24
Finished Jun 07 07:56:31 PM PDT 24
Peak memory 272776 kb
Host smart-4d8ef367-3cde-4fa9-94dd-f3997df90df6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050142450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1050142450
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1294205031
Short name T506
Test name
Test status
Simulation time 748523500 ps
CPU time 10.84 seconds
Started Jun 07 07:45:06 PM PDT 24
Finished Jun 07 07:45:18 PM PDT 24
Peak memory 248752 kb
Host smart-ffb3e4c3-2365-4bbc-a3b1-bd3c09401528
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1294205031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1294205031
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.1569625393
Short name T672
Test name
Test status
Simulation time 947995807 ps
CPU time 74.58 seconds
Started Jun 07 07:45:06 PM PDT 24
Finished Jun 07 07:46:23 PM PDT 24
Peak memory 256684 kb
Host smart-063a2bfb-6199-4b86-8378-4522663771bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15696
25393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1569625393
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.4200543635
Short name T694
Test name
Test status
Simulation time 5900288043 ps
CPU time 66.8 seconds
Started Jun 07 07:44:57 PM PDT 24
Finished Jun 07 07:46:05 PM PDT 24
Peak memory 255188 kb
Host smart-323061f3-4af2-442e-abec-4f06eea32dc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42005
43635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.4200543635
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2216925541
Short name T342
Test name
Test status
Simulation time 153768404677 ps
CPU time 2367.51 seconds
Started Jun 07 07:45:07 PM PDT 24
Finished Jun 07 08:24:37 PM PDT 24
Peak memory 289308 kb
Host smart-1204a42d-f152-46ac-a6bd-ea83fb144abd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216925541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2216925541
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1588050349
Short name T437
Test name
Test status
Simulation time 39819030422 ps
CPU time 812.38 seconds
Started Jun 07 07:45:08 PM PDT 24
Finished Jun 07 07:58:43 PM PDT 24
Peak memory 272368 kb
Host smart-d142cf01-b24a-409a-a23f-a8a29469ed1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588050349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1588050349
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.122211617
Short name T493
Test name
Test status
Simulation time 5692911215 ps
CPU time 226.51 seconds
Started Jun 07 07:44:55 PM PDT 24
Finished Jun 07 07:48:44 PM PDT 24
Peak memory 248364 kb
Host smart-e11aa72c-c165-45c2-94cc-1276ac3a1efb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122211617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.122211617
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2510066224
Short name T461
Test name
Test status
Simulation time 336781015 ps
CPU time 22.85 seconds
Started Jun 07 07:45:01 PM PDT 24
Finished Jun 07 07:45:25 PM PDT 24
Peak memory 255956 kb
Host smart-f3d247e9-c98c-4d57-bd0b-1c6d968b663a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25100
66224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2510066224
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.4095648218
Short name T64
Test name
Test status
Simulation time 489212691 ps
CPU time 14.54 seconds
Started Jun 07 07:45:04 PM PDT 24
Finished Jun 07 07:45:20 PM PDT 24
Peak memory 248660 kb
Host smart-12208ee1-086f-4849-8954-3a224bfd1bd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40956
48218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.4095648218
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.3372137125
Short name T372
Test name
Test status
Simulation time 480325175 ps
CPU time 26.93 seconds
Started Jun 07 07:44:58 PM PDT 24
Finished Jun 07 07:45:26 PM PDT 24
Peak memory 256008 kb
Host smart-c7788868-42b7-4159-bf45-72981c473ff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33721
37125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.3372137125
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1633674007
Short name T38
Test name
Test status
Simulation time 111962136 ps
CPU time 9.55 seconds
Started Jun 07 07:45:03 PM PDT 24
Finished Jun 07 07:45:14 PM PDT 24
Peak memory 254952 kb
Host smart-105c2117-8199-43af-89d7-30db51869cfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16336
74007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1633674007
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.1250359366
Short name T200
Test name
Test status
Simulation time 42402151 ps
CPU time 3.52 seconds
Started Jun 07 07:45:09 PM PDT 24
Finished Jun 07 07:45:15 PM PDT 24
Peak memory 248900 kb
Host smart-b1818614-33e1-4c8d-abf8-0b2deaf0df1e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1250359366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1250359366
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.4268001277
Short name T545
Test name
Test status
Simulation time 13037008851 ps
CPU time 1119.66 seconds
Started Jun 07 07:45:00 PM PDT 24
Finished Jun 07 08:03:40 PM PDT 24
Peak memory 288664 kb
Host smart-d25547d2-3e71-48e4-bdee-42a62888c81a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268001277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.4268001277
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.998625145
Short name T104
Test name
Test status
Simulation time 1435067905 ps
CPU time 17.92 seconds
Started Jun 07 07:45:03 PM PDT 24
Finished Jun 07 07:45:22 PM PDT 24
Peak memory 248720 kb
Host smart-dbf8ec82-f26e-45fd-b6e8-ddcff9ce83b9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=998625145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.998625145
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2485672917
Short name T68
Test name
Test status
Simulation time 183247537 ps
CPU time 15.42 seconds
Started Jun 07 07:45:02 PM PDT 24
Finished Jun 07 07:45:19 PM PDT 24
Peak memory 254416 kb
Host smart-81f3c3a4-ba17-4dec-8eed-5498d209c897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24856
72917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2485672917
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.576738495
Short name T700
Test name
Test status
Simulation time 3192336742 ps
CPU time 58.58 seconds
Started Jun 07 07:45:08 PM PDT 24
Finished Jun 07 07:46:10 PM PDT 24
Peak memory 255800 kb
Host smart-667ab484-f621-46fd-9c2e-80358980e7f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57673
8495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.576738495
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.2847619132
Short name T310
Test name
Test status
Simulation time 28868902666 ps
CPU time 1839.58 seconds
Started Jun 07 07:45:02 PM PDT 24
Finished Jun 07 08:15:43 PM PDT 24
Peak memory 273212 kb
Host smart-51aaee0a-4c62-47fe-8799-7036770682e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847619132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.2847619132
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.3181468263
Short name T689
Test name
Test status
Simulation time 14620673504 ps
CPU time 1106.54 seconds
Started Jun 07 07:45:03 PM PDT 24
Finished Jun 07 08:03:32 PM PDT 24
Peak memory 271664 kb
Host smart-82166c75-e978-4fc3-b6a0-91878cec396c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181468263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.3181468263
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2424825820
Short name T704
Test name
Test status
Simulation time 24999938113 ps
CPU time 177.4 seconds
Started Jun 07 07:45:08 PM PDT 24
Finished Jun 07 07:48:08 PM PDT 24
Peak memory 253572 kb
Host smart-40c81471-a96d-40a5-9124-c976bb4dc99b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424825820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2424825820
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.243949620
Short name T519
Test name
Test status
Simulation time 476783974 ps
CPU time 17.16 seconds
Started Jun 07 07:44:55 PM PDT 24
Finished Jun 07 07:45:13 PM PDT 24
Peak memory 248740 kb
Host smart-ebdd56ef-f247-4090-ae01-08573a123a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24394
9620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.243949620
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3832600811
Short name T660
Test name
Test status
Simulation time 777337289 ps
CPU time 36.74 seconds
Started Jun 07 07:44:54 PM PDT 24
Finished Jun 07 07:45:32 PM PDT 24
Peak memory 247648 kb
Host smart-eed7a071-b67d-4dca-bfc2-b35b6f1a6eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38326
00811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3832600811
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.460581275
Short name T368
Test name
Test status
Simulation time 44244428 ps
CPU time 4.71 seconds
Started Jun 07 07:45:02 PM PDT 24
Finished Jun 07 07:45:08 PM PDT 24
Peak memory 239100 kb
Host smart-57c84d5b-c029-44e5-9446-b63e3b10069d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46058
1275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.460581275
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.1853131058
Short name T619
Test name
Test status
Simulation time 2066121382 ps
CPU time 33.02 seconds
Started Jun 07 07:44:55 PM PDT 24
Finished Jun 07 07:45:30 PM PDT 24
Peak memory 248708 kb
Host smart-aef833a3-f0f9-4986-bbfe-77b23b3aa6c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18531
31058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1853131058
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3524069362
Short name T515
Test name
Test status
Simulation time 64054633310 ps
CPU time 827.65 seconds
Started Jun 07 07:45:07 PM PDT 24
Finished Jun 07 07:58:57 PM PDT 24
Peak memory 265236 kb
Host smart-0711076e-978b-4774-a73f-4ebf96d49412
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524069362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3524069362
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.1256535061
Short name T193
Test name
Test status
Simulation time 23883232781 ps
CPU time 1380.21 seconds
Started Jun 07 07:45:03 PM PDT 24
Finished Jun 07 08:08:05 PM PDT 24
Peak memory 287036 kb
Host smart-2a64862c-7073-431b-8f83-caac9e3ca232
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256535061 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.1256535061
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.2028860515
Short name T199
Test name
Test status
Simulation time 34527641 ps
CPU time 3.36 seconds
Started Jun 07 07:45:05 PM PDT 24
Finished Jun 07 07:45:10 PM PDT 24
Peak memory 248904 kb
Host smart-cd1cf416-54d8-4242-84ca-3d72e1b40807
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2028860515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2028860515
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1213720323
Short name T93
Test name
Test status
Simulation time 15977597614 ps
CPU time 1470.63 seconds
Started Jun 07 07:45:00 PM PDT 24
Finished Jun 07 08:09:32 PM PDT 24
Peak memory 287476 kb
Host smart-5d28787b-c897-440c-aeb3-8ca2ee35e904
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213720323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1213720323
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.2483798602
Short name T478
Test name
Test status
Simulation time 227568407 ps
CPU time 7.2 seconds
Started Jun 07 07:45:08 PM PDT 24
Finished Jun 07 07:45:18 PM PDT 24
Peak memory 248652 kb
Host smart-496116d7-1e61-4603-a24b-b073ed360b06
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2483798602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2483798602
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.1370324051
Short name T238
Test name
Test status
Simulation time 2083674117 ps
CPU time 146.72 seconds
Started Jun 07 07:45:06 PM PDT 24
Finished Jun 07 07:47:35 PM PDT 24
Peak memory 251020 kb
Host smart-12d6fe5b-0b88-4e42-bb43-c29212ed3406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13703
24051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1370324051
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.2248920256
Short name T497
Test name
Test status
Simulation time 431433862 ps
CPU time 25.18 seconds
Started Jun 07 07:45:04 PM PDT 24
Finished Jun 07 07:45:31 PM PDT 24
Peak memory 255068 kb
Host smart-8e123916-575f-42ad-a637-07e2eda856eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22489
20256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2248920256
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2386750703
Short name T343
Test name
Test status
Simulation time 175470542992 ps
CPU time 2194.32 seconds
Started Jun 07 07:45:06 PM PDT 24
Finished Jun 07 08:21:43 PM PDT 24
Peak memory 289032 kb
Host smart-176ccde1-ae6b-470b-8348-e19571ff2820
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386750703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2386750703
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.383447060
Short name T446
Test name
Test status
Simulation time 9054112809 ps
CPU time 1009.8 seconds
Started Jun 07 07:45:02 PM PDT 24
Finished Jun 07 08:01:53 PM PDT 24
Peak memory 287632 kb
Host smart-6809869c-92dc-4c6e-b128-6c58fc829d33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383447060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.383447060
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.223639893
Short name T306
Test name
Test status
Simulation time 10142081196 ps
CPU time 382.94 seconds
Started Jun 07 07:45:07 PM PDT 24
Finished Jun 07 07:51:32 PM PDT 24
Peak memory 248460 kb
Host smart-0e174dcf-7f4a-47a8-8f71-4475e35e3f77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223639893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.223639893
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3154306843
Short name T360
Test name
Test status
Simulation time 849712554 ps
CPU time 56.11 seconds
Started Jun 07 07:45:10 PM PDT 24
Finished Jun 07 07:46:10 PM PDT 24
Peak memory 255760 kb
Host smart-4c149aa5-fe56-4a03-8891-9861906b1d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31543
06843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3154306843
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2959657751
Short name T102
Test name
Test status
Simulation time 871607155 ps
CPU time 53.18 seconds
Started Jun 07 07:45:00 PM PDT 24
Finished Jun 07 07:45:54 PM PDT 24
Peak memory 255800 kb
Host smart-2d1ea326-5b46-49b7-b572-4f81c0c54fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29596
57751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2959657751
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.1348199293
Short name T439
Test name
Test status
Simulation time 71377390 ps
CPU time 3.05 seconds
Started Jun 07 07:45:08 PM PDT 24
Finished Jun 07 07:45:14 PM PDT 24
Peak memory 240448 kb
Host smart-6b4b64e5-cdaa-4698-adb3-8aab2110c039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13481
99293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1348199293
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2725271759
Short name T96
Test name
Test status
Simulation time 659521449 ps
CPU time 28.66 seconds
Started Jun 07 07:45:02 PM PDT 24
Finished Jun 07 07:45:32 PM PDT 24
Peak memory 256868 kb
Host smart-d5c1f1ec-686a-42c5-b153-f4ab9d0ebfcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27252
71759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2725271759
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.797217493
Short name T575
Test name
Test status
Simulation time 20801027498 ps
CPU time 267.55 seconds
Started Jun 07 07:45:03 PM PDT 24
Finished Jun 07 07:49:32 PM PDT 24
Peak memory 256956 kb
Host smart-b26e6895-e006-4278-a639-653c69f90d1f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797217493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand
ler_stress_all.797217493
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.3951518553
Short name T205
Test name
Test status
Simulation time 15660388 ps
CPU time 2.39 seconds
Started Jun 07 07:45:09 PM PDT 24
Finished Jun 07 07:45:14 PM PDT 24
Peak memory 248916 kb
Host smart-2fb8f1d2-fd85-41e3-ab52-aa4d457023f8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3951518553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3951518553
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3397929322
Short name T528
Test name
Test status
Simulation time 110470937215 ps
CPU time 1631.5 seconds
Started Jun 07 07:45:11 PM PDT 24
Finished Jun 07 08:12:25 PM PDT 24
Peak memory 282560 kb
Host smart-13d48408-f539-4d16-8662-c84023c976d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397929322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3397929322
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2264505588
Short name T388
Test name
Test status
Simulation time 329539257 ps
CPU time 9.97 seconds
Started Jun 07 07:45:10 PM PDT 24
Finished Jun 07 07:45:23 PM PDT 24
Peak memory 248752 kb
Host smart-86b9803f-5cb5-403e-8bf2-927dc36726c1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2264505588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2264505588
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.2978995374
Short name T383
Test name
Test status
Simulation time 446134866 ps
CPU time 9.02 seconds
Started Jun 07 07:45:04 PM PDT 24
Finished Jun 07 07:45:15 PM PDT 24
Peak memory 253276 kb
Host smart-ddc8d431-676e-4344-bf1e-ee877ec0bc5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29789
95374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.2978995374
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.4257715549
Short name T41
Test name
Test status
Simulation time 700412480 ps
CPU time 26.07 seconds
Started Jun 07 07:45:09 PM PDT 24
Finished Jun 07 07:45:38 PM PDT 24
Peak memory 255688 kb
Host smart-1ee4578d-bc3e-4068-ae1c-e6cc99f0f28b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42577
15549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.4257715549
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.1981399253
Short name T345
Test name
Test status
Simulation time 37710919139 ps
CPU time 2254.68 seconds
Started Jun 07 07:45:04 PM PDT 24
Finished Jun 07 08:22:41 PM PDT 24
Peak memory 285268 kb
Host smart-b403d5a7-b143-4b90-9c21-653ce0ab91a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981399253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.1981399253
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.1867334215
Short name T395
Test name
Test status
Simulation time 84969442947 ps
CPU time 3164.89 seconds
Started Jun 07 07:45:10 PM PDT 24
Finished Jun 07 08:37:58 PM PDT 24
Peak memory 288380 kb
Host smart-090cc788-eb7f-41e8-ac7f-80260bdd2a72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867334215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.1867334215
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3171791384
Short name T585
Test name
Test status
Simulation time 2786936659 ps
CPU time 116.69 seconds
Started Jun 07 07:45:09 PM PDT 24
Finished Jun 07 07:47:08 PM PDT 24
Peak memory 248268 kb
Host smart-bcbf648a-7470-4575-8945-e84c27aaf1d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171791384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3171791384
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2068778967
Short name T659
Test name
Test status
Simulation time 358622651 ps
CPU time 21.56 seconds
Started Jun 07 07:45:08 PM PDT 24
Finished Jun 07 07:45:32 PM PDT 24
Peak memory 256096 kb
Host smart-d20f17ad-55c0-46d3-8874-dee901067e91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20687
78967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2068778967
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.4004761880
Short name T227
Test name
Test status
Simulation time 707399718 ps
CPU time 20.44 seconds
Started Jun 07 07:45:08 PM PDT 24
Finished Jun 07 07:45:31 PM PDT 24
Peak memory 247700 kb
Host smart-bfbebd4d-51d9-4839-843a-e3256eb380e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40047
61880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.4004761880
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.3447886346
Short name T77
Test name
Test status
Simulation time 501113251 ps
CPU time 17.5 seconds
Started Jun 07 07:45:03 PM PDT 24
Finished Jun 07 07:45:23 PM PDT 24
Peak memory 248648 kb
Host smart-aa1767f2-38b8-466e-a9a0-b170e8928df1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34478
86346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3447886346
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.915486369
Short name T418
Test name
Test status
Simulation time 260125004 ps
CPU time 12.7 seconds
Started Jun 07 07:45:08 PM PDT 24
Finished Jun 07 07:45:23 PM PDT 24
Peak memory 248740 kb
Host smart-30a9c6e3-5c97-41a4-9c6c-541a27f38932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91548
6369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.915486369
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1228581144
Short name T52
Test name
Test status
Simulation time 193674871759 ps
CPU time 2217.07 seconds
Started Jun 07 07:45:12 PM PDT 24
Finished Jun 07 08:22:13 PM PDT 24
Peak memory 284348 kb
Host smart-a96593e8-ba7e-4446-8b95-142d02b3e137
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228581144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1228581144
Directory /workspace/9.alert_handler_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%