Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	61085	1			T13	8		T6	12		T39	29
class_i[0x1]	62147	1			T3	5		T13	4111		T6	704
class_i[0x2]	47766	1			T12	303		T6	138		T20	167
class_i[0x3]	57818	1			T15	3		T21	568		T47	842

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	55440	1			T3	1		T12	31		T13	1116
alert[0x1]	59043	1			T3	2		T12	231		T13	1070
alert[0x2]	58317	1			T12	28		T13	999		T6	192
alert[0x3]	56016	1			T3	2		T12	13		T13	934

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

228540

1

T12

303

T13

4119

T6

854

esc_ping_fail

276

1

T3

5

T14

8

T15

9

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	55361	1			T12	31		T13	1116		T6	224
esc_integrity_fail	alert[0x1]	58980	1			T12	231		T13	1070		T6	258
esc_integrity_fail	alert[0x2]	58251	1			T12	28		T13	999		T6	192
esc_integrity_fail	alert[0x3]	55948	1			T12	13		T13	934		T6	180
esc_ping_fail	alert[0x0]	79	1			T3	1		T14	3		T15	1
esc_ping_fail	alert[0x1]	63	1			T3	2		T14	1		T15	2
esc_ping_fail	alert[0x2]	66	1			T14	1		T15	3		T191	2
esc_ping_fail	alert[0x3]	68	1			T3	2		T14	3		T15	3

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	61037	1			T13	8		T6	12		T39	29
esc_integrity_fail	class_i[0x1]	62072	1			T13	4111		T6	704		T20	102
esc_integrity_fail	class_i[0x2]	47715	1			T12	303		T6	138		T20	167
esc_integrity_fail	class_i[0x3]	57716	1			T15	1		T21	568		T47	842
esc_ping_fail	class_i[0x0]	48	1			T15	6		T286	6		T282	1
esc_ping_fail	class_i[0x1]	75	1			T3	5		T14	7		T15	1
esc_ping_fail	class_i[0x2]	51	1			T14	1		T23	7		T280	7
esc_ping_fail	class_i[0x3]	102	1			T15	2		T191	7		T278	9