Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	634186842	0	0	621
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	634186842	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	634186842	634012009	0	0
tb.dut.CheckAccuCntDw	0	0	621	621	0	0
tb.dut.CheckEscCntDw	0	0	621	621	0	0
tb.dut.CheckNAlerts	0	0	621	621	0	0
tb.dut.CheckNClasses	0	0	621	621	0	0
tb.dut.CheckNEscSev	0	0	621	621	0	0
tb.dut.CrashdumpKnownO_A	0	0	634186842	634012009	0	0
tb.dut.EdnKnownO_A	0	0	634186842	634012009	0	0
tb.dut.EscPKnownO_A	0	0	634186842	634012009	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	634186842	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	634186842	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	634186842	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	634186842	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	634186842	80	0	0
tb.dut.IrqAKnownO_A	0	0	634186842	634012009	0	0
tb.dut.IrqBKnownO_A	0	0	634186842	634012009	0	0
tb.dut.IrqCKnownO_A	0	0	634186842	634012009	0	0
tb.dut.IrqDKnownO_A	0	0	634186842	634012009	0	0
tb.dut.TlAReadyKnownO_A	0	0	634186842	634012009	0	0
tb.dut.TlDValidKnownO_A	0	0	634186842	634012009	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	658808397	2376960	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	658808397	14779	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	658808397	17863	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	658808397	16290	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	658808397	15383	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	658808397	14842	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	658808397	15659	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	658808397	15279	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	658808397	15152	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	658808397	14819	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	658808397	16986	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	658808397	14733	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	658808397	16909	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	658808397	15369	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	658808397	14822	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	658808397	15287	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	658808397	15058	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	658808397	15291	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	658808397	16313	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	658808397	15332	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	658808397	15198	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	658808397	14463	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	658808397	15157	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	658808397	15124	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	658808397	16233	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	658808397	15236	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	658808397	16663	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	658808397	15747	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	658808397	17061	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	658808397	15378	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	658808397	16341	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	658808397	14783	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	658808397	15198	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	658808397	15687	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	658808397	14648	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	658808397	17526	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	658808397	16246	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	658808397	16130	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	658808397	14896	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	658808397	16135	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	658808397	17967	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	658808397	16291	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	658808397	15576	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	658808397	16338	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	658808397	16716	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	658808397	15819	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	658808397	16980	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	658808397	16573	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	658808397	16043	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	658808397	16032	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	658808397	14783	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	658808397	15920	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	658808397	15366	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	658808397	16671	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	658808397	15980	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	658808397	15331	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	658808397	14895	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	658808397	15161	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	658808397	14903	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	658808397	15230	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	658808397	17031	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	658808397	16166	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	658808397	16340	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	658808397	15182	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	658808397	15879	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	658808397	15007	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	658808397	16982	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	658808397	16132	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	658808397	15119	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	658808397	16339	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	658808397	28279	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	658808397	15267	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	658808397	15730	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	658808397	16353	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	658808397	15993	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	658808397	15831	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	658808397	15656	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	658808397	16117	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	658808397	15380	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	634186842	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	634186842	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	634186842	80	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	634186842	5535	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	634186842	164425	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	634186842	369198359	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	634186842	305	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	634186842	856	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	634186842	46	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	634186842	448	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	633990674	285151086	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	634186842	946	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	634186842	929	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	634186842	911	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	634186842	892	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	634186842	786	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	634186842	89854	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	634186842	679	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	634186842	59	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	634186842	1429	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	634186842	1189	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	633988528	633915282	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	621	621	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	634186842	634012009	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	634186842	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	634186842	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	634186842	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	634186842	5141	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	634186842	154865	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	634186842	384911737	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	634186842	292	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	634186842	468	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	634186842	22	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	634186842	193	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	633990674	305181094	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	634186842	535	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	634186842	528	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	634186842	516	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	634186842	509	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	634186842	582	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	634186842	79236	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	634186842	499	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	634186842	58	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	634186842	1417	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	634186842	1177	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	633988528	633915282	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	621	621	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	634186842	634012009	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	634186842	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	634186842	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	634186842	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	634186842	2488	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	634186842	140990	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	634186842	380027792	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	634186842	288	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	634186842	486	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	634186842	8	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	634186842	222	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	633990674	311306984	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	634186842	557	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	634186842	547	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	634186842	540	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	634186842	533	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	634186842	448	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	634186842	59726	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	634186842	365	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	634186842	72	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	634186842	1399	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	634186842	1159	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	633988528	633915282	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	621	621	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	634186842	634012009	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	634186842	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	634186842	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	634186842	80	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	634186842	2859	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	634186842	225557	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	634186842	373257012	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	634186842	298	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	634186842	465	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	634186842	24	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	634186842	202	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	633990674	302106295	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	634186842	553	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	634186842	544	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	634186842	537	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	634186842	529	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	634186842	1158	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	634186842	124372	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	634186842	1059	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	634186842	73	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	634186842	1482	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	634186842	1242	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	633988528	633915282	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	621	621	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	634186842	634012009	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	658808397	122561214	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	658808397	658150978	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	658808397	658150978	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	658808397	168761912	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	658808397	658150978	0	0
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