Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	59	1			T12	1		T40	1		T22	1
class_index[0x1]	58	1			T6	1		T20	1		T21	1
class_index[0x2]	72	1			T12	1		T6	1		T70	1
class_index[0x3]	73	1			T6	1		T21	1		T22	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	100	1			T6	2		T70	1		T21	1
intr_timeout_cnt[1]	69	1			T20	1		T21	1		T47	1
intr_timeout_cnt[2]	24	1			T6	1		T22	1		T117	1
intr_timeout_cnt[3]	12	1			T105	1		T82	1		T57	1
intr_timeout_cnt[4]	16	1			T21	1		T47	1		T79	1
intr_timeout_cnt[5]	8	1			T12	2		T79	1		T219	1
intr_timeout_cnt[6]	9	1			T47	1		T53	1		T232	1
intr_timeout_cnt[7]	7	1			T109	1		T99	1		T96	1
intr_timeout_cnt[8]	10	1			T105	1		T55	1		T95	1
intr_timeout_cnt[9]	7	1			T40	1		T57	2		T95	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x2]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[5]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	22	1			T77	1		T55	1		T92	1
class_index[0x0]	intr_timeout_cnt[1]	16	1			T22	1		T50	1		T57	1
class_index[0x0]	intr_timeout_cnt[2]	4	1			T55	1		T233	1		T234	1
class_index[0x0]	intr_timeout_cnt[3]	2	1			T57	1		T235	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	3	1			T84	1		T96	1		T236	1
class_index[0x0]	intr_timeout_cnt[5]	3	1			T12	1		T219	1		T122	1
class_index[0x0]	intr_timeout_cnt[6]	1	1			T237	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	1	1			T238	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[8]	3	1			T127	1		T239	1		T240	1
class_index[0x0]	intr_timeout_cnt[9]	4	1			T40	1		T57	2		T95	1
class_index[0x1]	intr_timeout_cnt[0]	23	1			T21	1		T81	1		T108	1
class_index[0x1]	intr_timeout_cnt[1]	13	1			T20	1		T80	1		T55	1
class_index[0x1]	intr_timeout_cnt[2]	4	1			T6	1		T55	1		T241	1
class_index[0x1]	intr_timeout_cnt[3]	1	1			T82	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[4]	1	1			T242	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[5]	4	1			T79	1		T243	1		T244	1
class_index[0x1]	intr_timeout_cnt[6]	5	1			T47	1		T53	1		T114	1
class_index[0x1]	intr_timeout_cnt[7]	2	1			T99	1		T245	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	3	1			T127	2		T103	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	2	1			T96	1		T89	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	27	1			T6	1		T70	1		T47	1
class_index[0x2]	intr_timeout_cnt[1]	20	1			T47	1		T73	1		T34	1
class_index[0x2]	intr_timeout_cnt[2]	9	1			T22	1		T57	2		T109	1
class_index[0x2]	intr_timeout_cnt[3]	4	1			T219	2		T99	1		T225	1
class_index[0x2]	intr_timeout_cnt[4]	6	1			T21	1		T47	1		T79	1
class_index[0x2]	intr_timeout_cnt[5]	1	1			T12	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	1	1			T245	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	2	1			T241	1		T246	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	2	1			T105	1		T122	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	28	1			T6	1		T22	1		T50	1
class_index[0x3]	intr_timeout_cnt[1]	20	1			T21	1		T50	2		T80	1
class_index[0x3]	intr_timeout_cnt[2]	7	1			T117	1		T83	1		T99	1
class_index[0x3]	intr_timeout_cnt[3]	5	1			T105	1		T247	1		T248	2
class_index[0x3]	intr_timeout_cnt[4]	6	1			T96	1		T249	1		T250	1
class_index[0x3]	intr_timeout_cnt[6]	2	1			T232	1		T238	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	2	1			T109	1		T96	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	2	1			T55	1		T95	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T245	1		-	-		-	-