Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	340616	1			T1	27		T2	31		T3	31
all_values[1]	340616	1			T1	27		T2	31		T3	31
all_values[2]	340616	1			T1	27		T2	31		T3	31
all_values[3]	340616	1			T1	27		T2	31		T3	31

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

678426

1

T1

61

T2

63

T10

6

auto[1]

684038

1

T1

47

T2

61

T3

124

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

814833

1

T1

108

T2

109

T3

109

auto[1]

547631

1

T2

15

T3

15

T10

1

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	99087	1			T1	21		T2	8		T10	2
all_values[0]	auto[0]	auto[1]	69954	1			T2	7		T10	1		T11	6
all_values[0]	auto[1]	auto[0]	101010	1			T1	6		T2	8		T3	31
all_values[0]	auto[1]	auto[1]	70565	1			T2	8		T11	4		T12	5
all_values[1]	auto[0]	auto[0]	102498	1			T1	14		T2	21		T11	4
all_values[1]	auto[0]	auto[1]	67669	1			T11	4		T12	4		T13	378
all_values[1]	auto[1]	auto[0]	103277	1			T1	13		T2	10		T3	17
all_values[1]	auto[1]	auto[1]	67172	1			T3	14		T11	6		T12	7
all_values[2]	auto[0]	auto[0]	101326	1			T1	16		T2	17		T10	3
all_values[2]	auto[0]	auto[1]	68213	1			T11	4		T12	8		T13	401
all_values[2]	auto[1]	auto[0]	102820	1			T1	11		T2	14		T3	30
all_values[2]	auto[1]	auto[1]	68257	1			T3	1		T11	6		T12	4
all_values[3]	auto[0]	auto[0]	101821	1			T1	10		T2	10		T11	5
all_values[3]	auto[0]	auto[1]	67858	1			T11	4		T12	5		T13	384
all_values[3]	auto[1]	auto[0]	102994	1			T1	17		T2	21		T3	31
all_values[3]	auto[1]	auto[1]	67943	1			T11	6		T12	6		T13	419