Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	340616	1			T1	27		T2	31		T3	31
all_pins[1]	340616	1			T1	27		T2	31		T3	31
all_pins[2]	340616	1			T1	27		T2	31		T3	31
all_pins[3]	340616	1			T1	27		T2	31		T3	31

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1088527	1			T1	108		T2	116		T3	109
values[0x1]	273937	1			T2	8		T3	15		T11	22
transitions[0x0=>0x1]	181575	1			T2	8		T3	15		T11	12
transitions[0x1=>0x0]	181830	1			T2	8		T3	15		T11	13

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	270051	1			T1	27		T2	23		T3	31
all_pins[0]	values[0x1]	70565	1			T2	8		T11	4		T12	5
all_pins[0]	transitions[0x0=>0x1]	69949	1			T2	8		T11	3		T12	2
all_pins[0]	transitions[0x1=>0x0]	67582	1			T11	6		T12	4		T13	419
all_pins[1]	values[0x0]	273444	1			T1	27		T2	31		T3	17
all_pins[1]	values[0x1]	67172	1			T3	14		T11	6		T12	7
all_pins[1]	transitions[0x0=>0x1]	36676	1			T3	14		T11	4		T12	5
all_pins[1]	transitions[0x1=>0x0]	40069	1			T2	8		T11	2		T12	3
all_pins[2]	values[0x0]	272359	1			T1	27		T2	31		T3	30
all_pins[2]	values[0x1]	68257	1			T3	1		T11	6		T12	4
all_pins[2]	transitions[0x0=>0x1]	37798	1			T3	1		T11	3		T12	2
all_pins[2]	transitions[0x1=>0x0]	36713	1			T3	14		T11	3		T12	5
all_pins[3]	values[0x0]	272673	1			T1	27		T2	31		T3	31
all_pins[3]	values[0x1]	67943	1			T11	6		T12	6		T13	419
all_pins[3]	transitions[0x0=>0x1]	37152	1			T11	2		T12	4		T13	206
all_pins[3]	transitions[0x1=>0x0]	37466	1			T3	1		T11	2		T12	2