Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	272	1			T170	7		T171	7		T172	4
all_values[1]	272	1			T170	7		T171	7		T172	4
all_values[2]	272	1			T170	7		T171	7		T172	4
all_values[3]	272	1			T170	7		T171	7		T172	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

603

1

T170

11

T171

18

T172

13

auto[1]

485

1

T170

17

T171

10

T172

3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

429

1

T170

3

T171

11

T172

5

auto[1]

659

1

T170

25

T171

17

T172

11

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

649

1

T170

13

T171

15

T172

10

auto[1]

439

1

T170

15

T171

13

T172

6

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

55

1

T171

1

T172

1

T329

2

all_values[0]

auto[0]

auto[0]

auto[1]

29

1

T170

1

T329

1

T229

1

all_values[0]

auto[0]

auto[1]

auto[0]

47

1

T171

1

T329

1

T330

1

all_values[0]

auto[0]

auto[1]

auto[1]

32

1

T170

3

T171

2

T329

1

all_values[0]

auto[1]

auto[0]

auto[1]

68

1

T170

1

T171

2

T172

3

all_values[0]

auto[1]

auto[1]

auto[1]

41

1

T170

2

T171

1

T329

1

all_values[1]

auto[0]

auto[0]

auto[0]

69

1

T170

1

T171

2

T172

1

all_values[1]

auto[0]

auto[0]

auto[1]

18

1

T331

1

T332

1

T333

1

all_values[1]

auto[0]

auto[1]

auto[0]

47

1

T330

1

T334

1

T331

3

all_values[1]

auto[0]

auto[1]

auto[1]

30

1

T170

1

T172

2

T330

1

all_values[1]

auto[1]

auto[0]

auto[1]

51

1

T170

1

T171

2

T329

2

all_values[1]

auto[1]

auto[1]

auto[1]

57

1

T170

4

T171

3

T172

1

all_values[2]

auto[0]

auto[0]

auto[0]

62

1

T171

3

T172

1

T329

5

all_values[2]

auto[0]

auto[0]

auto[1]

39

1

T170

2

T172

2

T329

1

all_values[2]

auto[0]

auto[1]

auto[0]

35

1

T330

3

T335

1

T334

1

all_values[2]

auto[0]

auto[1]

auto[1]

20

1

T170

1

T171

1

T336

1

all_values[2]

auto[1]

auto[0]

auto[1]

72

1

T170

3

T171

2

T172

1

all_values[2]

auto[1]

auto[1]

auto[1]

44

1

T170

1

T171

1

T335

2

all_values[3]

auto[0]

auto[0]

auto[0]

57

1

T170

1

T171

4

T172

2

all_values[3]

auto[0]

auto[0]

auto[1]

22

1

T170

1

T172

1

T336

2

all_values[3]

auto[0]

auto[1]

auto[0]

57

1

T170

1

T329

2

T330

1

all_values[3]

auto[0]

auto[1]

auto[1]

30

1

T170

1

T171

1

T329

2

all_values[3]

auto[1]

auto[0]

auto[1]

61

1

T171

2

T172

1

T329

1

all_values[3]

auto[1]

auto[1]

auto[1]

45

1

T170

3

T329

1

T330

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal