Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	78585	1			T13	568		T16	446		T17	1319
accum_cnt_1000	197019	1			T12	15		T13	502		T16	414
accum_cnt_100	22439	1			T2	12		T13	31		T16	24
accum_cnt_50	54828	1			T2	9		T11	11		T12	7
accum_cnt_10	201518	1			T2	2		T3	20		T10	1
accum_cnt_0	414212	1			T1	72		T2	69		T3	72

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	251633	1			T1	18		T2	23		T3	23
class_index[0x1]	251633	1			T1	18		T2	23		T3	23
class_index[0x2]	251633	1			T1	18		T2	23		T3	23
class_index[0x3]	251633	1			T1	18		T2	23		T3	23

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	17796	1			T16	446		T44	57		T21	92
class_index[0x0]	accum_cnt_1000	47836	1			T16	414		T6	104		T20	29
class_index[0x0]	accum_cnt_100	6200	1			T2	12		T16	24		T6	73
class_index[0x0]	accum_cnt_50	14967	1			T2	9		T11	8		T13	1213
class_index[0x0]	accum_cnt_10	60547	1			T2	2		T10	1		T11	9
class_index[0x0]	accum_cnt_0	95605	1			T1	18		T3	23		T10	1
class_index[0x1]	accum_cnt_2000	18185	1			T17	497		T19	632		T44	186
class_index[0x1]	accum_cnt_1000	49161	1			T6	40		T20	11		T17	455
class_index[0x1]	accum_cnt_100	5772	1			T6	93		T20	27		T17	27
class_index[0x1]	accum_cnt_50	12090	1			T6	114		T20	38		T17	25
class_index[0x1]	accum_cnt_10	51639	1			T3	20		T11	14		T12	13
class_index[0x1]	accum_cnt_0	106613	1			T1	18		T2	23		T3	3
class_index[0x2]	accum_cnt_2000	21916	1			T17	333		T18	441		T19	513
class_index[0x2]	accum_cnt_1000	49596	1			T12	15		T20	7		T17	733
class_index[0x2]	accum_cnt_100	5127	1			T6	10		T20	3		T17	43
class_index[0x2]	accum_cnt_50	15116	1			T6	41		T17	35		T18	21
class_index[0x2]	accum_cnt_10	42819	1			T12	2		T6	12		T20	2
class_index[0x2]	accum_cnt_0	111875	1			T1	18		T2	23		T3	23
class_index[0x3]	accum_cnt_2000	20688	1			T13	568		T17	489		T18	328
class_index[0x3]	accum_cnt_1000	50426	1			T13	502		T20	17		T17	448
class_index[0x3]	accum_cnt_100	5340	1			T13	31		T20	22		T17	26
class_index[0x3]	accum_cnt_50	12655	1			T11	3		T12	7		T13	24
class_index[0x3]	accum_cnt_10	46513	1			T11	10		T12	12		T13	8
class_index[0x3]	accum_cnt_0	100119	1			T1	18		T2	23		T3	23